gensoc: use add_verilog_include_path

diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py
index 436cd4fd5944963d380ed148dff0190e13f86977..615091a047c5c4d6429b188c69df15ad7004a0b9 100644 (file)
--- a/misoclib/gensoc/__init__.py
+++ b/misoclib/gensoc/__init__.py
@@ -66,7 +66,7 @@ class GenSoC(Module):
                        "lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
                        "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
                        "lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
-               platform.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
+               platform.add_verilog_include_path(os.path.join("verilog", "lm32"))
 
        def register_rom(self, rom_wb_if, bios_size=0x8000):
                if self._rom_registered: