Accept disable case for SVA liveness properties.

diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc
index 632043b6f091ef22e3b10e3f5a25481f3b087206..1f5da1b1d9572b5583cfec8ddb77ea8071ef0553 100644 (file)
--- a/frontends/verific/verificsva.cc
+++ b/frontends/verific/verificsva.cc
@@ -1759,6 +1759,11 @@ struct VerificSvaImporter
                                                clocking.addDff(NEW_ID, sig_en, sig_en_q, State::S0);
                                        }
 
+                                       // accept in disable case
+
+                                       if (clocking.disable_sig != State::S0)
+                                               sig_a_q = module->Or(NEW_ID, sig_a_q, clocking.disable_sig);
+
                                        // generate fair/live cell
 
                                        RTLIL::Cell *c = nullptr;