Move wishbone arbiter out of the core

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/core.vhdl b/core.vhdl
index 878bd4587407ac8a3c9e6e9626d0aed966edfbcb..01a96696f781ef758f96c032f3a7e2002539c77a 100644 (file)
--- a/core.vhdl
+++ b/core.vhdl
@@ -14,8 +14,11 @@ entity core is
                clk          : in std_logic;
                rst          : in std_logic;
 
-               wishbone_in  : in wishbone_slave_out;
-               wishbone_out : out wishbone_master_out;
+               wishbone_insn_in  : in wishbone_slave_out;
+               wishbone_insn_out : out wishbone_master_out;
+
+               wishbone_data_in  : in wishbone_slave_out;
+               wishbone_data_out : out wishbone_master_out;
 
                -- Added for debug, ghdl doesn't support external names unfortunately
                registers    : out regfile;
@@ -56,12 +59,6 @@ architecture behave of core is
        signal decode2_to_multiply: Decode2ToMultiplyType;
        signal multiply_to_writeback: MultiplyToWritebackType;
 
-       -- wishbone signals
-       signal wishbone_data_in : wishbone_slave_out;
-       signal wishbone_data_out : wishbone_master_out;
-       signal wishbone_insn_in : wishbone_slave_out;
-       signal wishbone_insn_out : wishbone_master_out;
-
        -- local signals
        signal fetch_enable: std_ulogic := '0';
        signal complete: std_ulogic;
@@ -124,11 +121,6 @@ begin
                          m_in => multiply_to_writeback, w_out => writeback_to_register_file,
                          c_out => writeback_to_cr_file, complete_out => complete);
 
-       wishbone_arbiter_0: entity work.wishbone_arbiter
-               port map (clk => clk, rst => rst, wb1_in => wishbone_data_out, wb1_out => wishbone_data_in,
-                         wb2_in => wishbone_insn_out, wb2_out => wishbone_insn_in, wb_out => wishbone_out,
-                         wb_in => wishbone_in);
-
        -- Only single issue until we add bypass support
        single_issue_0: process(clk)
        begin

diff --git a/core_tb.vhdl b/core_tb.vhdl
index 15626bab579235ab001bc7aa60574c6d7377f012..501cbfb2f1ab88c4f75fc767e175937a95c05835 100644 (file)
--- a/core_tb.vhdl
+++ b/core_tb.vhdl
@@ -13,6 +13,12 @@ end core_tb;
 architecture behave of core_tb is
        signal clk, rst: std_logic;
 
+       signal wishbone_dcore_in : wishbone_slave_out;
+       signal wishbone_dcore_out : wishbone_master_out;
+
+       signal wishbone_icore_in : wishbone_slave_out;
+       signal wishbone_icore_out : wishbone_master_out;
+
        signal wishbone_core_in : wishbone_slave_out;
        signal wishbone_core_out : wishbone_master_out;
 
@@ -30,8 +36,12 @@ architecture behave of core_tb is
 begin
        core_0: entity work.core
                generic map (SIM => true)
-               port map (clk => clk, rst => rst, wishbone_in => wishbone_core_in,
-                         wishbone_out => wishbone_core_out, registers => registers, terminate_out => terminate);
+           port map (clk => clk, rst => rst,
+                     wishbone_insn_in => wishbone_icore_in,
+                     wishbone_insn_out => wishbone_icore_out,
+                     wishbone_data_in => wishbone_dcore_in,
+                     wishbone_data_out => wishbone_dcore_out,
+                     registers => registers, terminate_out => terminate);
 
        simple_ram_0: entity work.simple_ram_behavioural
                generic map ( filename => "simple_ram_behavioural.bin", size => 524288)
@@ -41,6 +51,12 @@ begin
                port map ( clk => clk, reset => rst, wishbone_in => wishbone_uart_out, wishbone_out => wishbone_uart_in);
 
 
+       wishbone_arbiter_0: entity work.wishbone_arbiter
+               port map (clk => clk, rst => rst,
+                         wb1_in => wishbone_dcore_out, wb1_out => wishbone_dcore_in,
+                         wb2_in => wishbone_icore_out, wb2_out => wishbone_icore_in,
+                         wb_out => wishbone_core_out, wb_in => wishbone_core_in);
+
        bus_process: process(wishbone_core_out, wishbone_ram_in, wishbone_uart_in)
          -- Selected slave
          type slave_type is (SLAVE_UART, SLAVE_MEMORY, SLAVE_NONE);

diff --git a/fpga/soc.vhdl b/fpga/soc.vhdl
index 63c7811b9fa2a334053ca7d545c93150f639cf66..ea6e3e55edd0d6e20475dd0c6f447ed55b71e6e3 100644 (file)
--- a/fpga/soc.vhdl
+++ b/fpga/soc.vhdl
@@ -26,9 +26,13 @@ end entity soc;
 
 architecture behaviour of soc is
 
-    -- wishbone signals:
+    -- Wishbone master signals:
     signal wishbone_proc_out: wishbone_master_out;
     signal wishbone_proc_in: wishbone_slave_out;
+    signal wishbone_dcore_in : wishbone_slave_out;
+    signal wishbone_dcore_out : wishbone_master_out;
+    signal wishbone_icore_in : wishbone_slave_out;
+    signal wishbone_icore_out : wishbone_master_out;
 
     -- Processor signals:
     signal processor_adr_out : std_logic_vector(63 downto 0);
@@ -128,9 +132,22 @@ begin
        port map(
            clk => system_clk,
            rst => rst,
+           wishbone_insn_in => wishbone_icore_in,
+           wishbone_insn_out => wishbone_icore_out,
+           wishbone_data_in => wishbone_dcore_in,
+           wishbone_data_out => wishbone_dcore_out
+           );
 
-           wishbone_out => wishbone_proc_out,
-           wishbone_in => wishbone_proc_in
+    wishbone_arbiter_0: entity work.wishbone_arbiter
+       port map(
+           clk => system_clk,
+           rst => rst,
+           wb1_in => wishbone_dcore_out,
+           wb1_out => wishbone_dcore_in,
+           wb2_in => wishbone_icore_out,
+           wb2_out => wishbone_icore_in,
+           wb_out => wishbone_proc_out,
+           wb_in => wishbone_proc_in
            );
     processor_adr_out <= wishbone_proc_out.adr;
     processor_dat_out <= wishbone_proc_out.dat;