rename shadow_address to shadow_base (more appropriate) and use | instead of + (as...

diff --git a/misoclib/com/litepcie/example_designs/targets/dma.py b/misoclib/com/litepcie/example_designs/targets/dma.py
index 512e24e2b0b2ecceb8949a6ed891515e38f45a72..f129135547c09d27a6b11c2d53e4456acb6e4288 100644 (file)
--- a/misoclib/com/litepcie/example_designs/targets/dma.py
+++ b/misoclib/com/litepcie/example_designs/targets/dma.py
@@ -62,7 +62,7 @@ class PCIeDMASoC(SoC, AutoCSR):
         clk_freq = 125*1000000
         SoC.__init__(self, platform, clk_freq,
             cpu_type="none",
-            shadow_address=0x00000000,
+            shadow_base=0x00000000,
             with_csr=True, csr_data_width=32,
             with_uart=False,
             with_identifier=True,

diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py
index 3e3e1ffff80c107c6957469d24bee6869e9f03b1..217ce1378eaa78cb86fc935a4282b5fe0b1c13f4 100644 (file)
--- a/misoclib/soc/__init__.py
+++ b/misoclib/soc/__init__.py
@@ -39,7 +39,7 @@ class SoC(Module):
                 integrated_rom_size=0,
                 integrated_sram_size=4096,
                 integrated_main_ram_size=0,
-                shadow_address=0x80000000,
+                shadow_base=0x80000000,
                 with_csr=True, csr_data_width=8, csr_address_width=14,
                 with_uart=True, uart_baudrate=115200,
                 with_identifier=True,
@@ -61,7 +61,7 @@ class SoC(Module):
 
         self.with_identifier = with_identifier
 
-        self.shadow_address = shadow_address
+        self.shadow_base = shadow_base
 
         self.with_csr = with_csr
         self.csr_data_width = csr_data_width
@@ -193,9 +193,9 @@ class SoC(Module):
                 data_width=self.csr_data_width, address_width=self.csr_address_width)
             self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
             for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
-                self.add_csr_region(name, self.mem_map["csr"]+self.shadow_address+0x800*mapaddr, self.csr_data_width, csrs)
+                self.add_csr_region(name, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, csrs)
             for name, memory, mapaddr, mmap in self.csrbankarray.srams:
-                self.add_csr_region(name + "_" + memory.name_override, self.mem_map["csr"]+self.shadow_address+0x800*mapaddr, self.csr_data_width, memory)
+                self.add_csr_region(name + "_" + memory.name_override, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, memory)
 
         # Interrupts
         if hasattr(self.cpu_or_bridge, "interrupt"):

diff --git a/targets/kc705.py b/targets/kc705.py
index 8f65fa91174e1f926d4bc263d78b89e119e85100..6884f3f6e5eff4d589ef22033109855ba86b833c 100644 (file)
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -127,6 +127,6 @@ class MiniSoC(BaseSoC):
         self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), clk_freq=self.clk_freq)
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"]+self.shadow_address, 0x2000)
+        self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 
 default_subtarget = BaseSoC

diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index 9e5eaf1b0df1d3df05bbfdd9ce05e39bce4753b6..5943b2f23dd4a09e2bc87ca0781a9afc332437e0 100644 (file)
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -101,7 +101,7 @@ class MiniSoC(BaseSoC):
                                             platform.request("eth"))
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"]+self.shadow_address, 0x2000)
+        self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 
 
 def get_vga_dvi(platform):

diff --git a/targets/simple.py b/targets/simple.py
index 89bd57e2bdd6b6b01bb5b855e932bd078e30b164..3d2568483ac7f9b719ca33dc6cdcf05268ca8ac2 100644 (file)
--- a/targets/simple.py
+++ b/targets/simple.py
@@ -43,6 +43,6 @@ class MiniSoC(BaseSoC):
                                             interface="wishbone",
                                             with_preamble_crc=False)
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"]+self.shadow_address, 0x2000)
+        self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 
 default_subtarget = BaseSoC