arc-dis.c \
arc-ext.c \
arc-opc.c \
+ arc64-opc.c \
arm-dis.c \
avr-dis.c \
bfin-dis.c \
arc-dis.c \
arc-ext.c \
arc-opc.c \
+ arc64-opc.c \
arm-dis.c \
avr-dis.c \
bfin-dis.c \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arc-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arc-ext.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arc-opc.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arc64-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arm-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/avr-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bfin-dis.Plo@am__quote@
/* Instruction length w/o limm field. */
unsigned insn_len;
- /* TRUE if we have limm. */
+ /* true if we have limm. */
bool limm_p;
/* LIMM value, if exists. */
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
- "r24", "r25", "gp", "fp", "sp", "ilink", "r30", "blink",
+ "r24", "r25", "r26", "fp", "sp", "ilink", "r30", "blink",
"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
"r56", "r57", "r58", "r59", "lp_count", "reserved", "LIMM", "pcl"
};
+typedef struct regmod
+{
+ const unsigned int index;
+ const unsigned int isa;
+ const char *rname;
+} regmod_t;
+
+static regmod_t regmods[] =
+{
+ { 26, ARC_OPCODE_ARCV1 | ARC_OPCODE_ARCV2, "gp" },
+ { 29, ARC_OPCODE_ARCV1, "ilink1" },
+ { 30, ARC_OPCODE_ARCV1, "ilink2" },
+ { 0, ARC_OPCODE_NONE, 0 }
+};
+
+static const char * const fpnames[32] =
+{
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
+};
+
static const char * const addrtypenames[ARC_NUM_ADDRTYPES] =
{
"bd", "jid", "lbd", "mbd", "sd", "sm", "xa", "xd",
static bool print_hex = false;
/* Macros section. */
-
#ifdef DEBUG
# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
#else
#define BITS(word,s,e) (((word) >> (s)) & ((1ull << ((e) - (s)) << 1) - 1))
#define OPCODE_32BIT_INSN(word) (BITS ((word), 27, 31))
+#define REG_PCL 63
+#define REG_LIMM 62
+#define REG_LIMM_S 30
+#define REG_U32 62
+#define REG_S32 60
+
/* Functions implementation. */
+static const char *
+getregname (unsigned int index, unsigned int isa_mask)
+{
+ regmod_t *iregmods = regmods;
+ while (iregmods->rname)
+ {
+ if (index == iregmods->index
+ && (isa_mask & iregmods->isa))
+ return iregmods->rname;
+ iregmods ++;
+ }
+
+ return regnames[index % 64];
+}
+
/* Initialize private data. */
static bool
init_arc_disasm_info (struct disassemble_info *info)
decodelist = t;
}
-/* Return TRUE if we need to skip the opcode from being
+/* Return true if we need to skip the opcode from being
disassembled. */
static bool
if (arc_opcode_len (opcode) != (int) insn_len)
continue;
- if ((insn & opcode->mask) != opcode->opcode)
+ if ((insn & opcode->mask) != (opcode->mask & opcode->opcode))
continue;
*has_limm = false;
/* Possible candidate, check the operands. */
for (opidx = opcode->operands; *opidx; opidx++)
{
- int value, limmind;
+ int value, slimmind;
const struct arc_operand *operand = &arc_operands[*opidx];
if (operand->flags & ARC_OPERAND_FAKE)
else
value = (insn >> operand->shift) & ((1ull << operand->bits) - 1);
- /* Check for LIMM indicator. If it is there, then make sure
- we pick the right format. */
- limmind = (isa_mask & ARC_OPCODE_ARCV2) ? 0x1E : 0x3E;
+ /* Check for (short) LIMM indicator. If it is there, then
+ make sure we pick the right format. */
+ slimmind = (isa_mask & ARC_OPCODE_ARCVx) ? REG_LIMM_S : REG_LIMM;
if (operand->flags & ARC_OPERAND_IR
&& !(operand->flags & ARC_OPERAND_LIMM))
- {
- if ((value == 0x3E && insn_len == 4)
- || (value == limmind && insn_len == 2))
- {
- invalid = true;
- break;
- }
- }
+ if ((value == REG_LIMM && insn_len == 4)
+ || (value == slimmind && insn_len == 2)
+ || (isa_mask & ARC_OPCODE_ARC64
+ && (value == REG_S32) && (insn_len == 4)))
+ {
+ invalid = true;
+ break;
+ }
if (operand->flags & ARC_OPERAND_LIMM
&& !(operand->flags & ARC_OPERAND_DUPLICATE))
for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
{
+ bool tmp = false;
const struct arc_flag_operand *flg_operand =
&arc_flag_operands[*flgopridx];
- value = (insn >> flg_operand->shift)
- & ((1 << flg_operand->bits) - 1);
+ if (cl_flags->extract)
+ value = (*cl_flags->extract)(insn, &tmp);
+ else
+ value = (insn >> flg_operand->shift)
+ & ((1 << flg_operand->bits) - 1);
if (value == flg_operand->code)
foundA = 1;
if (value)
the found opcode requires a LIMM then the LIMM value will be loaded into a
field of ITER.
- This function returns TRUE in almost all cases, FALSE is reserved to
+ This function returns true in almost all cases, false is reserved to
indicate an error (failing to find an opcode is not an error) a returned
- result of FALSE would indicate that the disassembler can't continue.
+ result of false would indicate that the disassembler can't continue.
- If no matching opcode is found then the returned result will be TRUE, the
+ If no matching opcode is found then the returned result will be true, the
value placed into OPCODE_RESULT will be NULL, ITER will be undefined, and
INSN_LEN will be unchanged.
- If a matching opcode is found, then the returned result will be TRUE, the
+ If a matching opcode is found, then the returned result will be true, the
opcode pointer is placed into OPCODE_RESULT, INSN_LEN will be increased by
4 if the instruction requires a LIMM, and the LIMM value will have been
loaded into a field of ITER. Finally, ITER will have been initialised so
struct arc_operand_iterator * iter)
{
const struct arc_opcode *opcode = NULL;
+ const struct arc_opcode *opcodeList = NULL;
bool needs_limm = false;
const extInstruction_t *einsn, *i;
unsigned limm = 0;
struct arc_disassemble_info *arc_infop = info->private_data;
+ opcodeList = arc_opcodes;
+
/* First, try the extension instructions. */
if (*insn_len == 4)
{
/* Then, try finding the first match in the opcode table. */
if (opcode == NULL)
- opcode = find_format_from_table (info, arc_opcodes, insn, *insn_len,
+ opcode = find_format_from_table (info, opcodeList, insn, *insn_len,
isa_mask, &needs_limm, true);
if (opcode != NULL && needs_limm)
if (!flg_operand->favail)
continue;
- value = (insn[0] >> flg_operand->shift)
- & ((1 << flg_operand->bits) - 1);
+ if (cl_flags->extract)
+ {
+ bool tmp = false;
+ value = (*cl_flags->extract)(insn[0], &tmp);
+ }
+ else
+ value = (insn[0] >> flg_operand->shift)
+ & ((1 << flg_operand->bits) - 1);
if (value == flg_operand->code)
{
/* FIXME!: print correctly nt/t flag. */
{
bfd_byte major_opcode = msb >> 3;
- switch (info->mach)
+ switch (info->arch)
{
- case bfd_mach_arc_arc700:
- /* The nps400 extension set requires this special casing of the
- instruction length calculation. Right now this is not causing any
- problems as none of the known extensions overlap in opcode space,
- but, if they ever do then we might need to start carrying
- information around in the elf about which extensions are in use. */
- if (major_opcode == 0xb)
- {
- bfd_byte minor_opcode = lsb & 0x1f;
+ case bfd_arch_arc:
+ switch (info->mach)
+ {
+ case bfd_mach_arc_arc700:
+ /* The nps400 extension set requires this special casing of
+ the instruction length calculation. Right now this is
+ not causing any problems as none of the known extensions
+ overlap in opcode space, but, if they ever do then we
+ might need to start carrying information around in the
+ elf about which extensions are in use. */
+ if (major_opcode == 0xb)
+ {
+ bfd_byte minor_opcode = lsb & 0x1f;
- if (minor_opcode < 4)
- return 6;
- else if (minor_opcode == 0x10 || minor_opcode == 0x11)
- return 8;
- }
- if (major_opcode == 0xa)
- {
- return 8;
- }
- /* Fall through. */
- case bfd_mach_arc_arc600:
- return (major_opcode > 0xb) ? 2 : 4;
+ if (minor_opcode < 4)
+ return 6;
+ else if (minor_opcode == 0x10 || minor_opcode == 0x11)
+ return 8;
+ }
+ if (major_opcode == 0xa)
+ {
+ return 8;
+ }
+ /* Fall through. */
+ case bfd_mach_arc_arc600:
+ return (major_opcode > 0xb) ? 2 : 4;
+ break;
+
+ case bfd_mach_arc_arcv2:
+ return (major_opcode > 0x7) ? 2 : 4;
+ break;
+
+ default:
+ return 0;
+ }
break;
- case bfd_mach_arc_arcv2:
- return (major_opcode > 0x7) ? 2 : 4;
+ case bfd_arch_arc64:
+ switch (info->mach)
+ {
+ case bfd_mach_arcv3_32:
+ case bfd_mach_arcv3_64:
+ if (major_opcode == 0x0b
+ || major_opcode == 0x0d
+ || major_opcode == 0x1c)
+ return 4;
+ return (major_opcode > 0x7) ? 2 : 4;
+
+ default:
+ return 0;
+ }
break;
default:
return value;
}
-/* Find the next operand, and the operands value from ITER. Return TRUE if
- there is another operand, otherwise return FALSE. If there is an
+/* Find the next operand, and the operands value from ITER. Return true if
+ there is another operand, otherwise return false. If there is an
operand returned then the operand is placed into OPERAND, and the value
into VALUE. If there is no operand returned then OPERAND and VALUE are
unchanged. */
}
#define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
- { #NAME, ARC_OPCODE_ARC600, "ARC600" }
+ { #NAME, ARC_OPCODE_ARC600, "ARC600" },
#define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
- { #NAME, ARC_OPCODE_ARC700, "ARC700" }
+ { #NAME, ARC_OPCODE_ARC700, "ARC700" },
#define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
- { #NAME, ARC_OPCODE_ARCv2EM, "ARC EM" }
+ { #NAME, ARC_OPCODE_ARCv2EM, "ARC EM" },
#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
- { #NAME, ARC_OPCODE_ARCv2HS, "ARC HS" }
-#define ARC_CPU_TYPE_NONE \
+ { #NAME, ARC_OPCODE_ARCv2HS, "ARC HS" },
+#define ARC_CPU_TYPE_A64x(NAME,EXTRA) \
+ { #NAME, ARC_OPCODE_ARC64, "ARC64" },
+#define ARC_CPU_TYPE_A32x(NAME,EXTRA) \
+ { #NAME, ARC_OPCODE_ARC64, "ARC32" },
+#define ARC_CPU_TYPE_NONE \
{ 0, 0, 0 }
/* A table of CPU names and opcode sets. */
bool open_braket;
int size;
const struct arc_operand *operand;
- int value, vpcl;
+ int value;
+ bfd_vma vpcl;
struct arc_operand_iterator iter;
struct arc_disassemble_info *arc_infop;
bool rpcl = false, rset = false;
if (info->section && info->section->owner)
header = elf_elfheader (info->section->owner);
- switch (info->mach)
+ switch (info->arch)
{
- case bfd_mach_arc_arc700:
- isa_mask = ARC_OPCODE_ARC700;
+ case bfd_arch_arc:
+ switch (info->mach)
+ {
+ case bfd_mach_arc_arc700:
+ isa_mask = ARC_OPCODE_ARC700;
+ break;
+
+ case bfd_mach_arc_arc600:
+ isa_mask = ARC_OPCODE_ARC600;
+ break;
+
+ case bfd_mach_arc_arcv2:
+ default:
+ isa_mask = ARC_OPCODE_ARCv2EM;
+ /* TODO: Perhaps remove definition of header since it is
+ only used at this location. */
+ if (header != NULL
+ && (header->e_flags & EF_ARC_MACH_MSK) == EF_ARC_CPU_ARCV2HS)
+ isa_mask = ARC_OPCODE_ARCv2HS;
+ break;
+ }
break;
- case bfd_mach_arc_arc600:
- isa_mask = ARC_OPCODE_ARC600;
+ case bfd_arch_arc64:
+ switch (info->mach)
+ {
+ case bfd_mach_arcv3_64:
+ isa_mask = ARC_OPCODE_ARC64;
+ break;
+
+ case bfd_mach_arcv3_32:
+ isa_mask = ARC_OPCODE_ARC32;
+ break;
+
+ default:
+ /* xgettext:c-format */
+ opcodes_error_handler (_("unrecognised arc64 disassembler \
+variant"));
+ return -1;
+ }
break;
- case bfd_mach_arc_arcv2:
default:
- isa_mask = ARC_OPCODE_ARCv2EM;
- /* TODO: Perhaps remove definition of header since it is only used at
- this location. */
- if (header != NULL
- && (header->e_flags & EF_ARC_MACH_MSK) == EF_ARC_CPU_ARCV2HS)
- isa_mask = ARC_OPCODE_ARCv2HS;
- break;
+ /* xgettext:c-format */
+ opcodes_error_handler (_("unrecognised disassembler architecture"));
+ return -1;
}
}
else
rpcl = true;
vpcl = value;
rset = true;
-
- info->target = (bfd_vma) (memaddr & ~3) + value;
+ if ((operand->flags & ARC_OPERAND_LIMM)
+ && (operand->flags & ARC_OPERAND_ALIGNED32))
+ vpcl <<= 2;
+ info->target = (bfd_vma) (memaddr & ~3) + vpcl;
}
else if (!(operand->flags & ARC_OPERAND_IR))
{
{
const char *rname;
- assert (value >=0 && value < 64);
+ assert (value >= 0 && value < 64);
rname = arcExtMap_coreRegName (value);
if (!rname)
- rname = regnames[value];
+ {
+ if (operand->flags & ARC_OPERAND_FP)
+ rname = fpnames[value & 0x1f];
+ else
+ rname = getregname (value, isa_mask);
+ }
(*info->fprintf_styled_func) (info->stream, dis_style_register,
"%s", rname);
if ((value & 0x01) == 0)
{
rname = arcExtMap_coreRegName (value + 1);
- if (!rname)
- rname = regnames[value + 1];
+ if (operand->flags & ARC_OPERAND_FP)
+ rname = fpnames[(value + 1) & 0x1f];
+ else
+ rname = getregname (value + 1, isa_mask);
}
else
rname = _("\nWarning: illegal use of double register "
(*info->fprintf_styled_func) (info->stream, dis_style_register,
"%s", rname);
}
- if (value == 63)
+ if (value == REG_PCL)
rpcl = true;
else
rpcl = false;
"%s", rname);
else
{
- (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
- "%#x", value);
+ if (operand->flags & ARC_OPERAND_SIGNED)
+ (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
+ "%d@s32", value);
+ else
+ (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
+ "%#x", value);
if (info->insn_type == dis_branch
|| info->insn_type == dis_jsr)
info->target = (bfd_vma) value;
= ARC_OPERAND_KIND_LIMM;
/* It is not important to have exactly the LIMM indicator
here. */
- arc_infop->operands[arc_infop->operands_count].value = 63;
+ arc_infop->operands[arc_infop->operands_count].value = REG_PCL;
}
else
{
+++ /dev/null
-/* ARC instruction defintions.
- Copyright (C) 2016-2023 Free Software Foundation, Inc.
-
- Contributed by Claudiu Zissulescu (claziss@synopsys.com)
-
- This file is part of libopcodes.
-
- This library is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software Foundation,
- Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-
-/* Common combinations of FLAGS. */
-#define FLAGS_NONE { 0 }
-#define FLAGS_F { C_F }
-#define FLAGS_CC { C_CC }
-#define FLAGS_CCF { C_CC, C_F }
-
-/* Common combination of arguments. */
-#define ARG_NONE { 0 }
-#define ARG_32BIT_RARBRC { RA, RB, RC }
-#define ARG_32BIT_ZARBRC { ZA, RB, RC }
-#define ARG_32BIT_RBRBRC { RB, RBdup, RC }
-#define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 }
-#define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 }
-#define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 }
-#define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 }
-#define ARG_32BIT_RALIMMRC { RA, LIMM, RC }
-#define ARG_32BIT_RARBLIMM { RA, RB, LIMM }
-#define ARG_32BIT_ZALIMMRC { ZA, LIMM, RC }
-#define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM }
-
-#define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM }
-#define ARG_32BIT_RALIMMU6 { RA, LIMM, UIMM6_20 }
-#define ARG_32BIT_ZALIMMU6 { ZA, LIMM, UIMM6_20 }
-
-#define ARG_32BIT_ZALIMMS12 { ZA, LIMM, SIMM12_20 }
-#define ARG_32BIT_RALIMMLIMM { RA, LIMM, LIMMdup }
-#define ARG_32BIT_ZALIMMLIMM { ZA, LIMM, LIMMdup }
-
-#define ARG_32BIT_RBRC { RB, RC }
-#define ARG_32BIT_ZARC { ZA, RC }
-#define ARG_32BIT_RBU6 { RB, UIMM6_20 }
-#define ARG_32BIT_ZAU6 { ZA, UIMM6_20 }
-#define ARG_32BIT_RBLIMM { RB, LIMM }
-#define ARG_32BIT_ZALIMM { ZA, LIMM }
-
-/* Macro to generate 2 operand extension instruction. */
-#define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL) \
- { NAME, INSN2OP_BC (MOP,SOP), MINSN2OP_BC, CPU, CLASS, SCLASS, \
- ARG_32BIT_RBRC, FL }, \
- { NAME, INSN2OP_0C (MOP,SOP), MINSN2OP_0C, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZARC, FL }, \
- { NAME, INSN2OP_BU (MOP,SOP), MINSN2OP_BU, CPU, CLASS, SCLASS, \
- ARG_32BIT_RBU6, FL }, \
- { NAME, INSN2OP_0U (MOP,SOP), MINSN2OP_0U, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZAU6, FL }, \
- { NAME, INSN2OP_BL (MOP,SOP), MINSN2OP_BL, CPU, CLASS, SCLASS, \
- ARG_32BIT_RBLIMM, FL }, \
- { NAME, INSN2OP_0L (MOP,SOP), MINSN2OP_0L, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZALIMM, FL },
-
-#define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \
- EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FLAGS_F)
-
-/* Macro to generate 3 operand extesion instruction. */
-#define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \
- { NAME, INSN3OP_ABC (MOP,SOP), MINSN3OP_ABC, CPU, CLASS, SCLASS, \
- ARG_32BIT_RARBRC, FLAGS_F }, \
- { NAME, INSN3OP_0BC (MOP,SOP), MINSN3OP_0BC, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZARBRC, FLAGS_F }, \
- { NAME, INSN3OP_CBBC (MOP,SOP), MINSN3OP_CBBC, CPU, CLASS, SCLASS, \
- ARG_32BIT_RBRBRC, FLAGS_CCF }, \
- { NAME, INSN3OP_ABU (MOP,SOP), MINSN3OP_ABU, CPU, CLASS, SCLASS, \
- ARG_32BIT_RARBU6, FLAGS_F }, \
- { NAME, INSN3OP_0BU (MOP,SOP), MINSN3OP_0BU, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZARBU6, FLAGS_F }, \
- { NAME, INSN3OP_CBBU (MOP,SOP), MINSN3OP_CBBU, CPU, CLASS, SCLASS, \
- ARG_32BIT_RBRBU6, FLAGS_CCF }, \
- { NAME, INSN3OP_BBS (MOP,SOP), MINSN3OP_BBS, CPU, CLASS, SCLASS, \
- ARG_32BIT_RBRBS12, FLAGS_F }, \
- { NAME, INSN3OP_ALC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \
- ARG_32BIT_RALIMMRC, FLAGS_F }, \
- { NAME, INSN3OP_ABL (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \
- ARG_32BIT_RARBLIMM, FLAGS_F }, \
- { NAME, INSN3OP_0LC (MOP,SOP), MINSN3OP_0LC, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZALIMMRC, FLAGS_F }, \
- { NAME, INSN3OP_0BL (MOP,SOP), MINSN3OP_0BL, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZARBLIMM, FLAGS_F }, \
- { NAME, INSN3OP_C0LC (MOP,SOP), MINSN3OP_C0LC, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZALIMMRC, FLAGS_CCF }, \
- { NAME, INSN3OP_CBBL (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \
- ARG_32BIT_RBRBLIMM, FLAGS_CCF }, \
- { NAME, INSN3OP_ALU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \
- ARG_32BIT_RALIMMU6, FLAGS_F }, \
- { NAME, INSN3OP_0LU (MOP,SOP), MINSN3OP_0LU, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZALIMMU6, FLAGS_F }, \
- { NAME, INSN3OP_C0LU (MOP,SOP), MINSN3OP_C0LU, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZALIMMU6, FLAGS_CCF }, \
- { NAME, INSN3OP_0LS (MOP,SOP), MINSN3OP_0LS, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZALIMMS12, FLAGS_F }, \
- { NAME, INSN3OP_ALL (MOP,SOP), MINSN3OP_ALL, CPU, CLASS, SCLASS, \
- ARG_32BIT_RALIMMLIMM, FLAGS_F }, \
- { NAME, INSN3OP_0LL (MOP,SOP), MINSN3OP_0LL, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZALIMMLIMM, FLAGS_F }, \
- { NAME, INSN3OP_C0LL (MOP,SOP), MINSN3OP_C0LL, CPU, CLASS, SCLASS, \
- ARG_32BIT_ZALIMMLIMM, FLAGS_CCF },
-
-/* Extension instruction declarations. */
-EXTINSN2OP ("dsp_fp_flt2i", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43)
-EXTINSN2OP ("dsp_fp_i2flt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 44)
-EXTINSN2OP ("dsp_fp_sqrt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 45)
-
-EXTINSN3OP ("dsp_fp_div", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 42)
-EXTINSN3OP ("dsp_fp_cmp", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43)
--- /dev/null
+/* ARC flag class defintions.
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+ Contributed by Claudiu Zissulescu (claziss@synopsys.com)
+ Refactored by Cupertino Miranda (cmiranda@synopsys.com)
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+FLAG_CLASS(EMPTY, F_CLASS_NONE, 0, 0, F_NULL)
+FLAG_CLASS(CC_EQ, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0 , F_EQUAL)
+FLAG_CLASS(CC_GE, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0 , F_GE)
+FLAG_CLASS(CC_GT, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_GT)
+FLAG_CLASS(CC_HI, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_HI)
+FLAG_CLASS(CC_HS, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_NOTCARRY)
+FLAG_CLASS(CC_LE, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_LE)
+FLAG_CLASS(CC_LO, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_CARRY)
+FLAG_CLASS(CC_LS, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_LS)
+FLAG_CLASS(CC_LT, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_LT)
+FLAG_CLASS(CC_NE, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_NOTEQUAL)
+
+FLAG_CLASS(AA_AB, F_CLASS_IMPLICIT | F_CLASS_WB, 0, 0, F_AB3)
+FLAG_CLASS(AA_AW, F_CLASS_IMPLICIT | F_CLASS_WB, 0, 0, F_AW3)
+
+FLAG_CLASS(ZZ_D, F_CLASS_IMPLICIT | F_CLASS_ZZ, 0, 0, F_SIZED)
+FLAG_CLASS(ZZ_L, F_CLASS_IMPLICIT | F_CLASS_ZZ, 0, 0, F_SIZEL)
+FLAG_CLASS(ZZ_W, F_CLASS_IMPLICIT | F_CLASS_ZZ, 0, 0, F_SIZEW)
+FLAG_CLASS(ZZ_H, F_CLASS_IMPLICIT | F_CLASS_ZZ, 0, 0, F_H1)
+FLAG_CLASS(ZZ_B, F_CLASS_IMPLICIT | F_CLASS_ZZ, 0, 0, F_SIZEB1)
+
+FLAG_CLASS(CC, F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND, 0, 0, F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T)
+
+FLAG_CLASS(AA_ADDR3, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A3, F_AW3, F_AB3, F_AS3)
+FLAG_CLASS(AA27, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A3, F_AW3, F_AB3, F_AS3)
+FLAG_CLASS(AS27, F_CLASS_OPTIONAL, 0, 0, F_AS3)
+FLAG_CLASS(AA_ADDR9, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A9, F_AW9, F_AB9, F_AS9)
+FLAG_CLASS(AA21, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A9, F_AW9, F_AB9, F_AS9)
+FLAG_CLASS(AAB21, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A9, F_AW9, F_AB9)
+FLAG_CLASS(AA_ADDR22, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A22, F_AW22, F_AB22, F_AS22)
+FLAG_CLASS(AA8, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A22, F_AW22, F_AB22, F_AS22)
+FLAG_CLASS(AAB8, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A22, F_AW22, F_AB22)
+
+FLAG_CLASS(F, F_CLASS_OPTIONAL, 0, 0, F_FLAG)
+FLAG_CLASS(FHARD, F_CLASS_OPTIONAL, 0, 0, F_FFAKE)
+
+FLAG_CLASS(RL, F_CLASS_OPTIONAL, 0, 0, F_RL)
+FLAG_CLASS(AQ, F_CLASS_OPTIONAL, 0, 0, F_AQ)
+
+FLAG_CLASS(ATOP, F_CLASS_REQUIRED, 0, 0, F_ATO_ADD, F_ATO_OR, F_ATO_AND, F_ATO_XOR, F_ATO_MINU, F_ATO_MAXU, F_ATO_MIN, F_ATO_MAX)
+
+FLAG_CLASS(T, F_CLASS_OPTIONAL, 0, 0, F_NT, F_T)
+FLAG_CLASS(D, F_CLASS_OPTIONAL, 0, 0, F_ND, F_D)
+FLAG_CLASS(DNZ_D, F_CLASS_OPTIONAL, 0, 0, F_DNZ_ND, F_DNZ_D)
+
+FLAG_CLASS(DHARD, F_CLASS_OPTIONAL, 0, 0, F_DFAKE)
+
+FLAG_CLASS(DI20, F_CLASS_OPTIONAL, 0, 0, F_DI11)
+FLAG_CLASS(DI14, F_CLASS_OPTIONAL, 0, 0, F_DI14)
+FLAG_CLASS(DI16, F_CLASS_OPTIONAL, 0, 0, F_DI15)
+FLAG_CLASS(DI26, F_CLASS_OPTIONAL, 0, 0, F_DI5)
+
+FLAG_CLASS(X25, F_CLASS_OPTIONAL, 0, 0, F_SIGN6)
+FLAG_CLASS(X15, F_CLASS_OPTIONAL, 0, 0, F_SIGN16)
+FLAG_CLASS(XHARD, F_CLASS_OPTIONAL, 0, 0, F_SIGNX)
+FLAG_CLASS(X, F_CLASS_OPTIONAL, 0, 0, F_SIGNX)
+
+FLAG_CLASS(ZZ13, F_CLASS_OPTIONAL, 0, 0, F_SIZEB17, F_SIZEW17, F_H17)
+FLAG_CLASS(ZZ23, F_CLASS_OPTIONAL, 0, 0, F_SIZEB7, F_SIZEW7, F_H7)
+FLAG_CLASS(ZZ29, F_CLASS_OPTIONAL, 0, 0, F_SIZEB1, F_SIZEW1, F_H1)
+FLAG_CLASS(ZZW6, F_CLASS_OPTIONAL, 0, 0, F_SIZEB1)
+FLAG_CLASS(ZZH1, F_CLASS_OPTIONAL, 0, 0, F_SIZEW1, F_H1)
+
+FLAG_CLASS(AS, F_CLASS_OPTIONAL, 0, 0, F_ASFAKE)
+FLAG_CLASS(AAHARD13, F_CLASS_OPTIONAL, 0, 0, F_ASFAKE)
+FLAG_CLASS(NE, F_CLASS_REQUIRED, 0, 0, F_NE)
+
+/* ARC NPS400 Support: See comment near head of file. */
+FLAG_CLASS(NPS_CL, F_CLASS_REQUIRED, 0, 0, F_NPS_CL)
+FLAG_CLASS(NPS_NA, F_CLASS_OPTIONAL, 0, 0, F_NPS_NA)
+FLAG_CLASS(NPS_SR, F_CLASS_OPTIONAL, 0, 0, F_NPS_SR)
+FLAG_CLASS(NPS_M, F_CLASS_OPTIONAL, 0, 0, F_NPS_M)
+FLAG_CLASS(NPS_F, F_CLASS_OPTIONAL, 0, 0, F_NPS_FLAG)
+FLAG_CLASS(NPS_R, F_CLASS_OPTIONAL, 0, 0, F_NPS_R)
+FLAG_CLASS(NPS_SCHD_RW, F_CLASS_REQUIRED, 0, 0, F_NPS_RW, F_NPS_RD)
+FLAG_CLASS(NPS_SCHD_TRIG, F_CLASS_REQUIRED, 0, 0, F_NPS_WFT)
+FLAG_CLASS(NPS_SCHD_IE, F_CLASS_OPTIONAL, 0, 0, F_NPS_IE1, F_NPS_IE2, F_NPS_IE12)
+FLAG_CLASS(NPS_SYNC, F_CLASS_REQUIRED, 0, 0, F_NPS_SYNC_RD, F_NPS_SYNC_WR)
+FLAG_CLASS(NPS_HWS_OFF, F_CLASS_REQUIRED, 0, 0, F_NPS_HWS_OFF)
+FLAG_CLASS(NPS_HWS_RESTORE, F_CLASS_REQUIRED, 0, 0, F_NPS_HWS_RESTORE)
+FLAG_CLASS(NPS_SX, F_CLASS_OPTIONAL, 0, 0, F_NPS_SX)
+FLAG_CLASS(NPS_AR_AL, F_CLASS_REQUIRED, 0, 0, F_NPS_AR, F_NPS_AL)
+FLAG_CLASS(NPS_S, F_CLASS_REQUIRED, 0, 0, F_NPS_S)
+FLAG_CLASS(NPS_ZNCV, F_CLASS_REQUIRED, 0, 0, F_NPS_ZNCV_RD, F_NPS_ZNCV_WR)
+FLAG_CLASS(NPS_P0, F_CLASS_REQUIRED, 0, 0, F_NPS_P0)
+FLAG_CLASS(NPS_P1, F_CLASS_REQUIRED, 0, 0, F_NPS_P1)
+FLAG_CLASS(NPS_P2, F_CLASS_REQUIRED, 0, 0, F_NPS_P2)
+FLAG_CLASS(NPS_P3, F_CLASS_REQUIRED, 0, 0, F_NPS_P3)
+FLAG_CLASS(NPS_LDBIT_DI, F_CLASS_REQUIRED, 0, 0, F_NPS_LDBIT_DI)
+FLAG_CLASS(NPS_LDBIT_CL1, F_CLASS_OPTIONAL, 0, 0, F_NPS_LDBIT_CL1)
+FLAG_CLASS(NPS_LDBIT_CL2, F_CLASS_OPTIONAL, 0, 0, F_NPS_LDBIT_CL2)
+FLAG_CLASS(NPS_LDBIT_X_1, F_CLASS_OPTIONAL, 0, 0, F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1)
+FLAG_CLASS(NPS_LDBIT_X_2, F_CLASS_OPTIONAL, 0, 0, F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2)
+FLAG_CLASS(NPS_CORE, F_CLASS_REQUIRED, 0, 0, F_NPS_CORE)
+FLAG_CLASS(NPS_CLSR, F_CLASS_REQUIRED, 0, 0, F_NPS_CLSR)
+FLAG_CLASS(NPS_ALL, F_CLASS_REQUIRED, 0, 0, F_NPS_ALL)
+FLAG_CLASS(NPS_GIC, F_CLASS_REQUIRED, 0, 0, F_NPS_GIC)
+FLAG_CLASS(NPS_RSPI_GIC, F_CLASS_REQUIRED, 0, 0, F_NPS_RSPI_GIC)
+FLAG_CLASS(FPCC, F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND, insert_fs2, extract_fs2, F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T)
+FLAG_CLASS(AA_128, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_AA128, F_AA128W, F_AA128B, F_AA128S)
+FLAG_CLASS(AS_128, F_CLASS_OPTIONAL, 0, 0, F_AA128S)
+FLAG_CLASS(AA_128S, F_CLASS_OPTIONAL | F_CLASS_WB, insert_qq, extract_qq, F_AA128, F_AA128W, F_AA128B, F_AA128S)
+FLAG_CLASS(AS_128S, F_CLASS_OPTIONAL, insert_qq, extract_qq, F_AA128S)
--- /dev/null
+/* ARC flag defintions.
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+ Contributed by Claudiu Zissulescu (claziss@synopsys.com)
+ Refactored by Cupertino Miranda (cmiranda@synopsys.com)
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+FLAG(ALWAYS, "al", 0, 0, 0, 0)
+FLAG(RA, "ra", 0, 0, 0, 0)
+FLAG(EQUAL, "eq", 1, 5, 0, 1)
+FLAG(ZERO, "z", 1, 5, 0, 0)
+FLAG(NOTEQUAL, "ne", 2, 5, 0, 1)
+FLAG(NOTZERO, "nz", 2, 5, 0, 0)
+FLAG(POZITIVE, "p", 3, 5, 0, 1)
+FLAG(PL, "pl", 3, 5, 0, 0)
+FLAG(NEGATIVE, "n", 4, 5, 0, 1)
+FLAG(MINUS, "mi", 4, 5, 0, 0)
+FLAG(CARRY, "c", 5, 5, 0, 1)
+FLAG(CARRYSET, "cs", 5, 5, 0, 0)
+FLAG(LOWER, "lo", 5, 5, 0, 0)
+FLAG(CARRYCLR, "cc", 6, 5, 0, 0)
+FLAG(NOTCARRY, "nc", 6, 5, 0, 1)
+FLAG(HIGHER, "hs", 6, 5, 0, 0)
+FLAG(OVERFLOWSET, "vs", 7, 5, 0, 0)
+FLAG(OVERFLOW, "v", 7, 5, 0, 1)
+FLAG(NOTOVERFLOW, "nv", 8, 5, 0, 1)
+FLAG(OVERFLOWCLR, "vc", 8, 5, 0, 0)
+FLAG(GT, "gt", 9, 5, 0, 1)
+FLAG(GE, "ge", 10, 5, 0, 1)
+FLAG(LT, "lt", 11, 5, 0, 1)
+FLAG(LE, "le", 12, 5, 0, 1)
+FLAG(HI, "hi", 13, 5, 0, 1)
+FLAG(LS, "ls", 14, 5, 0, 1)
+FLAG(PNZ, "pnz", 15, 5, 0, 1)
+FLAG(NJ, "nj", 21, 5, 0, 1)
+FLAG(NM, "nm", 23, 5, 0, 1)
+FLAG(NO_T, "nt", 24, 5, 0, 1)
+
+ /* FLAG. */
+FLAG(FLAG, "f", 1, 1, 15, 1)
+FLAG(FFAKE, "f", 0, 0, 0, 1)
+FLAG(AQ, "aq", 1, 1, 15, 1)
+FLAG(RL, "rl", 1, 1, 15, 1)
+
+ /* Atomic operations. */
+FLAG(ATO_ADD, "add", 0, 3, 0, 1)
+FLAG(ATO_OR, "or", 1, 3, 0, 1)
+FLAG(ATO_AND, "and", 2, 3, 0, 1)
+FLAG(ATO_XOR, "xor", 3, 3, 0, 1)
+FLAG(ATO_MINU, "minu", 4, 3, 0, 1)
+FLAG(ATO_MAXU, "maxu", 5, 3, 0, 1)
+FLAG(ATO_MIN, "min", 6, 3, 0, 1)
+FLAG(ATO_MAX, "max", 7, 3, 0, 1)
+
+ /* Delay slot. */
+FLAG(ND, "nd", 0, 1, 5, 0)
+FLAG(D, "d", 1, 1, 5, 1)
+FLAG(DFAKE, "d", 0, 0, 0, 1)
+FLAG(DNZ_ND, "nd", 0, 1, 16, 0)
+FLAG(DNZ_D, "d", 1, 1, 16, 1)
+
+ /* Data size. */
+FLAG(SIZEB1, "b", 1, 2, 1, 1)
+FLAG(SIZEB7, "b", 1, 2, 7, 1)
+FLAG(SIZEB17, "b", 1, 2, 17, 1)
+FLAG(SIZEW1, "w", 2, 2, 1, 0)
+FLAG(SIZEW7, "w", 2, 2, 7, 0)
+FLAG(SIZEW17, "w", 2, 2, 17, 0)
+
+ /* Sign extension. */
+FLAG(SIGN6, "x", 1, 1, 6, 1)
+FLAG(SIGN16, "x", 1, 1, 16, 1)
+FLAG(SIGNX, "x", 0, 0, 0, 1)
+
+ /* Address write-back modes. */
+FLAG(A3, "a", 1, 2, 3, 0)
+FLAG(A9, "a", 1, 2, 9, 0)
+FLAG(A22, "a", 1, 2, 22, 0)
+FLAG(AW3, "aw", 1, 2, 3, 1)
+FLAG(AW9, "aw", 1, 2, 9, 1)
+FLAG(AW22, "aw", 1, 2, 22, 1)
+FLAG(AB3, "ab", 2, 2, 3, 1)
+FLAG(AB9, "ab", 2, 2, 9, 1)
+FLAG(AB22, "ab", 2, 2, 22, 1)
+FLAG(AS3, "as", 3, 2, 3, 1)
+FLAG(AS9, "as", 3, 2, 9, 1)
+FLAG(AS22, "as", 3, 2, 22, 1)
+FLAG(ASFAKE, "as", 0, 0, 0, 1)
+
+/* address writebacks for 128-bit loads.
+ ,---.---.----------.
+ | X | D | mnemonic |
+ |---+---+----------|
+ | 0 | 0 | none |
+ | 0 | 1 | as |
+ | 1 | 0 | a/aw |
+ | 1 | 1 | ab |
+ `---^---^----------' */
+FLAG(AA128, "a", 2, 2, 15, 0)
+FLAG(AA128W, "aw", 2, 2, 15, 1)
+FLAG(AA128B, "ab", 3, 2, 15, 1)
+FLAG(AA128S, "as", 1, 2, 15, 1)
+
+ /* Cache bypass. */
+FLAG(DI5, "di", 1, 1, 5, 1)
+FLAG(DI11, "di", 1, 1, 11, 1)
+FLAG(DI14, "di", 1, 1, 14, 1)
+FLAG(DI15, "di", 1, 1, 15, 1)
+
+ /* ARCv2 specific. */
+FLAG(NT, "nt", 0, 1, 3, 1)
+FLAG(T, "t", 1, 1, 3, 1)
+FLAG(H1, "h", 2, 2, 1, 1)
+FLAG(H7, "h", 2, 2, 7, 1)
+FLAG(H17, "h", 2, 2, 17, 1)
+/* Fake */
+FLAG(SIZED, "dd", 8, 0, 0, 0)
+/* Fake */
+FLAG(SIZEL, "dl", 8, 0, 0, 0)
+/* Fake */
+FLAG(SIZEW, "xx", 4, 0, 0, 0)
+
+ /* Fake Flags. */
+FLAG(NE, "ne", 0, 0, 0, 1)
+
+/* ARC NPS400 Support: See comment near head of arcxx-opc.inc file. */
+FLAG(NPS_CL, "cl", 0, 0, 0, 1)
+FLAG(NPS_NA, "na", 1, 1, 9, 1)
+FLAG(NPS_SR, "s", 1, 1, 13, 1)
+FLAG(NPS_M, "m", 1, 1, 7, 1)
+FLAG(NPS_FLAG, "f", 1, 1, 20, 1)
+FLAG(NPS_R, "r", 1, 1, 15, 1)
+FLAG(NPS_RW, "rw", 0, 1, 7, 1)
+FLAG(NPS_RD, "rd", 1, 1, 7, 1)
+FLAG(NPS_WFT, "wft", 0, 0, 0, 1)
+FLAG(NPS_IE1, "ie1", 1, 2, 8, 1)
+FLAG(NPS_IE2, "ie2", 2, 2, 8, 1)
+FLAG(NPS_IE12, "ie12", 3, 2, 8, 1)
+FLAG(NPS_SYNC_RD, "rd", 0, 1, 6, 1)
+FLAG(NPS_SYNC_WR, "wr", 1, 1, 6, 1)
+FLAG(NPS_HWS_OFF, "off", 0, 0, 0, 1)
+FLAG(NPS_HWS_RESTORE, "restore", 0, 0, 0, 1)
+FLAG(NPS_SX, "sx", 1, 1, 14, 1)
+FLAG(NPS_AR, "ar", 0, 1, 0, 1)
+FLAG(NPS_AL, "al", 1, 1, 0, 1)
+FLAG(NPS_S, "s", 0, 0, 0, 1)
+FLAG(NPS_ZNCV_RD, "rd", 0, 1, 15, 1)
+FLAG(NPS_ZNCV_WR, "wr", 1, 1, 15, 1)
+FLAG(NPS_P0, "p0", 0, 0, 0, 1)
+FLAG(NPS_P1, "p1", 0, 0, 0, 1)
+FLAG(NPS_P2, "p2", 0, 0, 0, 1)
+FLAG(NPS_P3, "p3", 0, 0, 0, 1)
+FLAG(NPS_LDBIT_DI, "di", 0, 0, 0, 1)
+FLAG(NPS_LDBIT_CL1, "cl", 1, 1, 6, 1)
+FLAG(NPS_LDBIT_CL2, "cl", 1, 1, 16, 1)
+FLAG(NPS_LDBIT_X2_1, "x2", 1, 2, 9, 1)
+FLAG(NPS_LDBIT_X2_2, "x2", 1, 2, 22, 1)
+FLAG(NPS_LDBIT_X4_1, "x4", 2, 2, 9, 1)
+FLAG(NPS_LDBIT_X4_2, "x4", 2, 2, 22, 1)
+FLAG(NPS_CORE, "core", 1, 3, 6, 1)
+FLAG(NPS_CLSR, "clsr", 2, 3, 6, 1)
+FLAG(NPS_ALL, "all", 3, 3, 6, 1)
+FLAG(NPS_GIC, "gic", 4, 3, 6, 1)
+FLAG(NPS_RSPI_GIC, "gic", 5, 3, 6, 1)
return value;
}
#endif /* EXTRACT_UIMM6_AXX_ */
+
+/* mask = 0000022000011111. */
+#ifndef INSERT_UIMM9_A32_11_S
+#define INSERT_UIMM9_A32_11_S
+ATTRIBUTE_UNUSED static unsigned long long
+insert_uimm9_a32_11_s (unsigned long long insn ATTRIBUTE_UNUSED,
+ long long int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value & 0x03)
+ *errmsg = "Target address is not 32bit aligned.";
+
+ insn |= ((value >> 2) & 0x001f) << 0;
+ insn |= ((value >> 7) & 0x0003) << 9;
+ return insn;
+}
+#endif /* INSERT_UIMM9_A32_11_S. */
+
+#ifndef EXTRACT_UIMM9_A32_11_S
+#define EXTRACT_UIMM9_A32_11_S
+ATTRIBUTE_UNUSED static long long int
+extract_uimm9_a32_11_s (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ unsigned value = 0;
+ value |= ((insn >> 0) & 0x001f) << 2;
+ value |= ((insn >> 9) & 0x0003) << 7;
+
+ return value;
+}
+#endif /* EXTRACT_UIMM9_A32_11_S. */
+
+/* mask = 0000022222220111. */
+#ifndef INSERT_UIMM10_13_S
+#define INSERT_UIMM10_13_S
+ATTRIBUTE_UNUSED static unsigned long long
+insert_uimm10_13_s (unsigned long long insn ATTRIBUTE_UNUSED,
+ long long int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ insn |= ((value >> 0) & 0x0007) << 0;
+ insn |= ((value >> 3) & 0x007f) << 4;
+
+ return insn;
+}
+#endif /* INSERT_UIMM10_13_S. */
+
+#ifndef EXTRACT_UIMM10_13_S
+#define EXTRACT_UIMM10_13_S
+ATTRIBUTE_UNUSED static long long int
+extract_uimm10_13_s (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ unsigned value = 0;
+ value |= ((insn >> 0) & 0x0007) << 0;
+ value |= ((insn >> 4) & 0x007f) << 3;
+
+ return value;
+}
+#endif /* EXTRACT_UIMM10_13_S. */
along with this program; if not, write to the Free Software Foundation,
Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-#include "sysdep.h"
-#include <stdio.h>
-#include "bfd.h"
-#include "opcode/arc.h"
-#include "opintl.h"
-#include "libiberty.h"
-
-/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
- instructions. All NPS400 features are built into all ARC target builds as
- this reduces the chances that regressions might creep in. */
-
-/* Insert RA register into a 32-bit opcode, with checks. */
-
-static unsigned long long
-insert_ra_chk (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value == 60)
- *errmsg = _("LP_COUNT register cannot be used as destination register");
-
- return insn | (value & 0x3F);
-}
-
-/* Insert RB register into a 32-bit opcode. */
-
-static unsigned long long
-insert_rb (unsigned long long insn,
- long long value,
- const char ** errmsg ATTRIBUTE_UNUSED)
-{
- return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
-}
-
-/* Insert RB register with checks. */
-
-static unsigned long long
-insert_rb_chk (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value == 60)
- *errmsg = _("LP_COUNT register cannot be used as destination register");
-
- return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
-}
-
-static long long
-extract_rb (unsigned long long insn,
- bool *invalid)
-{
- int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
-
- if (value == 0x3e && invalid)
- *invalid = true; /* A limm operand, it should be extracted in a
- different way. */
-
- return value;
-}
-
-static unsigned long long
-insert_rad (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value & 0x01)
- *errmsg = _("cannot use odd number destination register");
- if (value == 60)
- *errmsg = _("LP_COUNT register cannot be used as destination register");
-
- return insn | (value & 0x3F);
-}
-
-static unsigned long long
-insert_rcd (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value & 0x01)
- *errmsg = _("cannot use odd number source register");
-
- return insn | ((value & 0x3F) << 6);
-}
-
-static unsigned long long
-insert_rbd (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value & 0x01)
- *errmsg = _("cannot use odd number source register");
- if (value == 60)
- *errmsg = _("LP_COUNT register cannot be used as destination register");
-
- return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
-}
-
-/* Dummy insert ZERO operand function. */
-
-static unsigned long long
-insert_za (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value)
- *errmsg = _("operand is not zero");
- return insn;
-}
-
-/* Insert Y-bit in bbit/br instructions. This function is called only
- when solving fixups. */
-
-static unsigned long long
-insert_Ybit (unsigned long long insn,
- long long value,
- const char ** errmsg ATTRIBUTE_UNUSED)
-{
- if (value > 0)
- insn |= 0x08;
-
- return insn;
-}
-
-/* Insert Y-bit in bbit/br instructions. This function is called only
- when solving fixups. */
-
-static unsigned long long
-insert_NYbit (unsigned long long insn,
- long long value,
- const char ** errmsg ATTRIBUTE_UNUSED)
-{
- if (value < 0)
- insn |= 0x08;
-
- return insn;
-}
-
-/* Insert H register into a 16-bit opcode. */
-
-static unsigned long long
-insert_rhv1 (unsigned long long insn,
- long long value,
- const char ** errmsg ATTRIBUTE_UNUSED)
-{
- return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
-}
-
-static long long
-extract_rhv1 (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7);
-
- return value;
-}
-
-/* Insert H register into a 16-bit opcode. */
-
-static unsigned long long
-insert_rhv2 (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value == 0x1E)
- *errmsg = _("register R30 is a limm indicator");
- else if (value < 0 || value > 31)
- *errmsg = _("register out of range");
- return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
-}
-
-static long long
-extract_rhv2 (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
-
- return value;
-}
-
-static unsigned long long
-insert_r0 (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 0)
- *errmsg = _("register must be R0");
- return insn;
-}
-
-static long long
-extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-
-static unsigned long long
-insert_r1 (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 1)
- *errmsg = _("register must be R1");
- return insn;
-}
-
-static long long
-extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED,
- bool* invalid ATTRIBUTE_UNUSED)
-{
- return 1;
-}
-
-static unsigned long long
-insert_r2 (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 2)
- *errmsg = _("register must be R2");
- return insn;
-}
-
-static long long
-extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return 2;
-}
-
-static unsigned long long
-insert_r3 (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 3)
- *errmsg = _("register must be R3");
- return insn;
-}
-
-static long long
-extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return 3;
-}
-
-static unsigned long long
-insert_sp (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 28)
- *errmsg = _("register must be SP");
- return insn;
-}
-
-static long long
-extract_sp (unsigned long long insn ATTRIBUTE_UNUSED,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return 28;
-}
-
-static unsigned long long
-insert_gp (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 26)
- *errmsg = _("register must be GP");
- return insn;
-}
-
-static long long
-extract_gp (unsigned long long insn ATTRIBUTE_UNUSED,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return 26;
-}
-
-static unsigned long long
-insert_pcl (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 63)
- *errmsg = _("register must be PCL");
- return insn;
-}
-
-static long long
-extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return 63;
-}
-
-static unsigned long long
-insert_blink (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 31)
- *errmsg = _("register must be BLINK");
- return insn;
-}
-
-static long long
-extract_blink (unsigned long long insn ATTRIBUTE_UNUSED,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return 31;
-}
-
-static unsigned long long
-insert_ilink1 (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 29)
- *errmsg = _("register must be ILINK1");
- return insn;
-}
-
-static long long
-extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return 29;
-}
-
-static unsigned long long
-insert_ilink2 (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 30)
- *errmsg = _("register must be ILINK2");
- return insn;
-}
-
-static long long
-extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return 30;
-}
-
-static unsigned long long
-insert_ras (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- switch (value)
- {
- case 0:
- case 1:
- case 2:
- case 3:
- insn |= value;
- break;
- case 12:
- case 13:
- case 14:
- case 15:
- insn |= (value - 8);
- break;
- default:
- *errmsg = _("register must be either r0-r3 or r12-r15");
- break;
- }
- return insn;
-}
-
-static long long
-extract_ras (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int value = insn & 0x07;
-
- if (value > 3)
- return (value + 8);
- else
- return value;
-}
-
-static unsigned long long
-insert_rbs (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- switch (value)
- {
- case 0:
- case 1:
- case 2:
- case 3:
- insn |= value << 8;
- break;
- case 12:
- case 13:
- case 14:
- case 15:
- insn |= ((value - 8)) << 8;
- break;
- default:
- *errmsg = _("register must be either r0-r3 or r12-r15");
- break;
- }
- return insn;
-}
-
-static long long
-extract_rbs (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int value = (insn >> 8) & 0x07;
-
- if (value > 3)
- return (value + 8);
- else
- return value;
-}
-
-static unsigned long long
-insert_rcs (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- switch (value)
- {
- case 0:
- case 1:
- case 2:
- case 3:
- insn |= value << 5;
- break;
- case 12:
- case 13:
- case 14:
- case 15:
- insn |= ((value - 8)) << 5;
- break;
- default:
- *errmsg = _("register must be either r0-r3 or r12-r15");
- break;
- }
- return insn;
-}
-
-static long long
-extract_rcs (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int value = (insn >> 5) & 0x07;
-
- if (value > 3)
- return (value + 8);
- else
- return value;
-}
-
-static unsigned long long
-insert_simm3s (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- int tmp = 0;
- switch (value)
- {
- case -1:
- tmp = 0x07;
- break;
- case 0:
- tmp = 0x00;
- break;
- case 1:
- tmp = 0x01;
- break;
- case 2:
- tmp = 0x02;
- break;
- case 3:
- tmp = 0x03;
- break;
- case 4:
- tmp = 0x04;
- break;
- case 5:
- tmp = 0x05;
- break;
- case 6:
- tmp = 0x06;
- break;
- default:
- *errmsg = _("accepted values are from -1 to 6");
- break;
- }
-
- insn |= tmp << 8;
- return insn;
-}
-
-static long long
-extract_simm3s (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int value = (insn >> 8) & 0x07;
-
- if (value == 7)
- return -1;
- else
- return value;
-}
-
-static unsigned long long
-insert_rrange (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- int reg1 = (value >> 16) & 0xFFFF;
- int reg2 = value & 0xFFFF;
-
- if (reg1 != 13)
- *errmsg = _("first register of the range should be r13");
- else if (reg2 < 13 || reg2 > 26)
- *errmsg = _("last register of the range doesn't fit");
- else
- insn |= ((reg2 - 12) & 0x0F) << 1;
- return insn;
-}
-
-static long long
-extract_rrange (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return (insn >> 1) & 0x0F;
-}
-
-static unsigned long long
-insert_r13el (unsigned long long insn,
- long long int value,
- const char **errmsg)
-{
- if (value != 13)
- {
- *errmsg = _("invalid register number, should be fp");
- return insn;
- }
-
- insn |= 0x02;
- return insn;
-}
-
-static unsigned long long
-insert_fpel (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 27)
- {
- *errmsg = _("invalid register number, should be fp");
- return insn;
- }
-
- insn |= 0x0100;
- return insn;
-}
-
-static long long
-extract_fpel (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return (insn & 0x0100) ? 27 : -1;
-}
-
-static unsigned long long
-insert_blinkel (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 31)
- {
- *errmsg = _("invalid register number, should be blink");
- return insn;
- }
-
- insn |= 0x0200;
- return insn;
-}
-
-static long long
-extract_blinkel (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return (insn & 0x0200) ? 31 : -1;
-}
-
-static unsigned long long
-insert_pclel (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value != 63)
- {
- *errmsg = _("invalid register number, should be pcl");
- return insn;
- }
-
- insn |= 0x0400;
- return insn;
-}
-
-static long long
-extract_pclel (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return (insn & 0x0400) ? 63 : -1;
-}
-
-#define INSERT_W6
-
-/* mask = 00000000000000000000111111000000
- insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
-
-static unsigned long long
-insert_w6 (unsigned long long insn,
- long long value,
- const char ** errmsg ATTRIBUTE_UNUSED)
-{
- insn |= ((value >> 0) & 0x003f) << 6;
-
- return insn;
-}
-
-#define EXTRACT_W6
-
-/* mask = 00000000000000000000111111000000. */
-
-static long long
-extract_w6 (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int value = 0;
-
- value |= ((insn >> 6) & 0x003f) << 0;
-
- /* Extend the sign. */
- int signbit = 1 << 5;
- value = (value ^ signbit) - signbit;
-
- return value;
-}
-
-#define INSERT_G_S
-
-/* mask = 0000011100022000
- insn = 01000ggghhhGG0HH. */
-
-static unsigned long long
-insert_g_s (unsigned long long insn,
- long long value,
- const char ** errmsg ATTRIBUTE_UNUSED)
-{
- insn |= ((value >> 0) & 0x0007) << 8;
- insn |= ((value >> 3) & 0x0003) << 3;
-
- return insn;
-}
-
-#define EXTRACT_G_S
-
-/* mask = 0000011100022000. */
-
-static long long
-extract_g_s (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int value = 0;
- int signbit = 1 << (6 - 1);
-
- value |= ((insn >> 8) & 0x0007) << 0;
- value |= ((insn >> 3) & 0x0003) << 3;
-
- /* Extend the sign. */
- value = (value ^ signbit) - signbit;
-
- return value;
-}
-
-/* ARC NPS400 Support: See comment near head of file. */
-#define MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(NAME,OFFSET) \
-static unsigned long long \
-insert_nps_3bit_reg_at_##OFFSET##_##NAME \
- (unsigned long long insn, \
- long long value, \
- const char ** errmsg) \
-{ \
- switch (value) \
- { \
- case 0: \
- case 1: \
- case 2: \
- case 3: \
- insn |= value << (OFFSET); \
- break; \
- case 12: \
- case 13: \
- case 14: \
- case 15: \
- insn |= (value - 8) << (OFFSET); \
- break; \
- default: \
- *errmsg = _("register must be either r0-r3 or r12-r15"); \
- break; \
- } \
- return insn; \
-} \
- \
-static long long \
-extract_nps_3bit_reg_at_##OFFSET##_##NAME \
- (unsigned long long insn, \
- bool *invalid ATTRIBUTE_UNUSED) \
-{ \
- int value = (insn >> (OFFSET)) & 0x07; \
- if (value > 3) \
- value += 8; \
- return value; \
-} \
-
-MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,8)
-MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,24)
-MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,40)
-MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,56)
-
-MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,5)
-MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,21)
-MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,37)
-MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,53)
-
-static unsigned long long
-insert_nps_bitop_size_2b (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- switch (value)
- {
- case 1:
- value = 0;
- break;
- case 2:
- value = 1;
- break;
- case 4:
- value = 2;
- break;
- case 8:
- value = 3;
- break;
- default:
- value = 0;
- *errmsg = _("invalid size, should be 1, 2, 4, or 8");
- break;
- }
-
- insn |= value << 10;
- return insn;
-}
-
-static long long
-extract_nps_bitop_size_2b (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return 1 << ((insn >> 10) & 0x3);
-}
-
-static unsigned long long
-insert_nps_bitop_uimm8 (unsigned long long insn,
- long long value,
- const char ** errmsg ATTRIBUTE_UNUSED)
-{
- insn |= ((value >> 5) & 7) << 12;
- insn |= (value & 0x1f);
- return insn;
-}
-
-static long long
-extract_nps_bitop_uimm8 (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
-}
-
-static unsigned long long
-insert_nps_rflt_uimm6 (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- switch (value)
- {
- case 1:
- case 2:
- case 4:
- break;
-
- default:
- *errmsg = _("invalid immediate, must be 1, 2, or 4");
- value = 0;
- }
-
- insn |= (value << 6);
- return insn;
-}
-
-static long long
-extract_nps_rflt_uimm6 (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return (insn >> 6) & 0x3f;
-}
-
-static unsigned long long
-insert_nps_dst_pos_and_size (unsigned long long insn,
- long long value,
- const char ** errmsg ATTRIBUTE_UNUSED)
-{
- insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
- return insn;
-}
-
-static long long
-extract_nps_dst_pos_and_size (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return (insn & 0x1f);
-}
-
-static unsigned long long
-insert_nps_cmem_uimm16 (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- int top = (value >> 16) & 0xffff;
-
- if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE)
- *errmsg = _("invalid value for CMEM ld/st immediate");
- insn |= (value & 0xffff);
- return insn;
-}
-
-static long long
-extract_nps_cmem_uimm16 (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
-}
-
-static unsigned long long
-insert_nps_imm_offset (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- switch (value)
- {
- case 0:
- case 16:
- case 32:
- case 48:
- case 64:
- value = value >> 4;
- break;
- default:
- *errmsg = _("invalid position, should be 0, 16, 32, 48 or 64.");
- value = 0;
- }
- insn |= (value << 10);
- return insn;
-}
-
-static long long
-extract_nps_imm_offset (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return ((insn >> 10) & 0x7) * 16;
-}
-
-static unsigned long long
-insert_nps_imm_entry (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- switch (value)
- {
- case 16:
- value = 0;
- break;
- case 32:
- value = 1;
- break;
- case 64:
- value = 2;
- break;
- case 128:
- value = 3;
- break;
- default:
- *errmsg = _("invalid position, should be 16, 32, 64 or 128.");
- value = 0;
- }
- insn |= (value << 2);
- return insn;
-}
-
-static long long
-extract_nps_imm_entry (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int imm_entry = ((insn >> 2) & 0x7);
- return (1 << (imm_entry + 4));
-}
-
-static unsigned long long
-insert_nps_size_16bit (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if ((value < 1) || (value > 64))
- {
- *errmsg = _("invalid size value must be on range 1-64.");
- value = 0;
- }
- value = value & 0x3f;
- insn |= (value << 6);
- return insn;
-}
-
-static long long
-extract_nps_size_16bit (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return ((insn & 0xfc0) >> 6) ? ((insn & 0xfc0) >> 6) : 64;
-}
-
-
-#define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
-static unsigned long long \
-insert_nps_##NAME##_pos (unsigned long long insn, \
- long long value, \
- const char ** errmsg) \
-{ \
- switch (value) \
- { \
- case 0: \
- case 8: \
- case 16: \
- case 24: \
- value = value / 8; \
- break; \
- default: \
- *errmsg = _("invalid position, should be 0, 8, 16, or 24"); \
- value = 0; \
- } \
- insn |= (value << SHIFT); \
- return insn; \
-} \
- \
-static long long \
-extract_nps_##NAME##_pos (unsigned long long insn, \
- bool *invalid ATTRIBUTE_UNUSED) \
-{ \
- return ((insn >> SHIFT) & 0x3) * 8; \
-}
-
-MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12)
-MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10)
-
-#define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT) \
-static unsigned long long \
-insert_nps_##NAME (unsigned long long insn, \
- long long value, \
- const char ** errmsg) \
- { \
- if (value < LOWER || value > UPPER) \
- { \
- *errmsg = _("invalid size, value must be " \
- #LOWER " to " #UPPER "."); \
- return insn; \
- } \
- value -= BIAS; \
- insn |= (value << SHIFT); \
- return insn; \
- } \
- \
-static long long \
-extract_nps_##NAME (unsigned long long insn, \
- bool *invalid ATTRIBUTE_UNUSED) \
-{ \
- return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
-}
-
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5)
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5)
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5)
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5)
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10)
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9)
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20)
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25)
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6)
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2)
-MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0)
-
-static long long
-extract_nps_qcmp_m3 (unsigned long long insn,
- bool *invalid)
-{
- int m3 = (insn >> 5) & 0xf;
- if (m3 == 0xf)
- *invalid = true;
- return m3;
-}
-
-static long long
-extract_nps_qcmp_m2 (unsigned long long insn,
- bool *invalid)
-{
- bool tmp_invalid = false;
- int m2 = (insn >> 15) & 0x1;
- int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
-
- if (m2 == 0 && m3 == 0xf)
- *invalid = true;
- return m2;
-}
-
-static long long
-extract_nps_qcmp_m1 (unsigned long long insn,
- bool *invalid)
-{
- bool tmp_invalid = false;
- int m1 = (insn >> 14) & 0x1;
- int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid);
- int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
-
- if (m1 == 0 && m2 == 0 && m3 == 0xf)
- *invalid = true;
- return m1;
-}
-
-static unsigned long long
-insert_nps_calc_entry_size (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- unsigned pwr;
-
- if (value < 1 || value > 256)
- {
- *errmsg = _("value out of range 1 - 256");
- return 0;
- }
-
- for (pwr = 0; (value & 1) == 0; value >>= 1)
- ++pwr;
-
- if (value != 1)
- {
- *errmsg = _("value must be power of 2");
- return 0;
- }
-
- return insn | (pwr << 8);
-}
-
-static long long
-extract_nps_calc_entry_size (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- unsigned entry_size = (insn >> 8) & 0xf;
- return 1 << entry_size;
-}
-
-static unsigned long long
-insert_nps_bitop_mod4 (unsigned long long insn,
- long long value,
- const char ** errmsg ATTRIBUTE_UNUSED)
-{
- return insn | ((value & 0x2) << 30) | ((value & 0x1) << 47);
-}
-
-static long long
-extract_nps_bitop_mod4 (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return ((insn >> 30) & 0x2) | ((insn >> 47) & 0x1);
-}
-
-static unsigned long long
-insert_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
- long long value,
- const char ** errmsg ATTRIBUTE_UNUSED)
-{
- return insn | (value << 42) | (value << 37);
-}
-
-static long long
-extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
- bool *invalid)
-{
- if (((insn >> 42) & 0x1f) != ((insn >> 37) & 0x1f))
- *invalid = true;
- return ((insn >> 37) & 0x1f);
-}
-
-static unsigned long long
-insert_nps_bitop_ins_ext (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value < 0 || value > 28)
- *errmsg = _("value must be in the range 0 to 28");
- return insn | (value << 20);
-}
-
-static long long
-extract_nps_bitop_ins_ext (unsigned long long insn,
- bool *invalid)
-{
- int value = (insn >> 20) & 0x1f;
-
- if (value > 28)
- *invalid = true;
- return value;
-}
-
-#define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \
-static unsigned long long \
-insert_nps_##NAME (unsigned long long insn, \
- long long value, \
- const char ** errmsg) \
-{ \
- if (value < 1 || value > UPPER) \
- *errmsg = _("value must be in the range 1 to " #UPPER); \
- if (value == UPPER) \
- value = 0; \
- return insn | (value << SHIFT); \
-} \
- \
-static long long \
-extract_nps_##NAME (unsigned long long insn, \
- bool *invalid ATTRIBUTE_UNUSED) \
-{ \
- int value = (insn >> SHIFT) & ((1 << BITS) - 1); \
- if (value == 0) \
- value = UPPER; \
- return value; \
-}
-
-MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3)
-MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3)
-MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3)
-MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8)
-MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3)
-MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2)
-MAKE_1BASED_INSERT_EXTRACT_FUNCS (proto_size, 16, 64, 6)
-
-static unsigned long long
-insert_nps_min_hofs (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value < 0 || value > 240)
- *errmsg = _("value must be in the range 0 to 240");
- if ((value % 16) != 0)
- *errmsg = _("value must be a multiple of 16");
- value = value / 16;
- return insn | (value << 6);
-}
-
-static long long
-extract_nps_min_hofs (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int value = (insn >> 6) & 0xF;
- return value * 16;
-}
-
-#define MAKE_INSERT_NPS_ADDRTYPE(NAME, VALUE) \
-static unsigned long long \
-insert_nps_##NAME (unsigned long long insn, \
- long long value, \
- const char ** errmsg) \
-{ \
- if (value != ARC_NPS400_ADDRTYPE_##VALUE) \
- *errmsg = _("invalid address type for operand"); \
- return insn; \
-} \
- \
-static long long \
-extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
- bool *invalid ATTRIBUTE_UNUSED) \
-{ \
- return ARC_NPS400_ADDRTYPE_##VALUE; \
-}
-
-MAKE_INSERT_NPS_ADDRTYPE (bd, BD)
-MAKE_INSERT_NPS_ADDRTYPE (jid, JID)
-MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD)
-MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD)
-MAKE_INSERT_NPS_ADDRTYPE (sd, SD)
-MAKE_INSERT_NPS_ADDRTYPE (sm, SM)
-MAKE_INSERT_NPS_ADDRTYPE (xa, XA)
-MAKE_INSERT_NPS_ADDRTYPE (xd, XD)
-MAKE_INSERT_NPS_ADDRTYPE (cd, CD)
-MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD)
-MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID)
-MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD)
-MAKE_INSERT_NPS_ADDRTYPE (cm, CM)
-MAKE_INSERT_NPS_ADDRTYPE (csd, CSD)
-MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA)
-MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD)
-
-static unsigned long long
-insert_nps_rbdouble_64 (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value < 0 || value > 31)
- *errmsg = _("value must be in the range 0 to 31");
- return insn | (value << 43) | (value << 48);
-}
-
-
-static long long
-extract_nps_rbdouble_64 (unsigned long long insn,
- bool *invalid)
-{
- int value1 = (insn >> 43) & 0x1F;
- int value2 = (insn >> 48) & 0x1F;
-
- if (value1 != value2)
- *invalid = true;
-
- return value1;
-}
-
-static unsigned long long
-insert_nps_misc_imm_offset (unsigned long long insn,
- long long value,
- const char ** errmsg)
-{
- if (value & 0x3)
- {
- *errmsg = _("invalid position, should be one of: 0,4,8,...124.");
- value = 0;
- }
- insn |= (value << 6);
- return insn;
-}
-
-static long long int
-extract_nps_misc_imm_offset (unsigned long long insn,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- return ((insn >> 8) & 0x1f) * 4;
-}
-
-static long long int
-extract_uimm12_20 (unsigned long long insn ATTRIBUTE_UNUSED,
- bool *invalid ATTRIBUTE_UNUSED)
-{
- int value = 0;
-
- value |= ((insn >> 6) & 0x003f) << 0;
- value |= ((insn >> 0) & 0x003f) << 6;
-
- return value;
-}
-
-/* Include the generic extract/insert functions. Order is important
- as some of the functions present in the .h may be disabled via
- defines. */
-#include "arc-fxi.h"
-
-/* The flag operands table.
-
- The format of the table is
- NAME CODE BITS SHIFT FAVAIL. */
-const struct arc_flag_operand arc_flag_operands[] =
-{
-#define F_NULL 0
- { 0, 0, 0, 0, 0},
-#define F_ALWAYS (F_NULL + 1)
- { "al", 0, 0, 0, 0 },
-#define F_RA (F_ALWAYS + 1)
- { "ra", 0, 0, 0, 0 },
-#define F_EQUAL (F_RA + 1)
- { "eq", 1, 5, 0, 1 },
-#define F_ZERO (F_EQUAL + 1)
- { "z", 1, 5, 0, 0 },
-#define F_NOTEQUAL (F_ZERO + 1)
- { "ne", 2, 5, 0, 1 },
-#define F_NOTZERO (F_NOTEQUAL + 1)
- { "nz", 2, 5, 0, 0 },
-#define F_POZITIVE (F_NOTZERO + 1)
- { "p", 3, 5, 0, 1 },
-#define F_PL (F_POZITIVE + 1)
- { "pl", 3, 5, 0, 0 },
-#define F_NEGATIVE (F_PL + 1)
- { "n", 4, 5, 0, 1 },
-#define F_MINUS (F_NEGATIVE + 1)
- { "mi", 4, 5, 0, 0 },
-#define F_CARRY (F_MINUS + 1)
- { "c", 5, 5, 0, 1 },
-#define F_CARRYSET (F_CARRY + 1)
- { "cs", 5, 5, 0, 0 },
-#define F_LOWER (F_CARRYSET + 1)
- { "lo", 5, 5, 0, 0 },
-#define F_CARRYCLR (F_LOWER + 1)
- { "cc", 6, 5, 0, 0 },
-#define F_NOTCARRY (F_CARRYCLR + 1)
- { "nc", 6, 5, 0, 1 },
-#define F_HIGHER (F_NOTCARRY + 1)
- { "hs", 6, 5, 0, 0 },
-#define F_OVERFLOWSET (F_HIGHER + 1)
- { "vs", 7, 5, 0, 0 },
-#define F_OVERFLOW (F_OVERFLOWSET + 1)
- { "v", 7, 5, 0, 1 },
-#define F_NOTOVERFLOW (F_OVERFLOW + 1)
- { "nv", 8, 5, 0, 1 },
-#define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
- { "vc", 8, 5, 0, 0 },
-#define F_GT (F_OVERFLOWCLR + 1)
- { "gt", 9, 5, 0, 1 },
-#define F_GE (F_GT + 1)
- { "ge", 10, 5, 0, 1 },
-#define F_LT (F_GE + 1)
- { "lt", 11, 5, 0, 1 },
-#define F_LE (F_LT + 1)
- { "le", 12, 5, 0, 1 },
-#define F_HI (F_LE + 1)
- { "hi", 13, 5, 0, 1 },
-#define F_LS (F_HI + 1)
- { "ls", 14, 5, 0, 1 },
-#define F_PNZ (F_LS + 1)
- { "pnz", 15, 5, 0, 1 },
-#define F_NJ (F_PNZ + 1)
- { "nj", 21, 5, 0, 1 },
-#define F_NM (F_NJ + 1)
- { "nm", 23, 5, 0, 1 },
-#define F_NO_T (F_NM + 1)
- { "nt", 24, 5, 0, 1 },
-
- /* FLAG. */
-#define F_FLAG (F_NO_T + 1)
- { "f", 1, 1, 15, 1 },
-#define F_FFAKE (F_FLAG + 1)
- { "f", 0, 0, 0, 1 },
-
- /* Delay slot. */
-#define F_ND (F_FFAKE + 1)
- { "nd", 0, 1, 5, 0 },
-#define F_D (F_ND + 1)
- { "d", 1, 1, 5, 1 },
-#define F_DFAKE (F_D + 1)
- { "d", 0, 0, 0, 1 },
-#define F_DNZ_ND (F_DFAKE + 1)
- { "nd", 0, 1, 16, 0 },
-#define F_DNZ_D (F_DNZ_ND + 1)
- { "d", 1, 1, 16, 1 },
-
- /* Data size. */
-#define F_SIZEB1 (F_DNZ_D + 1)
- { "b", 1, 2, 1, 1 },
-#define F_SIZEB7 (F_SIZEB1 + 1)
- { "b", 1, 2, 7, 1 },
-#define F_SIZEB17 (F_SIZEB7 + 1)
- { "b", 1, 2, 17, 1 },
-#define F_SIZEW1 (F_SIZEB17 + 1)
- { "w", 2, 2, 1, 0 },
-#define F_SIZEW7 (F_SIZEW1 + 1)
- { "w", 2, 2, 7, 0 },
-#define F_SIZEW17 (F_SIZEW7 + 1)
- { "w", 2, 2, 17, 0 },
-
- /* Sign extension. */
-#define F_SIGN6 (F_SIZEW17 + 1)
- { "x", 1, 1, 6, 1 },
-#define F_SIGN16 (F_SIGN6 + 1)
- { "x", 1, 1, 16, 1 },
-#define F_SIGNX (F_SIGN16 + 1)
- { "x", 0, 0, 0, 1 },
-
- /* Address write-back modes. */
-#define F_A3 (F_SIGNX + 1)
- { "a", 1, 2, 3, 0 },
-#define F_A9 (F_A3 + 1)
- { "a", 1, 2, 9, 0 },
-#define F_A22 (F_A9 + 1)
- { "a", 1, 2, 22, 0 },
-#define F_AW3 (F_A22 + 1)
- { "aw", 1, 2, 3, 1 },
-#define F_AW9 (F_AW3 + 1)
- { "aw", 1, 2, 9, 1 },
-#define F_AW22 (F_AW9 + 1)
- { "aw", 1, 2, 22, 1 },
-#define F_AB3 (F_AW22 + 1)
- { "ab", 2, 2, 3, 1 },
-#define F_AB9 (F_AB3 + 1)
- { "ab", 2, 2, 9, 1 },
-#define F_AB22 (F_AB9 + 1)
- { "ab", 2, 2, 22, 1 },
-#define F_AS3 (F_AB22 + 1)
- { "as", 3, 2, 3, 1 },
-#define F_AS9 (F_AS3 + 1)
- { "as", 3, 2, 9, 1 },
-#define F_AS22 (F_AS9 + 1)
- { "as", 3, 2, 22, 1 },
-#define F_ASFAKE (F_AS22 + 1)
- { "as", 0, 0, 0, 1 },
-
- /* Cache bypass. */
-#define F_DI5 (F_ASFAKE + 1)
- { "di", 1, 1, 5, 1 },
-#define F_DI11 (F_DI5 + 1)
- { "di", 1, 1, 11, 1 },
-#define F_DI14 (F_DI11 + 1)
- { "di", 1, 1, 14, 1 },
-#define F_DI15 (F_DI14 + 1)
- { "di", 1, 1, 15, 1 },
-
- /* ARCv2 specific. */
-#define F_NT (F_DI15 + 1)
- { "nt", 0, 1, 3, 1},
-#define F_T (F_NT + 1)
- { "t", 1, 1, 3, 1},
-#define F_H1 (F_T + 1)
- { "h", 2, 2, 1, 1 },
-#define F_H7 (F_H1 + 1)
- { "h", 2, 2, 7, 1 },
-#define F_H17 (F_H7 + 1)
- { "h", 2, 2, 17, 1 },
-#define F_SIZED (F_H17 + 1)
- { "dd", 8, 0, 0, 0 }, /* Fake. */
-
- /* Fake Flags. */
-#define F_NE (F_SIZED + 1)
- { "ne", 0, 0, 0, 1 },
-
- /* ARC NPS400 Support: See comment near head of file. */
-#define F_NPS_CL (F_NE + 1)
- { "cl", 0, 0, 0, 1 },
-
-#define F_NPS_NA (F_NPS_CL + 1)
- { "na", 1, 1, 9, 1 },
-
-#define F_NPS_SR (F_NPS_NA + 1)
- { "s", 1, 1, 13, 1 },
-
-#define F_NPS_M (F_NPS_SR + 1)
- { "m", 1, 1, 7, 1 },
-
-#define F_NPS_FLAG (F_NPS_M + 1)
- { "f", 1, 1, 20, 1 },
-
-#define F_NPS_R (F_NPS_FLAG + 1)
- { "r", 1, 1, 15, 1 },
-
-#define F_NPS_RW (F_NPS_R + 1)
- { "rw", 0, 1, 7, 1 },
-
-#define F_NPS_RD (F_NPS_RW + 1)
- { "rd", 1, 1, 7, 1 },
-
-#define F_NPS_WFT (F_NPS_RD + 1)
- { "wft", 0, 0, 0, 1 },
-
-#define F_NPS_IE1 (F_NPS_WFT + 1)
- { "ie1", 1, 2, 8, 1 },
-
-#define F_NPS_IE2 (F_NPS_IE1 + 1)
- { "ie2", 2, 2, 8, 1 },
-
-#define F_NPS_IE12 (F_NPS_IE2 + 1)
- { "ie12", 3, 2, 8, 1 },
-
-#define F_NPS_SYNC_RD (F_NPS_IE12 + 1)
- { "rd", 0, 1, 6, 1 },
-
-#define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1)
- { "wr", 1, 1, 6, 1 },
-
-#define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1)
- { "off", 0, 0, 0, 1 },
-
-#define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1)
- { "restore", 0, 0, 0, 1 },
-
-#define F_NPS_SX (F_NPS_HWS_RESTORE + 1)
- { "sx", 1, 1, 14, 1 },
-
-#define F_NPS_AR (F_NPS_SX + 1)
- { "ar", 0, 1, 0, 1 },
-
-#define F_NPS_AL (F_NPS_AR + 1)
- { "al", 1, 1, 0, 1 },
-
-#define F_NPS_S (F_NPS_AL + 1)
- { "s", 0, 0, 0, 1 },
-
-#define F_NPS_ZNCV_RD (F_NPS_S + 1)
- { "rd", 0, 1, 15, 1 },
-
-#define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1)
- { "wr", 1, 1, 15, 1 },
-
-#define F_NPS_P0 (F_NPS_ZNCV_WR + 1)
- { "p0", 0, 0, 0, 1 },
-
-#define F_NPS_P1 (F_NPS_P0 + 1)
- { "p1", 0, 0, 0, 1 },
-
-#define F_NPS_P2 (F_NPS_P1 + 1)
- { "p2", 0, 0, 0, 1 },
-
-#define F_NPS_P3 (F_NPS_P2 + 1)
- { "p3", 0, 0, 0, 1 },
-
-#define F_NPS_LDBIT_DI (F_NPS_P3 + 1)
- { "di", 0, 0, 0, 1 },
-
-#define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1)
- { "cl", 1, 1, 6, 1 },
-
-#define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1)
- { "cl", 1, 1, 16, 1 },
-
-#define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1)
- { "x2", 1, 2, 9, 1 },
-
-#define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1)
- { "x2", 1, 2, 22, 1 },
-
-#define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1)
- { "x4", 2, 2, 9, 1 },
-
-#define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1)
- { "x4", 2, 2, 22, 1 },
-
-#define F_NPS_CORE (F_NPS_LDBIT_X4_2 + 1)
- { "core", 1, 3, 6, 1 },
-
-#define F_NPS_CLSR (F_NPS_CORE + 1)
- { "clsr", 2, 3, 6, 1 },
-
-#define F_NPS_ALL (F_NPS_CLSR + 1)
- { "all", 3, 3, 6, 1 },
-
-#define F_NPS_GIC (F_NPS_ALL + 1)
- { "gic", 4, 3, 6, 1 },
-
-#define F_NPS_RSPI_GIC (F_NPS_GIC + 1)
- { "gic", 5, 3, 6, 1 },
-};
-
-const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
-
-/* Table of the flag classes.
-
- The format of the table is
- CLASS {FLAG_CODE}. */
-const struct arc_flag_class arc_flag_classes[] =
-{
-#define C_EMPTY 0
- { F_CLASS_NONE, { F_NULL } },
-
-#define C_CC_EQ (C_EMPTY + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_EQUAL, F_NULL} },
-
-#define C_CC_GE (C_CC_EQ + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GE, F_NULL} },
-
-#define C_CC_GT (C_CC_GE + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GT, F_NULL} },
-
-#define C_CC_HI (C_CC_GT + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_HI, F_NULL} },
-
-#define C_CC_HS (C_CC_HI + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTCARRY, F_NULL} },
-
-#define C_CC_LE (C_CC_HS + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LE, F_NULL} },
-
-#define C_CC_LO (C_CC_LE + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_CARRY, F_NULL} },
-
-#define C_CC_LS (C_CC_LO + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LS, F_NULL} },
-
-#define C_CC_LT (C_CC_LS + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LT, F_NULL} },
-
-#define C_CC_NE (C_CC_LT + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTEQUAL, F_NULL} },
-
-#define C_AA_AB (C_CC_NE + 1)
- {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AB3, F_NULL} },
-
-#define C_AA_AW (C_AA_AB + 1)
- {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AW3, F_NULL} },
-
-#define C_ZZ_D (C_AA_AW + 1)
- {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZED, F_NULL} },
-
-#define C_ZZ_H (C_ZZ_D + 1)
- {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_H1, F_NULL} },
-
-#define C_ZZ_B (C_ZZ_H + 1)
- {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEB1, F_NULL} },
-
-#define C_CC (C_ZZ_B + 1)
- { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND,
- { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
- F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
- F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
- F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
- F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
- F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T, F_NULL } },
-
-#define C_AA_ADDR3 (C_CC + 1)
-#define C_AA27 (C_CC + 1)
- { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
-#define C_AA_ADDR9 (C_AA_ADDR3 + 1)
-#define C_AA21 (C_AA_ADDR3 + 1)
- { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
-#define C_AA_ADDR22 (C_AA_ADDR9 + 1)
-#define C_AA8 (C_AA_ADDR9 + 1)
- { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
-
-#define C_F (C_AA_ADDR22 + 1)
- { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
-#define C_FHARD (C_F + 1)
- { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
-
-#define C_T (C_FHARD + 1)
- { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
-#define C_D (C_T + 1)
- { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
-#define C_DNZ_D (C_D + 1)
- { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL } },
-
-#define C_DHARD (C_DNZ_D + 1)
- { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
-
-#define C_DI20 (C_DHARD + 1)
- { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
-#define C_DI14 (C_DI20 + 1)
- { F_CLASS_OPTIONAL, { F_DI14, F_NULL }},
-#define C_DI16 (C_DI14 + 1)
- { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
-#define C_DI26 (C_DI16 + 1)
- { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
-
-#define C_X25 (C_DI26 + 1)
- { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
-#define C_X15 (C_X25 + 1)
- { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
-#define C_XHARD (C_X15 + 1)
-#define C_X (C_X15 + 1)
- { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
-
-#define C_ZZ13 (C_X + 1)
- { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
-#define C_ZZ23 (C_ZZ13 + 1)
- { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
-#define C_ZZ29 (C_ZZ23 + 1)
- { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
-
-#define C_AS (C_ZZ29 + 1)
- { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
-
-#define C_NE (C_AS + 1)
- { F_CLASS_REQUIRED, { F_NE, F_NULL}},
-
- /* ARC NPS400 Support: See comment near head of file. */
-#define C_NPS_CL (C_NE + 1)
- { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
-
-#define C_NPS_NA (C_NPS_CL + 1)
- { F_CLASS_OPTIONAL, { F_NPS_NA, F_NULL}},
-
-#define C_NPS_SR (C_NPS_NA + 1)
- { F_CLASS_OPTIONAL, { F_NPS_SR, F_NULL}},
-
-#define C_NPS_M (C_NPS_SR + 1)
- { F_CLASS_OPTIONAL, { F_NPS_M, F_NULL}},
-
-#define C_NPS_F (C_NPS_M + 1)
- { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
-
-#define C_NPS_R (C_NPS_F + 1)
- { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}},
-
-#define C_NPS_SCHD_RW (C_NPS_R + 1)
- { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}},
-
-#define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1)
- { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}},
-
-#define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1)
- { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}},
-
-#define C_NPS_SYNC (C_NPS_SCHD_IE + 1)
- { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}},
-
-#define C_NPS_HWS_OFF (C_NPS_SYNC + 1)
- { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}},
-
-#define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1)
- { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}},
-
-#define C_NPS_SX (C_NPS_HWS_RESTORE + 1)
- { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}},
-
-#define C_NPS_AR_AL (C_NPS_SX + 1)
- { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}},
-
-#define C_NPS_S (C_NPS_AR_AL + 1)
- { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}},
-
-#define C_NPS_ZNCV (C_NPS_S + 1)
- { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}},
-
-#define C_NPS_P0 (C_NPS_ZNCV + 1)
- { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }},
-
-#define C_NPS_P1 (C_NPS_P0 + 1)
- { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }},
-
-#define C_NPS_P2 (C_NPS_P1 + 1)
- { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }},
-
-#define C_NPS_P3 (C_NPS_P2 + 1)
- { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }},
-
-#define C_NPS_LDBIT_DI (C_NPS_P3 + 1)
- { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }},
-
-#define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1)
- { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }},
-
-#define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1)
- { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }},
-
-#define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1)
- { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }},
-
-#define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1)
- { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }},
-
-#define C_NPS_CORE (C_NPS_LDBIT_X_2 + 1)
- { F_CLASS_REQUIRED, { F_NPS_CORE, F_NULL}},
-
-#define C_NPS_CLSR (C_NPS_CORE + 1)
- { F_CLASS_REQUIRED, { F_NPS_CLSR, F_NULL}},
-
-#define C_NPS_ALL (C_NPS_CLSR + 1)
- { F_CLASS_REQUIRED, { F_NPS_ALL, F_NULL}},
-
-#define C_NPS_GIC (C_NPS_ALL + 1)
- { F_CLASS_REQUIRED, { F_NPS_GIC, F_NULL}},
-
-#define C_NPS_RSPI_GIC (C_NPS_GIC + 1)
- { F_CLASS_REQUIRED, { F_NPS_RSPI_GIC, F_NULL}},
-};
-
-const unsigned char flags_none[] = { 0 };
-const unsigned char flags_f[] = { C_F };
-const unsigned char flags_cc[] = { C_CC };
-const unsigned char flags_ccf[] = { C_CC, C_F };
-
-/* The operands table.
-
- The format of the operands table is:
-
- BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
-const struct arc_operand arc_operands[] =
-{
- /* The fields are bits, shift, insert, extract, flags. The zero
- index is used to indicate end-of-list. */
-#define UNUSED 0
- { 0, 0, 0, 0, 0, 0 },
-
-#define IGNORED (UNUSED + 1)
- { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 },
-
- /* The plain integer register fields. Used by 32 bit
- instructions. */
-#define RA (IGNORED + 1)
- { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
-#define RA_CHK (RA + 1)
- { 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0 },
-#define RB (RA_CHK + 1)
- { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
-#define RB_CHK (RB + 1)
- { 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb },
-#define RC (RB_CHK + 1)
- { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
-#define RBdup (RC + 1)
- { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
-
-#define RAD (RBdup + 1)
- { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
-#define RAD_CHK (RAD + 1)
- { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
-#define RCD (RAD_CHK + 1)
- { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
-#define RBD (RCD + 1)
- { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rbd, extract_rb },
-#define RBDdup (RBD + 1)
- { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_TRUNCATE,
- insert_rbd, extract_rb },
-
- /* The plain integer register fields. Used by short
- instructions. */
-#define RA16 (RBDdup + 1)
-#define RA_S (RBDdup + 1)
- { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
-#define RB16 (RA16 + 1)
-#define RB_S (RA16 + 1)
- { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
-#define RB16dup (RB16 + 1)
-#define RB_Sdup (RB16 + 1)
- { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
-#define RC16 (RB16dup + 1)
-#define RC_S (RB16dup + 1)
- { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
-#define R6H (RC16 + 1) /* 6bit register field 'h' used
- by V1 cpus. */
- { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
-#define R5H (R6H + 1) /* 5bit register field 'h' used
- by V2 cpus. */
-#define RH_S (R6H + 1) /* 5bit register field 'h' used
- by V2 cpus. */
- { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
-#define R5Hdup (R5H + 1)
-#define RH_Sdup (R5H + 1)
- { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
- insert_rhv2, extract_rhv2 },
-
-#define RG (R5Hdup + 1)
-#define G_S (R5Hdup + 1)
- { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
-
- /* Fix registers. */
-#define R0 (RG + 1)
-#define R0_S (RG + 1)
- { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
-#define R1 (R0 + 1)
-#define R1_S (R0 + 1)
- { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
-#define R2 (R1 + 1)
-#define R2_S (R1 + 1)
- { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
-#define R3 (R2 + 1)
-#define R3_S (R2 + 1)
- { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
-#define RSP (R3 + 1)
-#define SP_S (R3 + 1)
- { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
-#define SPdup (RSP + 1)
-#define SP_Sdup (RSP + 1)
- { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
-#define GP (SPdup + 1)
-#define GP_S (SPdup + 1)
- { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
-
-#define PCL_S (GP + 1)
- { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
-
-#define BLINK (PCL_S + 1)
-#define BLINK_S (PCL_S + 1)
- { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
-
-#define ILINK1 (BLINK + 1)
- { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
-#define ILINK2 (ILINK1 + 1)
- { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
-
- /* Long immediate. */
-#define LIMM (ILINK2 + 1)
-#define LIMM_S (ILINK2 + 1)
- { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
-#define LIMMdup (LIMM + 1)
- { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
-
- /* Special operands. */
-#define ZA (LIMMdup + 1)
-#define ZB (LIMMdup + 1)
-#define ZA_S (LIMMdup + 1)
-#define ZB_S (LIMMdup + 1)
-#define ZC_S (LIMMdup + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
-
-#define RRANGE_EL (ZA + 1)
- { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
- insert_rrange, extract_rrange},
-#define R13_EL (RRANGE_EL + 1)
- { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
- insert_r13el, extract_rrange },
-#define FP_EL (R13_EL + 1)
- { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
- insert_fpel, extract_fpel },
-#define BLINK_EL (FP_EL + 1)
- { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
- insert_blinkel, extract_blinkel },
-#define PCL_EL (BLINK_EL + 1)
- { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
- insert_pclel, extract_pclel },
-
- /* Fake operand to handle the T flag. */
-#define BRAKET (PCL_EL + 1)
-#define BRAKETdup (PCL_EL + 1)
- { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
-
- /* Fake operand to handle the T flag. */
-#define FKT_T (BRAKET + 1)
- { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
- /* Fake operand to handle the T flag. */
-#define FKT_NT (FKT_T + 1)
- { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
-
- /* UIMM6_20 mask = 00000000000000000000111111000000. */
-#define UIMM6_20 (FKT_NT + 1)
- {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
-
- /* Exactly like the above but used by relaxation. */
-#define UIMM6_20R (UIMM6_20 + 1)
- {6, 0, -UIMM6_20R, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
- insert_uimm6_20, extract_uimm6_20},
-
- /* SIMM12_20 mask = 00000000000000000000111111222222. */
-#define SIMM12_20 (UIMM6_20R + 1)
- {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
-
- /* Exactly like the above but used by relaxation. */
-#define SIMM12_20R (SIMM12_20 + 1)
- {12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL,
- insert_simm12_20, extract_simm12_20},
-
- /* UIMM12_20 mask = 00000000000000000000111111222222. */
-#define UIMM12_20 (SIMM12_20R + 1)
- {12, 0, 0, ARC_OPERAND_UNSIGNED, insert_simm12_20, extract_uimm12_20},
-
- /* SIMM3_5_S mask = 0000011100000000. */
-#define SIMM3_5_S (UIMM12_20 + 1)
- {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
- insert_simm3s, extract_simm3s},
-
- /* UIMM7_A32_11_S mask = 0000000000011111. */
-#define UIMM7_A32_11_S (SIMM3_5_S + 1)
- {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
- extract_uimm7_a32_11_s},
-
- /* The same as above but used by relaxation. */
-#define UIMM7_A32_11R_S (UIMM7_A32_11_S + 1)
- {7, 0, -UIMM7_A32_11R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL,
- insert_uimm7_a32_11_s, extract_uimm7_a32_11_s},
-
- /* UIMM7_9_S mask = 0000000001111111. */
-#define UIMM7_9_S (UIMM7_A32_11R_S + 1)
- {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
-
- /* UIMM3_13_S mask = 0000000000000111. */
-#define UIMM3_13_S (UIMM7_9_S + 1)
- {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
-
- /* Exactly like the above but used for relaxation. */
-#define UIMM3_13R_S (UIMM3_13_S + 1)
- {3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
- insert_uimm3_13_s, extract_uimm3_13_s},
-
- /* SIMM11_A32_7_S mask = 0000000111111111. */
-#define SIMM11_A32_7_S (UIMM3_13R_S + 1)
- {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
- | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
-
- /* UIMM6_13_S mask = 0000000002220111. */
-#define UIMM6_13_S (SIMM11_A32_7_S + 1)
- {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
- /* UIMM5_11_S mask = 0000000000011111. */
-#define UIMM5_11_S (UIMM6_13_S + 1)
- {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
- extract_uimm5_11_s},
-
- /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
-#define SIMM9_A16_8 (UIMM5_11_S + 1)
- {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
- | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
- extract_simm9_a16_8},
-
- /* UIMM6_8 mask = 00000000000000000000111111000000. */
-#define UIMM6_8 (SIMM9_A16_8 + 1)
- {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
-
- /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
-#define SIMM21_A16_5 (UIMM6_8 + 1)
- {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
- | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
- insert_simm21_a16_5, extract_simm21_a16_5},
-
- /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
-#define SIMM25_A16_5 (SIMM21_A16_5 + 1)
- {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
- | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
- insert_simm25_a16_5, extract_simm25_a16_5},
-
- /* SIMM10_A16_7_S mask = 0000000111111111. */
-#define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
- {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
- extract_simm10_a16_7_s},
-
-#define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
- {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
- | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
-
- /* SIMM7_A16_10_S mask = 0000000000111111. */
-#define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
- {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
- extract_simm7_a16_10_s},
-
- /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
-#define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
- {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
- extract_simm21_a32_5},
-
- /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
-#define SIMM25_A32_5 (SIMM21_A32_5 + 1)
- {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
- extract_simm25_a32_5},
-
- /* SIMM13_A32_5_S mask = 0000011111111111. */
-#define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
- {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
- extract_simm13_a32_5_s},
-
- /* SIMM8_A16_9_S mask = 0000000001111111. */
-#define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
- {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
- extract_simm8_a16_9_s},
-
-/* UIMM10_6_S_JLIOFF mask = 0000001111111111. */
-#define UIMM10_6_S_JLIOFF (SIMM8_A16_9_S + 1)
- {12, 0, BFD_RELOC_ARC_JLI_SECTOFF, ARC_OPERAND_UNSIGNED
- | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_uimm10_6_s,
- extract_uimm10_6_s},
-
- /* UIMM3_23 mask = 00000000000000000000000111000000. */
-#define UIMM3_23 (UIMM10_6_S_JLIOFF + 1)
- {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
-
- /* UIMM10_6_S mask = 0000001111111111. */
-#define UIMM10_6_S (UIMM3_23 + 1)
- {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
-
- /* UIMM6_11_S mask = 0000002200011110. */
-#define UIMM6_11_S (UIMM10_6_S + 1)
- {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
-
- /* SIMM9_8 mask = 00000000111111112000000000000000. */
-#define SIMM9_8 (UIMM6_11_S + 1)
- {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
- insert_simm9_8, extract_simm9_8},
-
- /* The same as above but used by relaxation. */
-#define SIMM9_8R (SIMM9_8 + 1)
- {9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE
- | ARC_OPERAND_PCREL, insert_simm9_8, extract_simm9_8},
-
- /* UIMM10_A32_8_S mask = 0000000011111111. */
-#define UIMM10_A32_8_S (SIMM9_8R + 1)
- {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
- extract_uimm10_a32_8_s},
-
- /* SIMM9_7_S mask = 0000000111111111. */
-#define SIMM9_7_S (UIMM10_A32_8_S + 1)
- {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
- extract_simm9_7_s},
-
- /* UIMM6_A16_11_S mask = 0000000000011111. */
-#define UIMM6_A16_11_S (SIMM9_7_S + 1)
- {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
- extract_uimm6_a16_11_s},
-
- /* UIMM5_A32_11_S mask = 0000020000011000. */
-#define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
- {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
- extract_uimm5_a32_11_s},
-
- /* SIMM11_A32_13_S mask = 0000022222200111. */
-#define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
- {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
- | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
-
- /* UIMM7_13_S mask = 0000000022220111. */
-#define UIMM7_13_S (SIMM11_A32_13_S + 1)
- {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
-
- /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
-#define UIMM6_A16_21 (UIMM7_13_S + 1)
- {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
- | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
-
- /* UIMM7_11_S mask = 0000022200011110. */
-#define UIMM7_11_S (UIMM6_A16_21 + 1)
- {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
-
- /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
-#define UIMM7_A16_20 (UIMM7_11_S + 1)
- {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
- extract_uimm7_a16_20},
-
- /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
-#define SIMM13_A16_20 (UIMM7_A16_20 + 1)
- {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
- | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
- extract_simm13_a16_20},
-
- /* UIMM8_8_S mask = 0000000011111111. */
-#define UIMM8_8_S (SIMM13_A16_20 + 1)
- {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
-
- /* The same as above but used for relaxation. */
-#define UIMM8_8R_S (UIMM8_8_S + 1)
- {8, 0, -UIMM8_8R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
- insert_uimm8_8_s, extract_uimm8_8_s},
-
- /* W6 mask = 00000000000000000000111111000000. */
-#define W6 (UIMM8_8R_S + 1)
- {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
-
- /* UIMM6_5_S mask = 0000011111100000. */
-#define UIMM6_5_S (W6 + 1)
- {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
-
- /* ARC NPS400 Support: See comment near head of file. */
-#define NPS_R_DST_3B (UIMM6_5_S + 1)
- { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
-
-#define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
- { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
-
-#define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
- { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2 },
-
-#define NPS_R_DST (NPS_R_SRC2_3B + 1)
- { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
-
-#define NPS_R_SRC1 (NPS_R_DST + 1)
- { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
-
-#define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
- { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
-
-#define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
- { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
-
-#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
- { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_bitop_size, extract_nps_bitop_size },
-
-#define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
- { 5, 0, 0, ARC_OPERAND_UNSIGNED,
- insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
-
-#define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
-
-#define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
- { 8, 0, 0, ARC_OPERAND_UNSIGNED,
- insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
-
-#define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
- { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_SIMM16 (NPS_UIMM16 + 1)
- { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL },
-
-#define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1)
- { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
-
-#define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1)
- { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 },
-
-#define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_src2_pos, extract_nps_src2_pos },
-
-#define NPS_SRC1_POS (NPS_SRC2_POS + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_src1_pos, extract_nps_src1_pos },
-
-#define NPS_ADDB_SIZE (NPS_SRC1_POS + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_addb_size, extract_nps_addb_size },
-
-#define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_andb_size, extract_nps_andb_size },
-
-#define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_fxorb_size, extract_nps_fxorb_size },
-
-#define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_wxorb_size, extract_nps_wxorb_size },
-
-#define NPS_R_XLDST (NPS_WXORB_SIZE + 1)
- { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL },
-
-#define NPS_DIV_UIMM4 (NPS_R_XLDST + 1)
- { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_qcmp_size, extract_nps_qcmp_size },
-
-#define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1)
- { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 },
-
-#define NPS_QCMP_M2 (NPS_QCMP_M1 + 1)
- { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 },
-
-#define NPS_QCMP_M3 (NPS_QCMP_M2 + 1)
- { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 },
-
-#define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_calc_entry_size, extract_nps_calc_entry_size },
-
-#define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1)
- { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
-
-#define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1)
- { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
-
-#define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1)
- { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_5_src2, extract_nps_3bit_reg_at_5_src2 },
-
-#define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1)
- { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_bitop2_size, extract_nps_bitop2_size },
-
-#define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1)
- { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_bitop1_size, extract_nps_bitop1_size },
-
-#define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1)
- { 5, 0, 0, ARC_OPERAND_UNSIGNED,
- insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 },
-
-#define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1)
- { 5, 42, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1)
- { 5, 37, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1)
- { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1)
- { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1)
- { 5, 32, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1)
- { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1)
- { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1)
- { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_MOD4 (NPS_BITOP_SRC_POS1 + 1)
- { 2, 0, 0, ARC_OPERAND_UNSIGNED,
- insert_nps_bitop_mod4, extract_nps_bitop_mod4 },
-
-#define NPS_BITOP_MOD3 (NPS_BITOP_MOD4 + 1)
- { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1)
- { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1)
- { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1)
- { 5, 20, 0, ARC_OPERAND_UNSIGNED,
- insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext },
-
-#define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1)
- { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1)
- { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_field_size, extract_nps_field_size },
-
-#define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1)
- { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_shift_factor, extract_nps_shift_factor },
-
-#define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1)
- { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_bits_to_scramble, extract_nps_bits_to_scramble },
-
-#define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1)
- { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1)
- { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_bdlen_max_len, extract_nps_bdlen_max_len },
-
-#define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1)
- { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_min_hofs, extract_nps_min_hofs },
-
-#define NPS_PSBC (NPS_MIN_HOFS + 1)
- { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_DPI_DST (NPS_PSBC + 1)
- { 5, 11, 0, ARC_OPERAND_IR, NULL, NULL },
-
- /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B
- but doesn't duplicate an operand. */
-#define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1)
- { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
-
-#define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1)
- { 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_hash_width, extract_nps_hash_width },
-
-#define NPS_HASH_PERM (NPS_HASH_WIDTH + 1)
- { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1)
- { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1)
- { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1)
- { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_hash_len, extract_nps_hash_len },
-
-#define NPS_HASH_OFS (NPS_HASH_LEN + 1)
- { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1)
- { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1)
- { 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1)
- { 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1)
- { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1)
- { 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_index3, extract_nps_index3 },
-
-#define COLON (NPS_E4BY_INDEX3 + 1)
- { 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL },
-
-#define NPS_BD (COLON + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_bd, extract_nps_bd },
-
-#define NPS_JID (NPS_BD + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_jid, extract_nps_jid },
-
-#define NPS_LBD (NPS_JID + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_lbd, extract_nps_lbd },
-
-#define NPS_MBD (NPS_LBD + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_mbd, extract_nps_mbd },
-
-#define NPS_SD (NPS_MBD + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_sd, extract_nps_sd },
-
-#define NPS_SM (NPS_SD + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_sm, extract_nps_sm },
-
-#define NPS_XA (NPS_SM + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_xa, extract_nps_xa },
-
-#define NPS_XD (NPS_XA + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_xd, extract_nps_xd },
-
-#define NPS_CD (NPS_XD + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_cd, extract_nps_cd },
-
-#define NPS_CBD (NPS_CD + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_cbd, extract_nps_cbd },
-
-#define NPS_CJID (NPS_CBD + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_cjid, extract_nps_cjid },
-
-#define NPS_CLBD (NPS_CJID + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_clbd, extract_nps_clbd },
-
-#define NPS_CM (NPS_CLBD + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_cm, extract_nps_cm },
-
-#define NPS_CSD (NPS_CM + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_csd, extract_nps_csd },
-
-#define NPS_CXA (NPS_CSD + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_cxa, extract_nps_cxa },
-
-#define NPS_CXD (NPS_CXA + 1)
- { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
- insert_nps_cxd, extract_nps_cxd },
-
-#define NPS_BD_TYPE (NPS_CXD + 1)
- { 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_BMU_NUM (NPS_BD_TYPE + 1)
- { 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_bd_num_buff, extract_nps_bd_num_buff },
-
-#define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1)
- { 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_WHASH_SIZE (NPS_PMU_NXT_DST + 1)
- { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_size_16bit, extract_nps_size_16bit },
-
-#define NPS_PMU_NUM_JOB (NPS_WHASH_SIZE + 1)
- { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_pmu_num_job, extract_nps_pmu_num_job },
-
-#define NPS_DMA_IMM_ENTRY (NPS_PMU_NUM_JOB + 1)
- { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_imm_entry, extract_nps_imm_entry },
-
-#define NPS_DMA_IMM_OFFSET (NPS_DMA_IMM_ENTRY + 1)
- { 4, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_imm_offset, extract_nps_imm_offset },
-
-#define NPS_MISC_IMM_SIZE (NPS_DMA_IMM_OFFSET + 1)
- { 7, 0, 0, ARC_OPERAND_UNSIGNED , NULL, NULL },
-
-#define NPS_MISC_IMM_OFFSET (NPS_MISC_IMM_SIZE + 1)
- { 5, 8, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_misc_imm_offset, extract_nps_misc_imm_offset },
-
-#define NPS_R_DST_3B_48 (NPS_MISC_IMM_OFFSET + 1)
- { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
-
-#define NPS_R_SRC1_3B_48 (NPS_R_DST_3B_48 + 1)
- { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
-
-#define NPS_R_SRC2_3B_48 (NPS_R_SRC1_3B_48 + 1)
- { 3, 37, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_37_src2, extract_nps_3bit_reg_at_37_src2 },
-
-#define NPS_R_DST_3B_64 (NPS_R_SRC2_3B_48 + 1)
- { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
-
-#define NPS_R_SRC1_3B_64 (NPS_R_DST_3B_64 + 1)
- { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
-
-#define NPS_R_SRC2_3B_64 (NPS_R_SRC1_3B_64 + 1)
- { 3, 53, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
- insert_nps_3bit_reg_at_53_src2, extract_nps_3bit_reg_at_53_src2 },
-
-#define NPS_RA_64 (NPS_R_SRC2_3B_64 + 1)
- { 6, 53, 0, ARC_OPERAND_IR, NULL, NULL },
-
-#define NPS_RB_64 (NPS_RA_64 + 1)
- { 5, 48, 0, ARC_OPERAND_IR, NULL, NULL },
-
-#define NPS_RBdup_64 (NPS_RB_64 + 1)
- { 5, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
-
-#define NPS_RBdouble_64 (NPS_RBdup_64 + 1)
- { 10, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
- insert_nps_rbdouble_64, extract_nps_rbdouble_64 },
-
-#define NPS_RC_64 (NPS_RBdouble_64 + 1)
- { 5, 43, 0, ARC_OPERAND_IR, NULL, NULL },
-
-#define NPS_UIMM16_0_64 (NPS_RC_64 + 1)
- { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-
-#define NPS_PROTO_SIZE (NPS_UIMM16_0_64 + 1)
- { 6, 16, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_proto_size, extract_nps_proto_size }
-};
-const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
-
-const unsigned arc_Toperand = FKT_T;
-const unsigned arc_NToperand = FKT_NT;
-
-const unsigned char arg_none[] = { 0 };
-const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC };
-const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC };
-const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC };
-const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 };
-const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 };
-const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 };
-const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 };
-const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC };
-const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM };
-const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC };
-const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM };
-
-const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM };
-const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 };
-const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 };
-
-const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 };
-const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup };
-const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup };
-
-const unsigned char arg_32bit_rbrc[] = { RB, RC };
-const unsigned char arg_32bit_zarc[] = { ZA, RC };
-const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 };
-const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 };
-const unsigned char arg_32bit_rblimm[] = { RB, LIMM };
-const unsigned char arg_32bit_zalimm[] = { ZA, LIMM };
-
-const unsigned char arg_32bit_limmrc[] = { LIMM, RC };
-const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 };
-const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 };
-const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup };
-
-const unsigned char arg_32bit_rc[] = { RC };
-const unsigned char arg_32bit_u6[] = { UIMM6_20 };
-const unsigned char arg_32bit_limm[] = { LIMM };
+#include "arcxx-opc.inc"
+
+/* Common combinations of FLAGS. */
+#define FLAGS_NONE { 0 }
+#define FLAGS_F { C_F }
+#define FLAGS_CC { C_CC }
+#define FLAGS_CCF { C_CC, C_F }
+
+/* Common combination of arguments. */
+#define ARG_NONE { 0 }
+#define ARG_32BIT_RARBRC { RA, RB, RC }
+#define ARG_32BIT_ZARBRC { ZA, RB, RC }
+#define ARG_32BIT_RBRBRC { RB, RBdup, RC }
+#define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 }
+#define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 }
+#define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 }
+#define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 }
+#define ARG_32BIT_RALIMMRC { RA, LIMM, RC }
+#define ARG_32BIT_RARBLIMM { RA, RB, LIMM }
+#define ARG_32BIT_ZALIMMRC { ZA, LIMM, RC }
+#define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM }
+
+#define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM }
+#define ARG_32BIT_RALIMMU6 { RA, LIMM, UIMM6_20 }
+#define ARG_32BIT_ZALIMMU6 { ZA, LIMM, UIMM6_20 }
+
+#define ARG_32BIT_ZALIMMS12 { ZA, LIMM, SIMM12_20 }
+#define ARG_32BIT_RALIMMLIMM { RA, LIMM, LIMMdup }
+#define ARG_32BIT_ZALIMMLIMM { ZA, LIMM, LIMMdup }
+
+#define ARG_32BIT_RBRC { RB, RC }
+#define ARG_32BIT_ZARC { ZA, RC }
+#define ARG_32BIT_RBU6 { RB, UIMM6_20 }
+#define ARG_32BIT_ZAU6 { ZA, UIMM6_20 }
+#define ARG_32BIT_RBLIMM { RB, LIMM }
+#define ARG_32BIT_ZALIMM { ZA, LIMM }
+
+/* Macro to generate 2 operand extension instruction. */
+#define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL) \
+ { NAME, INSN2OP_BC (MOP,SOP), MINSN2OP_BC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRC, FL }, \
+ { NAME, INSN2OP_0C (MOP,SOP), MINSN2OP_0C, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZARC, FL }, \
+ { NAME, INSN2OP_BU (MOP,SOP), MINSN2OP_BU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBU6, FL }, \
+ { NAME, INSN2OP_0U (MOP,SOP), MINSN2OP_0U, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZAU6, FL }, \
+ { NAME, INSN2OP_BL (MOP,SOP), MINSN2OP_BL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBLIMM, FL }, \
+ { NAME, INSN2OP_0L (MOP,SOP), MINSN2OP_0L, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMM, FL },
+
+#define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \
+ EXTINSN2OPF (NAME, CPU, CLASS, SCLASS, MOP, SOP, FLAGS_F)
+
+/* Macro to generate 3 operand extesion instruction. */
+#define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \
+ { NAME, INSN3OP_ABC (MOP,SOP), MINSN3OP_ABC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RARBRC, FLAGS_F }, \
+ { NAME, INSN3OP_0BC (MOP,SOP), MINSN3OP_0BC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZARBRC, FLAGS_F }, \
+ { NAME, INSN3OP_CBBC (MOP,SOP), MINSN3OP_CBBC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBRC, FLAGS_CCF }, \
+ { NAME, INSN3OP_ABU (MOP,SOP), MINSN3OP_ABU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RARBU6, FLAGS_F }, \
+ { NAME, INSN3OP_0BU (MOP,SOP), MINSN3OP_0BU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZARBU6, FLAGS_F }, \
+ { NAME, INSN3OP_CBBU (MOP,SOP), MINSN3OP_CBBU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBU6, FLAGS_CCF }, \
+ { NAME, INSN3OP_BBS (MOP,SOP), MINSN3OP_BBS, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBS12, FLAGS_F }, \
+ { NAME, INSN3OP_ALC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RALIMMRC, FLAGS_F }, \
+ { NAME, INSN3OP_ABL (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RARBLIMM, FLAGS_F }, \
+ { NAME, INSN3OP_0LC (MOP,SOP), MINSN3OP_0LC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMRC, FLAGS_F }, \
+ { NAME, INSN3OP_0BL (MOP,SOP), MINSN3OP_0BL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZARBLIMM, FLAGS_F }, \
+ { NAME, INSN3OP_C0LC (MOP,SOP), MINSN3OP_C0LC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMRC, FLAGS_CCF }, \
+ { NAME, INSN3OP_CBBL (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBLIMM, FLAGS_CCF }, \
+ { NAME, INSN3OP_ALU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RALIMMU6, FLAGS_F }, \
+ { NAME, INSN3OP_0LU (MOP,SOP), MINSN3OP_0LU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMU6, FLAGS_F }, \
+ { NAME, INSN3OP_C0LU (MOP,SOP), MINSN3OP_C0LU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMU6, FLAGS_CCF }, \
+ { NAME, INSN3OP_0LS (MOP,SOP), MINSN3OP_0LS, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMS12, FLAGS_F }, \
+ { NAME, INSN3OP_ALL (MOP,SOP), MINSN3OP_ALL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RALIMMLIMM, FLAGS_F }, \
+ { NAME, INSN3OP_0LL (MOP,SOP), MINSN3OP_0LL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMLIMM, FLAGS_F }, \
+ { NAME, INSN3OP_C0LL (MOP,SOP), MINSN3OP_C0LL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMLIMM, FLAGS_CCF },
/* The opcode table.
mnemonic, so we end up with two groups for the sync instruction, the
first within the core arc instruction table, and the second within the
nps extension instructions. */
+
const struct arc_opcode arc_opcodes[] =
{
#include "arc-tbl.h"
#include "arc-nps400-tbl.h"
-#include "arc-ext-tbl.h"
-
- { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
-};
-
-/* List with special cases instructions and the applicable flags. */
-const struct arc_flag_special arc_flag_special_cases[] =
-{
- { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
- F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
- F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
- F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM,
- F_NO_T, F_NULL } },
- { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
- F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
- F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
- F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
- { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
- F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
- F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
- F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
- { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
- F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
- F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
- F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
- { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
- F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
- F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
- F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
- { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
- F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
- F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
- F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
- { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
- F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
- F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
- F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
- { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
- { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
-};
-
-const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
-
-/* Relocations. */
-const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
-{
- { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
- BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
- { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
- BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
- { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
- BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
- { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
- BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
-
- /* Next two entries will cover the undefined behavior ldb/stb with
- address scaling. */
- { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
- BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
- { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
- BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
-
- { "sda", "ld", { F_ASFAKE, F_NULL },
- BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
- { "sda", "st", { F_ASFAKE, F_NULL },
- BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
- { "sda", "ldd", { F_ASFAKE, F_NULL },
- BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
- { "sda", "std", { F_ASFAKE, F_NULL },
- BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
-
- /* Short instructions. */
- { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
- { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
- { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
- { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
-
- { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
- { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
-
- { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
- BFD_RELOC_ARC_S25H_PCREL_PLT },
- { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
- BFD_RELOC_ARC_S21H_PCREL_PLT },
- { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
- BFD_RELOC_ARC_S25W_PCREL_PLT },
- { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
- BFD_RELOC_ARC_S21W_PCREL_PLT },
-
- { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
-};
-
-const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
-
-const struct arc_pseudo_insn arc_pseudo_insns[] =
-{
- { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
- { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
- { BRAKETdup, 1, 0, 4} } },
- { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
- { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
- { BRAKETdup, 1, 0, 4} } },
-
- { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
- { SIMM9_A16_8, 0, 0, 2 } } },
-
- { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
- { SIMM9_A16_8, 0, 0, 2 } } },
-
- { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
- { SIMM9_A16_8, 0, 0, 2 } } },
-
- { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
- { SIMM9_A16_8, 0, 0, 2 } } },
- { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
- { SIMM9_A16_8, 0, 0, 2 } } },
-};
-
-const unsigned arc_num_pseudo_insn =
- sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
-
-const struct arc_aux_reg arc_aux_regs[] =
-{
-#undef DEF
-#define DEF(ADDR, CPU, SUBCLASS, NAME) \
- { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
-
-#include "arc-regs.h"
-#undef DEF
-};
-
-const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
-
-/* NOTE: The order of this array MUST be consistent with 'enum
- arc_rlx_types' located in tc-arc.h! */
-const struct arc_opcode arc_relax_opcodes[] =
-{
- { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
-
- /* bl_s s13 11111sssssssssss. */
- { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
- { SIMM13_A32_5_S }, { 0 }},
-
- /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
- { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
- { SIMM25_A32_5 }, { C_D }},
-
- /* b_s s10 1111000sssssssss. */
- { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
- { SIMM10_A16_7_S }, { 0 }},
-
- /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
- { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
- { SIMM25_A16_5 }, { C_D }},
-
- /* add_s c,b,u3 01101bbbccc00uuu. */
- { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
-
- /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */
- { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RA, RB, UIMM6_20R }, { C_F }},
-
- /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
- { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RA, RB, LIMM }, { C_F }},
-
- /* ld_s c,b,u7 10000bbbcccuuuuu. */
- { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RC_S, BRAKET, RB_S, UIMM7_A32_11R_S, BRAKETdup }, { 0 }},
-
- /* ld<.di><.aa><.x><zz> a,b,s9
- 00010bbbssssssssSBBBDaaZZXAAAAAA. */
- { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RA, BRAKET, RB, SIMM9_8R, BRAKETdup },
- { C_ZZ23, C_DI20, C_AA21, C_X25 }},
-
- /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
- { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RA, BRAKET, RB, LIMM, BRAKETdup },
- { C_ZZ13, C_DI16, C_AA8, C_X15 }},
-
- /* mov_s b,u8 11011bbbuuuuuuuu. */
- { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RB_S, UIMM8_8R_S }, { 0 }},
-
- /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */
- { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RB, SIMM12_20R }, { C_F }},
+ /* Extension instruction declarations. */
+ EXTINSN2OP ("dsp_fp_flt2i", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43)
+ EXTINSN2OP ("dsp_fp_i2flt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 44)
+ EXTINSN2OP ("dsp_fp_sqrt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 45)
- /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
- { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RB, LIMM }, { C_F }},
+ EXTINSN3OP ("dsp_fp_div", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 42)
+ EXTINSN3OP ("dsp_fp_cmp", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43)
- /* sub_s c,b,u3 01101bbbccc01uuu. */
- { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
-
- /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */
- { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RA, RB, UIMM6_20R }, { C_F }},
-
- /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
- { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RA, RB, LIMM }, { C_F }},
-
- /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */
- { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
- | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20R }, { C_F }},
-
- /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
- { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
- | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
-
- /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */
- { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RB, UIMM6_20R }, { C_F, C_CC }},
-
- /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
- { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RB, LIMM }, { C_F, C_CC }},
-
- /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */
- { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RB, RBdup, UIMM6_20R }, { C_F, C_CC }},
-
- /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
- { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RB, RBdup, LIMM }, { C_F, C_CC }}
+ { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
};
-
-const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
-
-/* Return length of an opcode in bytes. */
-
-int
-arc_opcode_len (const struct arc_opcode *opcode)
-{
- if (opcode->mask < 0x10000ull)
- return 2;
-
- if (opcode->mask < 0x100000000ull)
- return 4;
-
- if (opcode->mask < 0x1000000000000ull)
- return 6;
-
- return 8;
-}
--- /dev/null
+/* ARC operands defintions.
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+ Contributed by Claudiu Zissulescu (claziss@synopsys.com)
+ Refactored by Cupertino Miranda (cmiranda@synopsys.com)
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+
+/*
+ * ARC_OPERAND(NAME, BITS, SHIFT, RELO, FLAGS, FUN)
+ *
+ * BITS => The number of bits in the operand.
+ * SHIFT => How far the operand is left shifted in the instruction.
+ * RELO => The default relocation type for this operand.
+ * FLAGS => One bit syntax flags.
+ * FUN => Insertion function. This is used by the assembler.
+*/
+
+ARC_OPERAND(IGNORED, 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0)
+
+/* The plain integer register fields. Used by 32 bit instructions. */
+ARC_OPERAND(RA, 6, 0, 0, ARC_OPERAND_IR, 0, 0)
+ARC_OPERAND(RA_CHK, 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0)
+ARC_OPERAND(RB, 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb)
+ARC_OPERAND(RB_CHK, 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb)
+ARC_OPERAND(RBB_S, 6, 12, 0, ARC_OPERAND_IR, insert_rbb, extract_rbb)
+ARC_OPERAND(RC, 6, 6, 0, ARC_OPERAND_IR, 0, 0)
+ARC_OPERAND(RC_CHK, 6, 6, 0, ARC_OPERAND_IR, 0, 0)
+ARC_OPERAND(RBdup, 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb)
+
+ARC_OPERAND(RAD, 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0)
+ARC_OPERAND(RAD_CHK, 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0)
+ARC_OPERAND(RCD, 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0)
+ARC_OPERAND(RBD, 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rbd, extract_rb)
+ARC_OPERAND(RBDdup, 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_TRUNCATE, insert_rbd, extract_rb)
+
+/* The plain integer register fields. Used by short instructions. */
+ARC_OPERAND(RA16, 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras)
+ARC_OPERAND(RA_S, 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras)
+ARC_OPERAND(RB16, 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs)
+ARC_OPERAND(RB_S, 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs)
+ARC_OPERAND(RB16dup, 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs)
+ARC_OPERAND(RB_Sdup, 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs)
+ARC_OPERAND(RC16, 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs)
+ARC_OPERAND(RC_S, 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs)
+
+/* 6bit register field 'h' used by V1 cpus. */
+ARC_OPERAND(R6H, 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1)
+/* 5bit register field 'h' used by V2 cpus. */
+ARC_OPERAND(R5H, 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2)
+ARC_OPERAND(RH_S, 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2)
+ARC_OPERAND(R5Hdup, 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rhv2, extract_rhv2)
+ARC_OPERAND(RH_Sdup, 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rhv2, extract_rhv2)
+
+ARC_OPERAND(RG, 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s)
+ARC_OPERAND(G_S, 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s)
+
+/* Fix registers. */
+ARC_OPERAND(R0, 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0)
+ARC_OPERAND(R0_S, 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0)
+ARC_OPERAND(R1, 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1)
+ARC_OPERAND(R1_S, 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1)
+ARC_OPERAND(R2, 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2)
+ARC_OPERAND(R2_S, 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2)
+ARC_OPERAND(R3, 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3)
+ARC_OPERAND(R3_S, 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3)
+ARC_OPERAND(RSP, 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp)
+ARC_OPERAND(SP_S, 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp)
+ARC_OPERAND(SPdup, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp)
+ARC_OPERAND(SP_Sdup, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp)
+ARC_OPERAND(GP, 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp)
+ARC_OPERAND(GP_S, 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp)
+
+ARC_OPERAND(PCL_S, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl)
+
+ARC_OPERAND(BLINK, 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink)
+ARC_OPERAND(BLINK_S, 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink)
+
+ARC_OPERAND(ILINK1, 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1)
+ARC_OPERAND(ILINK2, 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2)
+
+ /* Long immediate. */
+ARC_OPERAND(LIMM, 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0)
+ARC_OPERAND(LIMM_S, 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0)
+ARC_OPERAND(LO32, 32, 0, BFD_RELOC_ARC_LO32_ME, ARC_OPERAND_LIMM, insert_limm, 0)
+ARC_OPERAND(HI32, 32, 0, BFD_RELOC_ARC_HI32_ME, ARC_OPERAND_LIMM, insert_limm, 0)
+ARC_OPERAND(LIMM34, 34, 0, BFD_RELOC_ARC_PCLO32_ME_2, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_limm, 0)
+ARC_OPERAND(XIMM_S, 32, 0, BFD_RELOC_ARC_LO32_ME, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_limm, 0)
+ARC_OPERAND(XIMM, 32, 0, BFD_RELOC_ARC_LO32_ME, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_limm, 0)
+ARC_OPERAND(LIMMdup, 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0)
+ARC_OPERAND(XIMMdup, 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE | ARC_OPERAND_SIGNED, insert_limm, 0)
+
+ /* Special operands. */
+ARC_OPERAND(ZA, 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0)
+ARC_OPERAND(ZB, 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0)
+ARC_OPERAND(ZA_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0)
+ARC_OPERAND(ZB_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0)
+ARC_OPERAND(ZC_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0)
+
+ARC_OPERAND(RRANGE_EL, 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE, insert_rrange, extract_rrange)
+ARC_OPERAND(R13_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, insert_r13el, extract_rrange)
+ARC_OPERAND(FP_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, insert_fpel, extract_fpel)
+ARC_OPERAND(BLINK_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, insert_blinkel, extract_blinkel)
+ARC_OPERAND(PCL_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, insert_pclel, extract_pclel)
+
+ /* Fake operand to handle the T flag. */
+ARC_OPERAND(BRAKET, 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0)
+ARC_OPERAND(BRAKETdup, 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0)
+
+ /* Fake operand to handle the T flag. */
+ARC_OPERAND(FKT_T, 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0)
+ /* Fake operand to handle the T flag. */
+ARC_OPERAND(FKT_NT, 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0)
+
+ /* UIMM6_20 mask = 00000000000000000000111111000000. */
+ARC_OPERAND(UIMM6_20, 6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20)
+
+ /* Exactly like the above but used by relaxation. */
+ARC_OPERAND(UIMM6_20R, 6, 0, -UIMM6_20R, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, insert_uimm6_20, extract_uimm6_20)
+
+ /* SIMM12_20 mask = 00000000000000000000111111222222. */
+ARC_OPERAND(SIMM12_20, 12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20)
+
+ /* Exactly like the above but used by relaxation. */
+ARC_OPERAND(SIMM12_20R, 12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL, insert_simm12_20, extract_simm12_20)
+
+ /* UIMM12_20 mask = 00000000000000000000111111222222. */
+ARC_OPERAND(UIMM12_20, 12, 0, 0, ARC_OPERAND_UNSIGNED, insert_simm12_20, extract_uimm12_20)
+
+ /* SIMM3_5_S mask = 0000011100000000. */
+ARC_OPERAND(SIMM3_5_S, 3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK, insert_simm3s, extract_simm3s)
+
+ /* UIMM7_A32_11_S mask = 0000000000011111. */
+ARC_OPERAND(UIMM7_A32_11_S, 7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s, extract_uimm7_a32_11_s)
+
+ /* The same as above but used by relaxation. */
+ARC_OPERAND(UIMM7_A32_11R_S, 7, 0, -UIMM7_A32_11R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL, insert_uimm7_a32_11_s, extract_uimm7_a32_11_s)
+
+ARC_OPERAND(UIMM9_A32_11_S, 9, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm9_a32_11_s, extract_uimm9_a32_11_s)
+
+ /* UIMM7_9_S mask = 0000000001111111. */
+ARC_OPERAND(UIMM7_9_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s)
+
+ /* UIMM3_13_S mask = 0000000000000111. */
+ARC_OPERAND(UIMM3_13_S, 3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s)
+
+ /* Exactly like the above but used for relaxation. */
+ARC_OPERAND(UIMM3_13R_S, 3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, insert_uimm3_13_s, extract_uimm3_13_s)
+
+ /* SIMM11_A32_7_S mask = 0000000111111111. */
+ARC_OPERAND(SIMM11_A32_7_S, 11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s)
+
+ /* UIMM6_13_S mask = 0000000002220111. */
+ARC_OPERAND(UIMM6_13_S, 6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s)
+ /* UIMM5_11_S mask = 0000000000011111. */
+ARC_OPERAND(UIMM5_11_S, 5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s, extract_uimm5_11_s)
+
+ /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
+ARC_OPERAND(SIMM9_A16_8, 9, 0, BFD_RELOC_ARC_S9H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8, extract_simm9_a16_8)
+
+ /* UIMM6_8 mask = 00000000000000000000111111000000. */
+ARC_OPERAND(UIMM6_8, 6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8)
+
+ /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
+ARC_OPERAND(SIMM21_A16_5, 21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a16_5, extract_simm21_a16_5)
+
+ /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
+ARC_OPERAND(SIMM25_A16_5, 25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a16_5, extract_simm25_a16_5)
+
+ /* SIMM10_A16_7_S mask = 0000000111111111. */
+ARC_OPERAND(SIMM10_A16_7_S, 10, 0, BFD_RELOC_ARC_S10H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s, extract_simm10_a16_7_s)
+
+ARC_OPERAND(SIMM10_A16_7_Sbis, 10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s)
+
+ /* SIMM7_A16_10_S mask = 0000000000111111. */
+ARC_OPERAND(SIMM7_A16_10_S, 7, 0, BFD_RELOC_ARC_S7H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s, extract_simm7_a16_10_s)
+
+ /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
+ARC_OPERAND(SIMM21_A32_5, 21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5, extract_simm21_a32_5)
+
+ /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
+ARC_OPERAND(SIMM25_A32_5, 25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5, extract_simm25_a32_5)
+
+ /* SIMM13_A32_5_S mask = 0000011111111111. */
+ARC_OPERAND(SIMM13_A32_5_S, 13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s, extract_simm13_a32_5_s)
+
+ /* SIMM8_A16_9_S mask = 0000000001111111. */
+ARC_OPERAND(SIMM8_A16_9_S, 8, 0, BFD_RELOC_ARC_S8H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s, extract_simm8_a16_9_s)
+
+/* UIMM10_6_S_JLIOFF mask = 0000001111111111. */
+ARC_OPERAND(UIMM10_6_S_JLIOFF, 12, 0, BFD_RELOC_ARC_JLI_SECTOFF, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_uimm10_6_s, extract_uimm10_6_s)
+
+ /* UIMM3_23 mask = 00000000000000000000000111000000. */
+ARC_OPERAND(UIMM3_23, 3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23)
+
+ /* UIMM10_6_S mask = 0000001111111111. */
+ARC_OPERAND(UIMM10_6_S, 10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s)
+
+ARC_OPERAND(UIMM10_13_S, 10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_13_s, extract_uimm10_13_s)
+
+ /* UIMM6_11_S mask = 0000002200011110. */
+ARC_OPERAND(UIMM6_11_S, 6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s)
+
+ /* SIMM9_8 mask = 00000000111111112000000000000000. */
+ARC_OPERAND(SIMM9_8, 9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE, insert_simm9_8, extract_simm9_8)
+
+ /* The same as above but used by relaxation. */
+ARC_OPERAND(SIMM9_8R, 9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL, insert_simm9_8, extract_simm9_8)
+
+ /* UIMM10_A32_8_S mask = 0000000011111111. */
+ARC_OPERAND(UIMM10_A32_8_S, 10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s, extract_uimm10_a32_8_s)
+
+ /* SIMM9_7_S mask = 0000000111111111. */
+ARC_OPERAND(SIMM9_7_S, 9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s, extract_simm9_7_s)
+
+ /* UIMM6_A16_11_S mask = 0000000000011111. */
+ARC_OPERAND(UIMM6_A16_11_S, 6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s, extract_uimm6_a16_11_s)
+
+ /* UIMM5_A32_11_S mask = 0000020000011000. */
+ARC_OPERAND(UIMM5_A32_11_S, 5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s, extract_uimm5_a32_11_s)
+
+ /* SIMM11_A32_13_S mask = 0000022222200111. */
+ARC_OPERAND(SIMM11_A32_13_S, 11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s)
+
+ /* UIMM7_13_S mask = 0000000022220111. */
+ARC_OPERAND(UIMM7_13_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s)
+
+ /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
+ARC_OPERAND(UIMM6_A16_21, 6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21)
+
+ /* UIMM7_11_S mask = 0000022200011110. */
+ARC_OPERAND(UIMM7_11_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s)
+
+ /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
+ARC_OPERAND(UIMM7_A16_20, 7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20, extract_uimm7_a16_20)
+
+ /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
+ARC_OPERAND(SIMM13_A16_20, 13, 0, BFD_RELOC_ARC_S13H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20, extract_simm13_a16_20)
+
+ /* UIMM8_8_S mask = 0000000011111111. */
+ARC_OPERAND(UIMM8_8_S, 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s)
+
+ /* The same as above but used for relaxation. */
+ARC_OPERAND(UIMM8_8R_S, 8, 0, -UIMM8_8R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, insert_uimm8_8_s, extract_uimm8_8_s)
+
+ /* W6 mask = 00000000000000000000111111000000. */
+ARC_OPERAND(W6, 6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6)
+
+ /* UIMM6_5_S mask = 0000011111100000. */
+ARC_OPERAND(UIMM6_5_S, 6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s)
+
+ /* ARC NPS400 Support: See comment near head of file. */
+ARC_OPERAND(NPS_R_DST_3B, 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst)
+
+ARC_OPERAND(NPS_R_SRC1_3B, 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst)
+
+ARC_OPERAND(NPS_R_SRC2_3B, 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2)
+
+ARC_OPERAND(NPS_R_DST, 6, 21, 0, ARC_OPERAND_IR, NULL, NULL)
+
+ARC_OPERAND(NPS_R_SRC1, 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_DST_POS, 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0)
+
+ARC_OPERAND(NPS_BITOP_SRC_POS, 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0)
+
+ARC_OPERAND(NPS_BITOP_SIZE, 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size)
+
+ARC_OPERAND(NPS_BITOP_DST_POS_SZ, 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size)
+
+ARC_OPERAND(NPS_BITOP_SIZE_2B, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b)
+
+ARC_OPERAND(NPS_BITOP_UIMM8, 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8)
+
+ARC_OPERAND(NPS_UIMM16, 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_SIMM16, 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_RFLT_UIMM6, 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6)
+
+ARC_OPERAND(NPS_XLDST_UIMM16, 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_cmem_uimm16, extract_nps_cmem_uimm16)
+
+ARC_OPERAND(NPS_SRC2_POS, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src2_pos, extract_nps_src2_pos)
+
+ARC_OPERAND(NPS_SRC1_POS, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src1_pos, extract_nps_src1_pos)
+
+ARC_OPERAND(NPS_ADDB_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_addb_size, extract_nps_addb_size)
+
+ARC_OPERAND(NPS_ANDB_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_andb_size, extract_nps_andb_size)
+
+ARC_OPERAND(NPS_FXORB_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_fxorb_size, extract_nps_fxorb_size)
+
+ARC_OPERAND(NPS_WXORB_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_wxorb_size, extract_nps_wxorb_size)
+
+ARC_OPERAND(NPS_R_XLDST, 6, 5, 0, ARC_OPERAND_IR, NULL, NULL)
+
+ARC_OPERAND(NPS_DIV_UIMM4, 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_QCMP_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_qcmp_size, extract_nps_qcmp_size)
+
+ARC_OPERAND(NPS_QCMP_M1, 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1)
+
+ARC_OPERAND(NPS_QCMP_M2, 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2)
+
+ARC_OPERAND(NPS_QCMP_M3, 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3)
+
+ARC_OPERAND(NPS_CALC_ENTRY_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_calc_entry_size, extract_nps_calc_entry_size)
+
+ARC_OPERAND(NPS_R_DST_3B_SHORT, 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst)
+
+ARC_OPERAND(NPS_R_SRC1_3B_SHORT, 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst)
+
+ARC_OPERAND(NPS_R_SRC2_3B_SHORT, 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_5_src2, extract_nps_3bit_reg_at_5_src2)
+
+ARC_OPERAND(NPS_BITOP_SIZE2, 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop2_size, extract_nps_bitop2_size)
+
+ARC_OPERAND(NPS_BITOP_SIZE1, 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop1_size, extract_nps_bitop1_size)
+
+ARC_OPERAND(NPS_BITOP_DST_POS3_POS4, 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4)
+
+ARC_OPERAND(NPS_BITOP_DST_POS4, 5, 42, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_DST_POS3, 5, 37, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_DST_POS2, 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_DST_POS1, 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_SRC_POS4, 5, 32, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_SRC_POS3, 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_SRC_POS2, 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_SRC_POS1, 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_MOD4, 2, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_mod4, extract_nps_bitop_mod4)
+
+ARC_OPERAND(NPS_BITOP_MOD3, 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_MOD2, 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_MOD1, 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BITOP_INS_EXT, 5, 20, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext)
+
+ARC_OPERAND(NPS_FIELD_START_POS, 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_FIELD_SIZE, 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_field_size, extract_nps_field_size)
+
+ARC_OPERAND(NPS_SHIFT_FACTOR, 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_shift_factor, extract_nps_shift_factor)
+
+ARC_OPERAND(NPS_BITS_TO_SCRAMBLE, 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bits_to_scramble, extract_nps_bits_to_scramble)
+
+ARC_OPERAND(NPS_SRC2_POS_5B, 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BDLEN_MAX_LEN, 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bdlen_max_len, extract_nps_bdlen_max_len)
+
+ARC_OPERAND(NPS_MIN_HOFS, 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_min_hofs, extract_nps_min_hofs)
+
+ARC_OPERAND(NPS_PSBC, 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_DPI_DST, 5, 11, 0, ARC_OPERAND_IR, NULL, NULL)
+
+ /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B
+ but doesn't duplicate an operand. */
+ARC_OPERAND(NPS_DPI_SRC1_3B, 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst)
+
+ARC_OPERAND(NPS_HASH_WIDTH, 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_width, extract_nps_hash_width)
+
+ARC_OPERAND(NPS_HASH_PERM, 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_HASH_NONLINEAR, 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_HASH_BASEMAT, 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_HASH_LEN, 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_len, extract_nps_hash_len)
+
+ARC_OPERAND(NPS_HASH_OFS, 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_HASH_BASEMAT2, 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_E4BY_INDEX0, 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_E4BY_INDEX1, 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_E4BY_INDEX2, 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_E4BY_INDEX3, 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_index3, extract_nps_index3)
+
+ARC_OPERAND(COLON, 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL)
+
+ARC_OPERAND(NPS_BD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_bd, extract_nps_bd)
+
+ARC_OPERAND(NPS_JID, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_jid, extract_nps_jid)
+
+ARC_OPERAND(NPS_LBD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_lbd, extract_nps_lbd)
+
+ARC_OPERAND(NPS_MBD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_mbd, extract_nps_mbd)
+
+ARC_OPERAND(NPS_SD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sd, extract_nps_sd)
+
+ARC_OPERAND(NPS_SM, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sm, extract_nps_sm)
+
+ARC_OPERAND(NPS_XA, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xa, extract_nps_xa)
+
+ARC_OPERAND(NPS_XD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xd, extract_nps_xd)
+
+ARC_OPERAND(NPS_CD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cd, extract_nps_cd)
+
+ARC_OPERAND(NPS_CBD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cbd, extract_nps_cbd)
+
+ARC_OPERAND(NPS_CJID, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cjid, extract_nps_cjid)
+
+ARC_OPERAND(NPS_CLBD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_clbd, extract_nps_clbd)
+
+ARC_OPERAND(NPS_CM, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cm, extract_nps_cm)
+
+ARC_OPERAND(NPS_CSD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_csd, extract_nps_csd)
+
+ARC_OPERAND(NPS_CXA, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxa, extract_nps_cxa)
+
+ARC_OPERAND(NPS_CXD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxd, extract_nps_cxd)
+
+ARC_OPERAND(NPS_BD_TYPE, 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_BMU_NUM, 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bd_num_buff, extract_nps_bd_num_buff)
+
+ARC_OPERAND(NPS_PMU_NXT_DST, 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_WHASH_SIZE, 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_size_16bit, extract_nps_size_16bit)
+
+ARC_OPERAND(NPS_PMU_NUM_JOB, 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_pmu_num_job, extract_nps_pmu_num_job)
+
+ARC_OPERAND(NPS_DMA_IMM_ENTRY, 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_imm_entry, extract_nps_imm_entry)
+
+ARC_OPERAND(NPS_DMA_IMM_OFFSET, 4, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_imm_offset, extract_nps_imm_offset)
+
+ARC_OPERAND(NPS_MISC_IMM_SIZE, 7, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_MISC_IMM_OFFSET, 5, 8, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_misc_imm_offset, extract_nps_misc_imm_offset)
+
+ARC_OPERAND(NPS_R_DST_3B_48, 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst)
+
+ARC_OPERAND(NPS_R_SRC1_3B_48, 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst)
+
+ARC_OPERAND(NPS_R_SRC2_3B_48, 3, 37, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_37_src2, extract_nps_3bit_reg_at_37_src2)
+
+ARC_OPERAND(NPS_R_DST_3B_64, 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst)
+
+ARC_OPERAND(NPS_R_SRC1_3B_64, 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst)
+
+ARC_OPERAND(NPS_R_SRC2_3B_64, 3, 53, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_53_src2, extract_nps_3bit_reg_at_53_src2)
+
+ARC_OPERAND(NPS_RA_64, 6, 53, 0, ARC_OPERAND_IR, NULL, NULL)
+
+ARC_OPERAND(NPS_RB_64, 5, 48, 0, ARC_OPERAND_IR, NULL, NULL)
+
+ARC_OPERAND(NPS_RBdup_64, 5, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL)
+
+ARC_OPERAND(NPS_RBdouble_64, 10, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_rbdouble_64, extract_nps_rbdouble_64)
+
+ARC_OPERAND(NPS_RC_64, 5, 43, 0, ARC_OPERAND_IR, NULL, NULL)
+
+ARC_OPERAND(NPS_UIMM16_0_64, 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL)
+
+ARC_OPERAND(NPS_PROTO_SIZE, 6, 16, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_proto_size, extract_nps_proto_size)
+
+ /* ARC64's floating point registers. */
+ARC_OPERAND(FA, 5, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_FP, 0, 0)
+ARC_OPERAND(FB, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_FP, 0, 0)
+ARC_OPERAND(FC, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_FP, insert_fs2, extract_fs2)
+ARC_OPERAND(FD, 5, 19, 0, ARC_OPERAND_IR | ARC_OPERAND_FP, 0, 0)
+
+ /* Double 128 registers, the same like above but only the odd ones
+ allowed. */
+ARC_OPERAND(FDA, 5, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_FP | ARC_OPERAND_TRUNCATE, 0, 0)
+ARC_OPERAND(FDB, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_FP | ARC_OPERAND_TRUNCATE, 0, 0)
+ARC_OPERAND(FDC, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_FP | ARC_OPERAND_TRUNCATE, insert_fs2, extract_fs2)
+ARC_OPERAND(FDD, 5, 19, 0, ARC_OPERAND_IR | ARC_OPERAND_FP | ARC_OPERAND_TRUNCATE, 0, 0)
+
+ /* 5bit integer registers used by fp instructions. */
+ARC_OPERAND(FRD, 5, 6, 0, ARC_OPERAND_IR, 0, 0)
+ARC_OPERAND(FRB, 5, 0, 0, ARC_OPERAND_IR, insert_fs2, extract_fs2)
+
+ /* 5bit unsigned immediate used by vfext and vfins. */
+ARC_OPERAND(UIMM5_FP, 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_fs2, extract_fs2)
DEF (0xc0, ARC_OPCODE_ARCALL, NONE, bpu_build)
DEF (0xc1, ARC_OPCODE_ARC600, NONE, arc600_build_config)
DEF (0xc1, ARC_OPCODE_ARC700, NONE, isa_config)
-DEF (0xc1, ARC_OPCODE_ARCV2, NONE, isa_config)
+DEF (0xc1, ARC_OPCODE_ARCVx, NONE, isa_config)
DEF (0xf4, ARC_OPCODE_ARCALL, NONE, hwp_build)
DEF (0xf5, ARC_OPCODE_ARCALL, NONE, pct_build)
DEF (0xf6, ARC_OPCODE_ARCALL, NONE, cc_build)
DEF (0x452, ARC_OPCODE_ARC600, NONE, dvfs_performance)
DEF (0x453, ARC_OPCODE_ARC600, NONE, pwr_ctrl)
DEF (0x460, ARC_OPCODE_ARCv2HS, NONE, tlbpd0)
+DEF (0x460, ARC_OPCODE_ARC64, NONE, mmu_rtp0_lo)
DEF (0x461, ARC_OPCODE_ARCv2HS, NONE, tlbpd1)
+DEF (0x461, ARC_OPCODE_ARC64, NONE, mmu_rtp0_hi)
+DEF (0x462, ARC_OPCODE_ARC64, NONE, mmu_rtp1_lo)
+DEF (0x463, ARC_OPCODE_ARC64, NONE, mmu_rtp1_hi)
DEF (0x464, ARC_OPCODE_ARCv2HS, NONE, tlbindex)
DEF (0x465, ARC_OPCODE_ARCv2HS, NONE, tlbcommand)
DEF (0x468, ARC_OPCODE_ARCv2HS, NONE, pid)
DEF (0x46c, ARC_OPCODE_ARCv2HS, NONE, scratch_data0)
+DEF (0x468, ARC_OPCODE_ARC64, NONE, mmu_ctrl)
+DEF (0x469, ARC_OPCODE_ARC64, NONE, mmu_ttbc)
DEF (0x500, ARC_OPCODE_ARC700, NONE, aux_vlc_buf_idx)
DEF (0x501, ARC_OPCODE_ARC700, NONE, aux_vlc_read_buf)
DEF (0x502, ARC_OPCODE_ARC700, NONE, aux_vlc_valid_bits)
--- /dev/null
+/* Opcode table for ARC64.
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+ Contributed by Claudiu Zissulescu (claziss@synopsys.com)
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+#include "arcxx-opc.inc"
+
+#define F32_BR0 0x00
+#define F32_BR1 0x01
+#define F32_LD_OFFSET 0x02
+#define F32_ST_OFFSET 0x03
+#define F32_GEN4 0x04
+#define F32_EXT5 0x05
+#define F32_EXT6 0x06
+#define F32_APEX 0x07
+
+#define F16_COMPACT0 0x08
+#define F16_COMPACT1 0x08
+#define F16_MOVL 0x08
+
+#define F16_LD_ADD_SUB 0x09
+
+#define LD_ST_R01 0x0A
+#define LDI_S 0x0A
+#define JLI_S_U10 0x0A
+
+#define F16_JLI_EI 0x0B
+#define F32_GEN_OP64 0x0B
+
+/* Macros required for ARCv3 floating point instructions. */
+/* Flags. */
+#define FL_NONE { 0 }
+#define FL_CC { C_FPCC }
+
+/* Arguments. */
+#define ARG_NONE { 0 }
+#define ARG_64FP_3OP { FA, FB, FC, FD }
+#define ARG_128FP_3OP { FDA, FDB, FDC, FDD }
+#define ARG_64FP_2OP { FA, FB, FC }
+#define ARG_64FP_CMP { FB, FC }
+#define ARG_128FP_2OP { FDA, FDB, FDC }
+#define ARG_64FP_1OP { FA, FC }
+#define ARG_64FP_SOP { FA, FB }
+#define ARG_128FP_SOP { FDA, FDB }
+
+#define ARG_64FP_CVI2F { FA, FRB }
+#define ARG_64FP_CVF2I { FRD, FC }
+
+/* Macros to help generating floating point pattern instructions. */
+/* Define FP_TOP. */
+#define FIELDS1(word) (word & 0x1F)
+#define FIELDS2(word) (((word & 0x07) << 24) | (((word >> 3) & 0x03) << 12))
+#define FIELDS3(word) ((word & 0x1F) << 19)
+#define FIELDD(word) ((word & 0x1F) << 6)
+#define FIELDTOP(word) (((word & 0x01) << 5) | ((word >> 1) & 0x07) << 16)
+#define FIELDP(word) ((word & 0x03) << 14)
+#define MASK_32BIT(VAL) (0xffffffff & (VAL))
+
+#define INSNFP3OP(TOPF, P) \
+ ((0x1C << 27) | FIELDTOP (TOPF) | FIELDP (P) | (1 << 11))
+#define MINSNFP3OP \
+ (MASK_32BIT (~(FIELDS1 (31) | FIELDS2 (31) | FIELDS3 (31) | FIELDD (31))))
+
+/* Define FP_DOP. */
+#define FIELDDOP(ops) ((ops & 0x1f) << 16)
+
+#define INSNFP2OP(DOPF, P) \
+ ((0x1C << 27) | FIELDDOP (DOPF) | FIELDP (P) | (1 << 5))
+#define MINSNFP2OP \
+ (MASK_32BIT (~(FIELDS2 (31) | FIELDS1 (31) | FIELDD (31))))
+
+/* Define FP_CVF2F. */
+#define FIELDCVTF(WORD) ((WORD & 0x03) << 16)
+#define FIELDU0(BIT) (BIT & 0x01)
+#define FIELDU1(BIT) (BIT & 0x02)
+#define FIELDU3(BIT) (BIT & 0x08)
+#define FIELDU4(BIT) (BIT & 0x10)
+
+#define FP_CVF2F_MACHINE(CVTF, BIT) \
+ ((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) \
+ | (1 << 5) | (1 << 2) | FIELDU0 (BIT) | FIELDU3 (BIT) | FIELDU4 (BIT))
+#define MFP_CVF2F (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FP_RND. */
+#define FP_RND_MACHINE(CVTF, BIT) \
+((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) | (1 << 5) | (0x03 << 1) \
+ | FIELDU3 (BIT))
+#define MFP_RND (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FP_CVF2I. */
+#define FP_CVF2I_MACHINE(CVTF, BIT) ((0x1C << 27) | (0x03 << 21) \
+ | FIELDCVTF (CVTF) | (1 << 5) | 1 \
+ | FIELDU3 (BIT) | FIELDU1 (BIT))
+#define MFP_CVF2I (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FMVVF2I. */
+#define FM_VVF2I(CVTF, BIT) ((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) \
+ | (1 << 5) | 1 << 4 | 1)
+#define MFM_VVF2I (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FP_SOP. */
+#define FP_SOP_MACHINE(SOPF, P) \
+ ((0x1C << 27) | (0x02 << 21) | FIELDCVTF (SOPF) | FIELDP (P) | (1 << 5))
+#define MFP_SOP_MACHINE (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31))))
+
+/* Define FP_COP. */
+#define FP_COP_MACHINE(COPF, P) \
+ ((0x1C << 27) | (0x09 << 19) | FIELDCVTF (COPF) | FIELDP (P) | (1 << 5))
+#define MFP_COP_MACHINE \
+ (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31) | FIELDS2(31))))
+
+/* Define FP_ZOP. */
+#define INSNFPZOP(COPF) \
+ ((0x1C << 27) | (0x07 << 20) | FIELDCVTF (COPF) | (1 << 5))
+
+/* Define FP_VMVI. */
+#define INSNFPVMVI(WMVF, P) \
+ ((0x1C << 27) | (0x05 << 20) | FIELDCVTF (WMVF) | FIELDP (P) | (1 << 5))
+#define MINSNFPCOP (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31) | FIELDS2 (31))))
+#define MINSNFPVMVIZ (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31))))
+
+/* Define FP_VMVR. */
+#define INSNFPVMVR(WMVF, P) \
+ ((0x1C << 27) | (0x01 << 23) | FIELDCVTF (WMVF) | FIELDP (P) | (1 << 5))
+#define MINSNFPVMVR (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31) | FIELDS2 (31))))
+
+/* Define FP_CVI2F. */
+#define INSNFPCVI2F(CVTF, BIT) ((0x1C << 27) | (0x07 << 21) | FIELDCVTF (CVTF) \
+ | (1 << 5) | FIELDU3 (BIT) | FIELDU1 (BIT))
+#define MINSNFPCVI2F (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FMVI2F. */
+#define INSNFMVI2F(CVTF, BIT) ((0x1C << 27) | (0x07 << 21) | FIELDCVTF (CVTF) \
+ | (1 << 5) | (1 << 4))
+#define MINSNFMVI2F (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FMVF2I. */
+#define INSNFMVF2I(CVTF, BIT) ((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) \
+ | (1 << 5) | (1 << 4) | (1))
+#define MINSNFMVF2I (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FP_LOAD. */
+#define FP_LOAD_ENCODING(SIZE, D) (0x0D << 27 | ((SIZE & 0x03) << 1) \
+ | ((D & 0x01) << 5))
+#define MSK_FP_LOAD (MASK_32BIT (~(FIELDB (63) | FIELDD (31) | (0x03 << 3) \
+ | (0x1FF << 15))))
+
+#define FP_LSYM_ENCODING(SIZE, D) (0x0D << 27 | ((SIZE & 0x03) << 1) \
+ | FIELDB(62) | ((D & 0x01) << 5))
+#define MSK_FP_SYM (MASK_32BIT (~(FIELDD (31))))
+
+/* Define FP_STORE. */
+#define FP_STORE_ENCODING(SIZE, D) ((0x0D << 27) | ((SIZE & 0x03) << 1) \
+ | ((D & 0x01) << 5) | (1))
+#define MSK_FP_STORE (MASK_32BIT (~(FIELDB (63) | FIELDD (31) | (0x03 << 3) \
+ | (0x1FF << 15))))
+#define FP_SSYM_ENCODING(SIZE, D) (0x0D << 27 | ((SIZE & 0x03) << 1) \
+ | FIELDB(62) | ((D & 0x01) << 5) | (1))
+
+/* FP Load/Store. */
+#define FP_LOAD(NAME, SIZE, D) \
+ { #NAME, FP_LOAD_ENCODING (SIZE, D), MSK_FP_LOAD, ARC_OPCODE_ARC64, LOAD, \
+ NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }, \
+ { #NAME, FP_LSYM_ENCODING (SIZE, D), MSK_FP_SYM, ARC_OPCODE_ARC64, LOAD, \
+ NONE, { FA, BRAKET, LIMM, BRAKETdup }, FL_NONE },
+
+#define FP_STORE(NAME, SIZE, D) \
+ { #NAME, FP_STORE_ENCODING (SIZE, D), MSK_FP_STORE, ARC_OPCODE_ARC64, STORE, \
+ NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }, \
+ { #NAME, FP_SSYM_ENCODING (SIZE, D), MSK_FP_SYM, ARC_OPCODE_ARC64, LOAD, \
+ NONE, { FA, BRAKET, LIMM, BRAKETdup }, FL_NONE },
+
+/* Macros used to generate conversion instructions. */
+#define FMVF2I_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \
+ { NAME, INSNFMVF2I (OPS, BIT), MINSNFMVF2I, CPU, CLASS, \
+ SCLASS, ARG, FL_NONE },
+
+#define FMVF2I(NAME, OPS, BIT) \
+ FMVF2I_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \
+ BIT, ARG_64FP_CVF2I)
+
+#define FMVI2F_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \
+ { NAME, INSNFMVI2F (OPS, BIT), MINSNFMVI2F, CPU, CLASS, \
+ SCLASS, ARG, FL_NONE },
+
+#define FMVI2F(NAME, OPS, BIT) \
+ FMVI2F_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \
+ BIT, ARG_64FP_CVI2F)
+
+#define FP_RND_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \
+ { NAME, FP_RND_MACHINE (OPS, BIT), MFP_RND, CPU, CLASS, \
+ SCLASS, ARG, FL_NONE },
+
+#define FP_RND(NAME, OPS, BIT) \
+ FP_RND_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \
+ BIT, ARG_64FP_1OP)
+
+#define FP_CVF2F_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \
+ { NAME, FP_CVF2F_MACHINE (OPS, BIT), MFP_CVF2F, CPU, CLASS, \
+ SCLASS, ARG, FL_NONE },
+
+#define FP_CVF2F(NAME, OPS, BIT) \
+ FP_CVF2F_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \
+ BIT, ARG_64FP_1OP)
+
+#define FP_CVF2I_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \
+ { NAME, FP_CVF2I_MACHINE (OPS, BIT), MFP_CVF2I, CPU, CLASS, \
+ SCLASS, ARG, FL_NONE },
+
+#define FP_CVF2I(NAME, OPS, BIT) \
+ FP_CVF2I_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \
+ BIT, ARG_64FP_CVF2I)
+
+#define FP_CVI2F_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \
+ { NAME, INSNFPCVI2F (OPS, BIT), MINSNFPCVI2F, CPU, CLASS, \
+ SCLASS, ARG, FL_NONE },
+
+#define FP_CVI2F(NAME, OPS, BIT) \
+ FP_CVI2F_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \
+ BIT, ARG_64FP_CVI2F)
+
+/* Macro to generate 1 operand extension instruction. */
+#define FP_SOP_INSN(NAME, CPU, CLASS, SCLASS, OPS, PRC, ARG) \
+ { NAME, FP_SOP_MACHINE (OPS, PRC), MFP_SOP_MACHINE, CPU, CLASS, SCLASS, \
+ ARG, FL_NONE },
+
+#define FP_SOP(NAME, OPS, PRECISION) \
+ FP_SOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, SOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_64FP_SOP)
+
+#define FP_SOP_D(NAME, OPS, PRECISION) \
+ FP_SOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, SOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_128FP_SOP)
+
+/* Macro to generate 2 operand extension instruction. */
+#define FP_DOP_INSN(NAME, CPU, CLASS, SCLASS, OPS, PRC, ARG) \
+ { NAME, INSNFP2OP (OPS, PRC), MINSNFP2OP, CPU, CLASS, SCLASS, \
+ ARG, FL_NONE },
+
+#define FP_DOP(NAME, OPS, PRECISION) \
+ FP_DOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, DOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_64FP_2OP)
+
+#define FP_DOPC_INSN(NAME, CPU, CLASS, SCLASS, OPS, PRC, ARG) \
+ { NAME, INSNFP2OP (OPS, PRC) | FIELDD (0), MINSNFP2OP, CPU, \
+ CLASS, SCLASS, ARG, FL_NONE },
+
+#define FP_DOP_C(NAME, OPS, PRECISION) \
+ FP_DOPC_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, DOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_64FP_CMP)
+
+#define FP_DOP_D(NAME, OPS, PRECISION) \
+ FP_DOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, DOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_128FP_2OP)
+
+/* Macro to generate 3 operand generic instruction. */
+#define FP_TOP_INSN(NAME, CPU, CLASS, SCLASS, TOPF, P, ARG) \
+ { NAME, INSNFP3OP (TOPF, P), MINSNFP3OP, CPU, CLASS, SCLASS, \
+ ARG, FL_NONE },
+
+#define FP_TOP(NAME, OPS, PRECISION) \
+ FP_TOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, TOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_64FP_3OP)
+
+#define FP_TOP_D(NAME, OPS, PRECISION) \
+ FP_TOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, TOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_128FP_3OP)
+
+/* Conditional mov instructions. */
+#define FP_COP_INSN(NAME, CPU, CLASS, SCLASS, OPS, PRC, ARG) \
+ { NAME, FP_COP_MACHINE (OPS, PRC), MFP_COP_MACHINE, CPU, CLASS, SCLASS, \
+ ARG, FL_CC },
+
+#define FP_COP(NAME, OPS, PRECISION) \
+ FP_COP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, COPF_ ## OPS, \
+ P_ ## PRECISION, ARG_64FP_SOP)
+
+#define FP_EXT(NAME, PRECISION) \
+ {#NAME, INSNFPVMVI (0x00, P_ ## PRECISION), MINSNFPCOP, \
+ ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, BRAKET, UIMM5_FP, \
+ BRAKETdup }, FL_NONE }, \
+ {#NAME, INSNFPVMVR (0x00, P_ ## PRECISION), MINSNFPVMVR, \
+ ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, BRAKET, FRB, BRAKETdup}, \
+ FL_NONE },
+
+#define FP_INS(NAME, PRECISION) \
+ {#NAME, INSNFPVMVI (0x01, P_ ## PRECISION), MINSNFPCOP, \
+ ARC_OPCODE_ARC64, FLOAT, NONE, { FA, BRAKET, UIMM5_FP, BRAKETdup, \
+ FB }, FL_NONE }, \
+ {#NAME, INSNFPVMVR (0x01, P_ ## PRECISION), MINSNFPVMVR, \
+ ARC_OPCODE_ARC64, FLOAT, NONE, { FA, BRAKET, FRB, BRAKETdup, \
+ FB }, FL_NONE },
+
+#define FP_REP(NAME, PRECISION) \
+ {#NAME, INSNFPVMVI (0x02, P_ ## PRECISION) | FIELDS2 (0x00), \
+ MINSNFPVMVIZ, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, FL_NONE },
+
+
+/* Common combinations of FLAGS. */
+#define FLAGS_NONE { 0 }
+#define FLAGS_F { C_F }
+#define FLAGS_CC { C_CC }
+#define FLAGS_CCF { C_CC, C_F }
+
+/* Common combination of arguments. */
+#define ARG_NONE { 0 }
+#define ARG_32BIT_RARBRC { RA, RB, RC }
+#define ARG_32BIT_ZARBRC { ZA, RB, RC }
+#define ARG_32BIT_RBRBRC { RB, RBdup, RC }
+#define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 }
+#define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 }
+#define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 }
+#define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 }
+#define ARG_32BIT_RALIMMRC { RA, LIMM, RC }
+#define ARG_32BIT_RARBLIMM { RA, RB, LIMM }
+#define ARG_32BIT_ZALIMMRC { ZA, LIMM, RC }
+#define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM }
+
+#define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM }
+#define ARG_32BIT_RALIMMU6 { RA, LIMM, UIMM6_20 }
+#define ARG_32BIT_ZALIMMU6 { ZA, LIMM, UIMM6_20 }
+
+#define ARG_32BIT_ZALIMMS12 { ZA, LIMM, SIMM12_20 }
+#define ARG_32BIT_RALIMMLIMM { RA, LIMM, LIMMdup }
+#define ARG_32BIT_ZALIMMLIMM { ZA, LIMM, LIMMdup }
+
+#define ARG_32BIT_RBRC { RB, RC }
+#define ARG_32BIT_ZARC { ZA, RC }
+#define ARG_32BIT_RBU6 { RB, UIMM6_20 }
+#define ARG_32BIT_ZAU6 { ZA, UIMM6_20 }
+#define ARG_32BIT_RBLIMM { RB, LIMM }
+#define ARG_32BIT_ZALIMM { ZA, LIMM }
+
+#define ARG_32BIT_RAXIMMRC { RA, XIMM, RC }
+#define ARG_32BIT_RARBXIMM { RA, RB, XIMM }
+#define ARG_32BIT_RBRBXIMM { RB, RBdup, XIMM }
+#define ARG_32BIT_RAXIMMU6 { RA, XIMM, UIMM6_20 }
+
+/* Macro to generate 2 operand extension instruction. */
+#define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL) \
+ { NAME, INSN2OP_BC (MOP,SOP), MINSN2OP_BC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRC, FL }, \
+ { NAME, INSN2OP_0C (MOP,SOP), MINSN2OP_0C, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZARC, FL }, \
+ { NAME, INSN2OP_BU (MOP,SOP), MINSN2OP_BU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBU6, FL }, \
+ { NAME, INSN2OP_0U (MOP,SOP), MINSN2OP_0U, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZAU6, FL }, \
+ { NAME, INSN2OP_BL (MOP,SOP), MINSN2OP_BL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBLIMM, FL }, \
+ { NAME, INSN2OP_0L (MOP,SOP), MINSN2OP_0L, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMM, FL },
+
+#define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \
+ EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FLAGS_F)
+
+/* Macro to generate 3 operand extesion instruction. */
+#define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \
+ { NAME, INSN3OP_ABC (MOP,SOP), MINSN3OP_ABC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RARBRC, FLAGS_F }, \
+ { NAME, INSN3OP_0BC (MOP,SOP), MINSN3OP_0BC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZARBRC, FLAGS_F }, \
+ { NAME, INSN3OP_CBBC (MOP,SOP), MINSN3OP_CBBC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBRC, FLAGS_CCF }, \
+ { NAME, INSN3OP_ABU (MOP,SOP), MINSN3OP_ABU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RARBU6, FLAGS_F }, \
+ { NAME, INSN3OP_0BU (MOP,SOP), MINSN3OP_0BU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZARBU6, FLAGS_F }, \
+ { NAME, INSN3OP_CBBU (MOP,SOP), MINSN3OP_CBBU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBU6, FLAGS_CCF }, \
+ { NAME, INSN3OP_BBS (MOP,SOP), MINSN3OP_BBS, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBS12, FLAGS_F }, \
+ { NAME, INSN3OP_ALC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RALIMMRC, FLAGS_F }, \
+ { NAME, INSN3OP_ABL (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RARBLIMM, FLAGS_F }, \
+ { NAME, INSN3OP_0LC (MOP,SOP), MINSN3OP_0LC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMRC, FLAGS_F }, \
+ { NAME, INSN3OP_0BL (MOP,SOP), MINSN3OP_0BL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZARBLIMM, FLAGS_F }, \
+ { NAME, INSN3OP_C0LC (MOP,SOP), MINSN3OP_C0LC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMRC, FLAGS_CCF }, \
+ { NAME, INSN3OP_CBBL (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBLIMM, FLAGS_CCF }, \
+ { NAME, INSN3OP_ALU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RALIMMU6, FLAGS_F }, \
+ { NAME, INSN3OP_0LU (MOP,SOP), MINSN3OP_0LU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMU6, FLAGS_F }, \
+ { NAME, INSN3OP_C0LU (MOP,SOP), MINSN3OP_C0LU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMU6, FLAGS_CCF }, \
+ { NAME, INSN3OP_0LS (MOP,SOP), MINSN3OP_0LS, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMS12, FLAGS_F }, \
+ { NAME, INSN3OP_ALL (MOP,SOP), MINSN3OP_ALL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RALIMMLIMM, FLAGS_F }, \
+ { NAME, INSN3OP_0LL (MOP,SOP), MINSN3OP_0LL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMLIMM, FLAGS_F }, \
+ { NAME, INSN3OP_C0LL (MOP,SOP), MINSN3OP_C0LL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZALIMMLIMM, FLAGS_CCF },
+
+
+/* Generate sign extend 32-bit immediate instructions. */
+#define INSN3OP_AXC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (60))
+#define INSN3OP_ABX(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (60))
+#define INSN3OP_CBBX(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (60))
+#define INSN3OP_AXU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (60))
+
+/* Macro to generate 3 operand 64bit instruction. */
+#define OP64INSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \
+ { NAME, INSN3OP_ABC (MOP,SOP), MINSN3OP_ABC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RARBRC, FLAGS_F }, \
+ { NAME, INSN3OP_0BC (MOP,SOP), MINSN3OP_0BC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZARBRC, FLAGS_F }, \
+ { NAME, INSN3OP_CBBC (MOP,SOP), MINSN3OP_CBBC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBRC, FLAGS_CCF }, \
+ { NAME, INSN3OP_ABU (MOP,SOP), MINSN3OP_ABU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RARBU6, FLAGS_F }, \
+ { NAME, INSN3OP_0BU (MOP,SOP), MINSN3OP_0BU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_ZARBU6, FLAGS_F }, \
+ { NAME, INSN3OP_CBBU (MOP,SOP), MINSN3OP_CBBU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBU6, FLAGS_CCF }, \
+ { NAME, INSN3OP_BBS (MOP,SOP), MINSN3OP_BBS, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBS12, FLAGS_F }, \
+ { NAME, INSN3OP_AXC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RAXIMMRC, FLAGS_F }, \
+ { NAME, INSN3OP_ABX (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RARBXIMM, FLAGS_F }, \
+ { NAME, INSN3OP_CBBX (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBXIMM, FLAGS_CCF }, \
+ { NAME, INSN3OP_AXU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RAXIMMU6, FLAGS_F }, \
+ { NAME, INSN3OP_ALC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RALIMMRC, FLAGS_F }, \
+ { NAME, INSN3OP_ABL (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RARBLIMM, FLAGS_F }, \
+ { NAME, INSN3OP_CBBL (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RBRBLIMM, FLAGS_CCF }, \
+ { NAME, INSN3OP_ALU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \
+ ARG_32BIT_RALIMMU6, FLAGS_F },
+
+
+#define STDL_ENCODING(K, ZZ) ((F32_ST_OFFSET << 27) | (1 << 5) | (ZZ << 1) \
+ | (K))
+#define MSK_STDL (MASK_32BIT (~(FIELDB (63) | (0x1ff << 15) | FIELDC (63) \
+ | (0x3 << 3))))
+#define STDL_ASYM_ENCODING(K, ZZ, X) ((F32_ST_OFFSET << 27) | FIELDB (X) \
+ | (1 << 5) | (ZZ << 1) | (K))
+#define STDL_DIMM_ENCODING(K, ZZ, X) ((F32_ST_OFFSET << 27) | FIELDC (X) \
+ | (1 << 5) | (ZZ << 1) | (K))
+
+/* stdl<.aa> c,[b,s9]
+ stdl<.aa> w6,[b,s9]
+ stdl<.as> c,[ximm]
+ stdl<.as> w6,[ximm]
+ stdl<.aa> ximm,[b,s9]
+ stdl<.aa> limm,[b,s9]
+*/
+#define STDL \
+ { "stdl", STDL_ENCODING (0, 0x03), MSK_STDL, ARC_OPCODE_ARC64, STORE, \
+ NONE, { RCD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \
+ { "stdl", STDL_ENCODING (1, 0x02), MSK_STDL, ARC_OPCODE_ARC64, STORE, \
+ NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \
+ { "stdl", STDL_ASYM_ENCODING (0, 0x03, 60), 0xFF007027, ARC_OPCODE_ARC64, \
+ STORE, NONE, { RCD, BRAKET, XIMM, BRAKETdup }, {C_AS27 }}, \
+ { "stdl", STDL_ASYM_ENCODING (1, 0x02, 60), 0xFF007027, ARC_OPCODE_ARC64, \
+ STORE, NONE, { W6, BRAKET, XIMM, BRAKETdup }, { C_AS27 }}, \
+ { "stdl", STDL_ASYM_ENCODING (0, 0x03, 62), 0xFF007027, ARC_OPCODE_ARC64, \
+ STORE, NONE, { RCD, BRAKET, LIMM, BRAKETdup }, {C_AS27 }}, \
+ { "stdl", STDL_ASYM_ENCODING (1, 0x02, 62), 0xFF007027, ARC_OPCODE_ARC64, \
+ STORE, NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_AS27 }}, \
+ { "stdl", STDL_DIMM_ENCODING (0, 0x03, 60), 0XF8000FE7, ARC_OPCODE_ARC64, \
+ STORE, NONE, { XIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \
+ { "stdl", STDL_DIMM_ENCODING (0, 0x03, 62), 0xF8000FE7, ARC_OPCODE_ARC64, \
+ STORE, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }},
+
+#define STL_ENCODING(DI) ((F32_ST_OFFSET << 27) | (DI << 5) | (0X03 << 1) \
+ | (1))
+#define MSK_STL (MASK_32BIT (~(FIELDB (63) | (0x1ff << 15) | FIELDC (63) \
+ | (0x03 << 3))))
+#define STL_ASYM_ENCODING(DI, X) ((F32_ST_OFFSET << 27) | (DI << 5) \
+ | (0X03 << 1) | FIELDB (X) | (1))
+#define STL_DSYM_ENCODING(X) ((F32_ST_OFFSET << 27) | (0X03 << 1) \
+ | FIELDC (X) | (1))
+
+/* stl<.aa> c,[b,s9]
+ stl<.aa> w6,[b,s9]
+ stl<.as> c,[ximm]
+ stl<.as> w6,[ximm]
+ stl<.aa> ximm,[b,s9]
+ stl<.aa> limm,[b,s9]
+*/
+#define STL \
+ { "stl", STL_ENCODING (0), MSK_STL, ARC_OPCODE_ARC64, STORE, NONE, \
+ { RC, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \
+ { "stl", STL_ENCODING (1), MSK_STL, ARC_OPCODE_ARC64, STORE, NONE, \
+ { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \
+ { "stl", STL_ASYM_ENCODING (0, 60), 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, \
+ NONE, { RC, BRAKET, XIMM, BRAKETdup }, { C_AS27 }}, \
+ { "stl", STL_ASYM_ENCODING (1, 60), 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, \
+ NONE, { W6, BRAKET, XIMM, BRAKETdup }, { C_AS27 }}, \
+ { "stl", STL_ASYM_ENCODING (0, 62), 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, \
+ NONE, { RC, BRAKET, LIMM, BRAKETdup }, { C_AS27 }}, \
+ { "stl", STL_ASYM_ENCODING (1, 62), 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, \
+ NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_AS27 }}, \
+ { "stl", STL_DSYM_ENCODING (60), 0xF8000FC7, ARC_OPCODE_ARC64, STORE, \
+ NONE, { XIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \
+ { "stl", STL_DSYM_ENCODING (62), 0xF8000FC7, ARC_OPCODE_ARC64, STORE, \
+ NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }},
+
+/* The opcode table.
+
+ The format of the opcode table is:
+
+ NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.
+
+ The table is organised such that, where possible, all instructions with
+ the same mnemonic are together in a block. When the assembler searches
+ for a suitable instruction the entries are checked in table order, so
+ more specific, or specialised cases should appear earlier in the table.
+
+ As an example, consider two instructions 'add a,b,u6' and 'add
+ a,b,limm'. The first takes a 6-bit immediate that is encoded within the
+ 32-bit instruction, while the second takes a 32-bit immediate that is
+ encoded in a follow-on 32-bit, making the total instruction length
+ 64-bits. In this case the u6 variant must appear first in the table, as
+ all u6 immediates could also be encoded using the 'limm' extension,
+ however, we want to use the shorter instruction wherever possible.
+
+ It is possible though to split instructions with the same mnemonic into
+ multiple groups. However, the instructions are still checked in table
+ order, even across groups. The only time that instructions with the
+ same mnemonic should be split into different groups is when different
+ variants of the instruction appear in different architectures, in which
+ case, grouping all instructions from a particular architecture together
+ might be preferable to merging the instruction into the main instruction
+ table.
+
+ An example of this split instruction groups can be found with the 'sync'
+ instruction. The core arc architecture provides a 'sync' instruction,
+ while the nps instruction set extension provides 'sync.rd' and
+ 'sync.wr'. The rd/wr flags are instruction flags, not part of the
+ mnemonic, so we end up with two groups for the sync instruction, the
+ first within the core arc instruction table, and the second within the
+ nps extension instructions. */
+
+const struct arc_opcode arc_opcodes[] =
+{
+
+ /* STL and STDL instructions. */
+ STL
+ STDL
+
+#include "arc64-tbl.h"
+
+ FP_TOP (fhmadd , FMADD , HALF)
+ FP_TOP (fhmsub , FMSUB , HALF)
+ FP_TOP (fhnmadd, FNMADD, HALF)
+ FP_TOP (fhnmsub, FNMSUB, HALF)
+
+ FP_TOP (fsmadd , FMADD , SINGLE)
+ FP_TOP (fsmsub , FMSUB , SINGLE)
+ FP_TOP (fsnmadd, FNMADD, SINGLE)
+ FP_TOP (fsnmsub, FNMSUB, SINGLE)
+
+ FP_TOP (fdmadd , FMADD , DOUBLE)
+ FP_TOP (fdmsub , FMSUB , DOUBLE)
+ FP_TOP (fdnmadd, FNMADD, DOUBLE)
+ FP_TOP (fdnmsub, FNMSUB, DOUBLE)
+
+ /* Vectors. */
+ FP_TOP (vfhmadd , VFMADD , HALF)
+ FP_TOP (vfhmsub , VFMSUB , HALF)
+ FP_TOP (vfhnmadd, VFNMADD, HALF)
+ FP_TOP (vfhnmsub, VFNMSUB, HALF)
+ FP_TOP (vfhmadds , VFMADDS , HALF)
+ FP_TOP (vfhmsubs , VFMSUBS , HALF)
+ FP_TOP (vfhnmadds, VFNMADDS, HALF)
+ FP_TOP (vfhnmsubs, VFNMSUBS, HALF)
+
+ FP_TOP (vfsmadd , VFMADD , SINGLE)
+ FP_TOP (vfsmsub , VFMSUB , SINGLE)
+ FP_TOP (vfsnmadd, VFNMADD, SINGLE)
+ FP_TOP (vfsnmsub, VFNMSUB, SINGLE)
+ FP_TOP (vfsmadds , VFMADDS , SINGLE)
+ FP_TOP (vfsmsubs , VFMSUBS , SINGLE)
+ FP_TOP (vfsnmadds, VFNMADDS, SINGLE)
+ FP_TOP (vfsnmsubs, VFNMSUBS, SINGLE)
+
+ FP_TOP_D (vfdmadd , VFMADD , DOUBLE)
+ FP_TOP_D (vfdmsub , VFMSUB , DOUBLE)
+ FP_TOP_D (vfdnmadd, VFNMADD, DOUBLE)
+ FP_TOP_D (vfdnmsub, VFNMSUB, DOUBLE)
+ FP_TOP_D (vfdmadds , VFMADDS , DOUBLE)
+ FP_TOP_D (vfdmsubs , VFMSUBS , DOUBLE)
+ FP_TOP_D (vfdnmadds, VFNMADDS, DOUBLE)
+ FP_TOP_D (vfdnmsubs, VFNMSUBS, DOUBLE)
+
+ /* 2OPS. */
+ FP_DOP (fhadd , FADD , HALF)
+ FP_DOP (fhsub , FSUB , HALF)
+ FP_DOP (fhmul , FMUL , HALF)
+ FP_DOP (fhdiv , FDIV , HALF)
+ FP_DOP (fhmin , FMIN , HALF)
+ FP_DOP (fhmax , FMAX , HALF)
+ FP_DOP (fhsgnj , FSGNJ , HALF)
+ FP_DOP (fhsgnjn, FSGNJN, HALF)
+ FP_DOP (fhsgnjx, FSGNJX, HALF)
+
+ FP_DOP (fsadd , FADD , SINGLE)
+ FP_DOP (fssub , FSUB , SINGLE)
+ FP_DOP (fsmul , FMUL , SINGLE)
+ FP_DOP (fsdiv , FDIV , SINGLE)
+ FP_DOP (fsmin , FMIN , SINGLE)
+ FP_DOP (fsmax , FMAX , SINGLE)
+ FP_DOP (fssgnj , FSGNJ , SINGLE)
+ FP_DOP (fssgnjn, FSGNJN, SINGLE)
+ FP_DOP (fssgnjx, FSGNJX, SINGLE)
+
+ FP_DOP (fdadd , FADD , DOUBLE)
+ FP_DOP (fdsub , FSUB , DOUBLE)
+ FP_DOP (fdmul , FMUL , DOUBLE)
+ FP_DOP (fddiv , FDIV , DOUBLE)
+ FP_DOP (fdmin , FMIN , DOUBLE)
+ FP_DOP (fdmax , FMAX , DOUBLE)
+ FP_DOP (fdsgnj , FSGNJ , DOUBLE)
+ FP_DOP (fdsgnjn, FSGNJN, DOUBLE)
+ FP_DOP (fdsgnjx, FSGNJX, DOUBLE)
+
+ FP_DOP_C (fhcmp , FCMP , HALF)
+ FP_DOP_C (fhcmpf, FCMPF, HALF)
+ FP_DOP_C (fscmp , FCMP , SINGLE)
+ FP_DOP_C (fscmpf, FCMPF, SINGLE)
+ FP_DOP_C (fdcmp , FCMP , DOUBLE)
+ FP_DOP_C (fdcmpf, FCMPF, DOUBLE)
+
+ /* Vectors. */
+ FP_DOP (vfhadd , VFADD , HALF)
+ FP_DOP (vfhsub , VFSUB , HALF)
+ FP_DOP (vfhmul , VFMUL , HALF)
+ FP_DOP (vfhdiv , VFDIV , HALF)
+ FP_DOP (vfhadds, VFADDS, HALF)
+ FP_DOP (vfhsubs, VFSUBS, HALF)
+ FP_DOP (vfhmuls, VFMULS, HALF)
+ FP_DOP (vfhdivs, VFDIVS, HALF)
+
+ FP_DOP (vfhunpkl , VFUNPKL , HALF)
+ FP_DOP (vfhunpkm , VFUNPKM , HALF)
+ FP_DOP (vfhpackl , VFPACKL , HALF)
+ FP_DOP (vfhpackm , VFPACKM , HALF)
+ FP_DOP (vfhbflyl , VFBFLYL , HALF)
+ FP_DOP (vfhbflym , VFBFLYM , HALF)
+ FP_DOP (vfhaddsub, VFADDSUB, HALF)
+ FP_DOP (vfhsubadd, VFSUBADD, HALF)
+
+ FP_DOP (vfsadd , VFADD , SINGLE)
+ FP_DOP (vfssub , VFSUB , SINGLE)
+ FP_DOP (vfsmul , VFMUL , SINGLE)
+ FP_DOP (vfsdiv , VFDIV , SINGLE)
+ FP_DOP (vfsadds, VFADDS, SINGLE)
+ FP_DOP (vfssubs, VFSUBS, SINGLE)
+ FP_DOP (vfsmuls, VFMULS, SINGLE)
+ FP_DOP (vfsdivs, VFDIVS, SINGLE)
+
+ FP_DOP (vfsunpkl , VFUNPKL , SINGLE)
+ FP_DOP (vfsunpkm , VFUNPKM , SINGLE)
+ FP_DOP (vfspackl , VFPACKL , SINGLE)
+ FP_DOP (vfspackm , VFPACKM , SINGLE)
+ FP_DOP (vfsbflyl , VFBFLYL , SINGLE)
+ FP_DOP (vfsbflym , VFBFLYM , SINGLE)
+ FP_DOP (vfsaddsub, VFADDSUB, SINGLE)
+ FP_DOP (vfssubadd, VFSUBADD, SINGLE)
+
+ FP_DOP_D (vfdadd , VFADD , DOUBLE)
+ FP_DOP_D (vfdsub , VFSUB , DOUBLE)
+ FP_DOP_D (vfdmul , VFMUL , DOUBLE)
+ FP_DOP_D (vfddiv , VFDIV , DOUBLE)
+ FP_DOP_D (vfdadds, VFADDS, DOUBLE)
+ FP_DOP_D (vfdsubs, VFSUBS, DOUBLE)
+ FP_DOP_D (vfdmuls, VFMULS, DOUBLE)
+ FP_DOP_D (vfddivs, VFDIVS, DOUBLE)
+
+ FP_DOP_D (vfdunpkl , VFUNPKL , DOUBLE)
+ FP_DOP_D (vfdunpkm , VFUNPKM , DOUBLE)
+ FP_DOP_D (vfdpackl , VFPACKL , DOUBLE)
+ FP_DOP_D (vfdpackm , VFPACKM , DOUBLE)
+ FP_DOP_D (vfdbflyl , VFBFLYL , DOUBLE)
+ FP_DOP_D (vfdbflym , VFBFLYM , DOUBLE)
+ FP_DOP_D (vfdaddsub, VFADDSUB, DOUBLE)
+ FP_DOP_D (vfdsubadd, VFSUBADD, DOUBLE)
+
+ FP_SOP (fhsqrt, FSQRT, HALF)
+ FP_SOP (fssqrt, FSQRT, SINGLE)
+ FP_SOP (fdsqrt, FSQRT, DOUBLE)
+ FP_SOP (vfhsqrt, VFSQRT, HALF)
+ FP_SOP (vfssqrt, VFSQRT, SINGLE)
+ FP_SOP_D (vfdsqrt, VFSQRT,DOUBLE)
+
+ FP_SOP (vfhexch, VFEXCH, HALF)
+ FP_SOP (vfsexch, VFEXCH, SINGLE)
+ FP_SOP_D (vfdexch, VFEXCH, DOUBLE)
+
+ FP_COP (fhmov, FMOV, HALF)
+ FP_COP (fsmov, FMOV, SINGLE)
+ FP_COP (fdmov, FMOV, DOUBLE)
+ FP_COP (vfhmov, VFMOV, HALF)
+ FP_COP (vfsmov, VFMOV, SINGLE)
+ FP_COP (vfdmov, VFMOV, DOUBLE)
+
+ FP_CVI2F (fuint2s, FUINT2S, 0x00)
+ FP_CVI2F (fuint2d, FUINT2D, 0x00)
+ FP_CVI2F (ful2s, FUL2S, 0x00)
+ FP_CVI2F (ful2d, FUL2D, 0x00)
+
+ FP_CVF2I (fs2uint, FS2UINT, 0x01)
+ FP_CVF2I (fs2ul, FS2UL, 0x01)
+ FP_CVF2I (fd2uint, FD2UINT, 0x01)
+ FP_CVF2I (fd2ul, FD2UL, 0x01)
+
+ FP_CVI2F (fint2s, FINT2S, 0x02)
+ FP_CVI2F (fint2d, FINT2D, 0x02)
+ FP_CVI2F (fl2s, FL2S, 0x02)
+ FP_CVI2F (fl2d, FL2D, 0x02)
+
+ FP_CVF2I (fs2int, FS2INT, 0x03)
+ FP_CVF2I (fs2l, FS2L, 0x03)
+ FP_CVF2I (fd2int, FD2INT, 0x03)
+ FP_CVF2I (fd2l, FD2L, 0x03)
+
+ FP_CVF2F (fs2d, FS2D, 0x04)
+ FP_CVF2F (fd2s, FD2S, 0x04)
+
+ FP_RND (fsrnd, FSRND, 0x06)
+ FP_RND (fdrnd, FDRND, 0x06)
+
+ FP_CVF2I (fs2uint_rz, F2UINT_RZ, 0x09)
+ FP_CVF2I (fs2ul_rz, FS2UL_RZ, 0x09)
+ FP_CVF2I (fd2uint_rz, FD2UINT_RZ, 0x09)
+ FP_CVF2I (fd2ul_rz, FD2UL_RZ, 0x09)
+
+ FP_CVF2I (fs2int_rz, FSINT_RZ, 0x0B)
+ FP_CVF2I (fs2l_rz, FS2L_RZ, 0x0B)
+ FP_CVF2I (fd2int_rz, FD2INT_RZ, 0x0B)
+ FP_CVF2I (fd2l_rz, FD2L_RZ, 0x0B)
+
+ FP_RND (fsrnd_rz, FSRND_RZ, 0x0E)
+ FP_RND (fdrnd_rz, FDRND_RZ, 0x0E)
+
+ FMVI2F (fmvi2s, FMVI2S, 0x10)
+ FMVI2F (fmvl2d, FMVL2D, 0x10)
+
+ FMVF2I (fmvs2i, FMVS2I, 0x11)
+ FMVF2I (fmvd2l, FMVD2L, 0x11)
+
+ FP_CVF2F (fs2h, FS2H, 0x14)
+ FP_CVF2F (fh2s, FH2S, 0x15)
+ FP_CVF2F (fs2h_rz, FS2H_RZ, 0x1C)
+
+ FP_LOAD (fld16, 0x02, 0)
+ FP_LOAD (fld32, 0x00, 0)
+ FP_LOAD (fld64, 0x01, 0)
+ FP_LOAD (fldd32, 0x00, 1)
+ FP_LOAD (fldd64, 0x01, 1)
+
+ FP_STORE (fst16, 0x02, 0)
+ FP_STORE (fst32, 0x00, 0)
+ FP_STORE (fst64, 0x01, 0)
+ FP_STORE (fstd32, 0x00, 1)
+ FP_STORE (fstd64, 0x01, 1)
+
+ FP_EXT (vfhext, HALF)
+ FP_EXT (vfsext, SINGLE)
+ FP_EXT (vfdext, DOUBLE)
+
+ FP_INS (vfhins, HALF)
+ FP_INS (vfsins, SINGLE)
+ FP_INS (vfdins, DOUBLE)
+
+ FP_REP (vfhrep, HALF)
+ FP_REP (vfsrep, SINGLE)
+ FP_REP (vfdrep, DOUBLE)
+
+#undef FLAGS_F
+#define FLAGS_F { 0 }
+
+#undef FLAGS_CCF
+#define FLAGS_CCF { C_CC }
+
+#undef FIELDF
+#define FIELDF 0x0
+
+ EXTINSN3OP ("vmin2", ARC_OPCODE_ARC32, MOVE, NONE, F32_GEN4, 0x11)
+ EXTINSN3OP ("vmax2", ARC_OPCODE_ARC32, MOVE, NONE, F32_GEN4, 0x0b)
+
+#undef HARD_FIELDF
+#define HARD_FIELDF (0x01 << 15)
+
+ EXTINSN3OP ("vmin2", ARC_OPCODE_ARC64, MOVE, NONE, F32_EXT5, 0x38)
+ EXTINSN3OP ("vmax2", ARC_OPCODE_ARC64, MOVE, NONE, F32_EXT5, 0x39)
+
+ EXTINSN3OP ("vpack4hl", ARC_OPCODE_ARC64, MOVE, NONE, F32_GEN_OP64, 0x30)
+ EXTINSN3OP ("vpack4hm", ARC_OPCODE_ARC64, MOVE, NONE, F32_GEN_OP64, 0x31)
+ EXTINSN3OP ("vpack2wl", ARC_OPCODE_ARC64, MOVE, NONE, F32_GEN_OP64, 0x32)
+ EXTINSN3OP ("vpack2wm", ARC_OPCODE_ARC64, MOVE, NONE, F32_GEN_OP64, 0x33)
+ EXTINSN3OP ("vpack2hm", ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE,
+ F32_EXT5, 0x29)
+
+#undef HARD_FIELDF
+#define HARD_FIELDF (0x0)
+
+ OP64INSN3OP ("mpyl", ARC_OPCODE_ARC64, ARITH, NONE, F32_GEN_OP64, 0x30)
+ OP64INSN3OP ("mpyml", ARC_OPCODE_ARC64, ARITH, NONE, F32_GEN_OP64, 0x31)
+ OP64INSN3OP ("mpymul", ARC_OPCODE_ARC64, ARITH, NONE, F32_GEN_OP64, 0x32)
+ OP64INSN3OP ("mpymsul", ARC_OPCODE_ARC64, ARITH, NONE, F32_GEN_OP64, 0x33)
+
+ EXTINSN3OP ("vpack2hl", ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE,
+ F32_EXT5, 0x29)
+
+ { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
+};
--- /dev/null
+/* Opcode table for the ARC.
+ Copyright (C) 1994-2023 Free Software Foundation, Inc.
+
+ Contributed by Claudiu Zissulescu (claziss@synopsys.com)
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "bfd.h"
+#include "opcode/arc.h"
+#include "opintl.h"
+#include "libiberty.h"
+
+/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some
+ custom instructions. All NPS400 features are built into all ARC
+ target builds as this reduces the chances that regressions might
+ creep in. */
+
+/* Insert RA register into a 32-bit opcode, with checks. */
+
+static unsigned long long
+insert_ra_chk (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value == 60)
+ *errmsg = _("LP_COUNT register cannot be used as destination register");
+
+ return insn | (value & 0x3F);
+}
+
+/* Insert RB register into a 32-bit opcode. */
+
+static unsigned long long
+insert_rb (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
+}
+
+/* Insert RB register into a push(d)l/pop(d)l instruction. */
+
+static unsigned long long
+insert_rbb (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x07) << 8) | (((value >> 3) & 0x07) << 1);
+}
+
+/* Insert RB register with checks. */
+
+static unsigned long long
+insert_rb_chk (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value == 60)
+ *errmsg = _("LP_COUNT register cannot be used as destination register");
+
+ return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
+}
+
+/* Insert a floating point register into fs2 slot. */
+
+static unsigned long long
+insert_fs2 (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x03) << 12);
+}
+
+/* Insert address writeback mode for 128-bit loads. */
+
+static unsigned long long
+insert_qq (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x01) << 11) | ((value & 0x02) << (6-1));
+}
+
+static long long
+extract_rb (unsigned long long insn,
+ bool *invalid)
+{
+ int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
+
+ if (value == 0x3e && invalid)
+ *invalid = true; /* A limm operand, it should be extracted in a
+ different way. */
+
+ return value;
+}
+
+static long long
+extract_rbb (unsigned long long insn,
+ bool *invalid)
+{
+ int value = (((insn >> 1) & 0x07) << 3) | ((insn >> 8) & 0x07);
+
+ if (value == 0x3e && invalid)
+ *invalid = true; /* A limm operand, it should be extracted in a
+ different way. */
+
+ return value;
+}
+
+/* Extract the floating point register number from fs2 slot. */
+
+static long long
+extract_fs2 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ long long value;
+ value = (((insn >> 12) & 0x03) << 3) | ((insn >> 24) & 0x07);
+ return value;
+}
+
+/* Extract address writeback mode for 128-bit loads. */
+
+static long long
+extract_qq (unsigned long long insn,
+ bool * invalid ATTRIBUTE_UNUSED)
+{
+ long long value;
+ value = ((insn & 0x800) >> 11) | ((insn & 0x40) >> (6 - 1));
+ return value;
+}
+
+static unsigned long long
+insert_rad (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value & 0x01)
+ *errmsg = _("cannot use odd number destination register");
+ if (value == 60)
+ *errmsg = _("LP_COUNT register cannot be used as destination register");
+
+ return insn | (value & 0x3F);
+}
+
+static unsigned long long
+insert_rcd (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value & 0x01)
+ *errmsg = _("cannot use odd number source register");
+
+ return insn | ((value & 0x3F) << 6);
+}
+
+static unsigned long long
+insert_rbd (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value & 0x01)
+ *errmsg = _("cannot use odd number source register");
+ if (value == 60)
+ *errmsg = _("LP_COUNT register cannot be used as destination register");
+
+ return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
+}
+
+/* Dummy insert ZERO operand function. */
+
+static unsigned long long
+insert_za (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value)
+ *errmsg = _("operand is not zero");
+ return insn;
+}
+
+/* Insert Y-bit in bbit/br instructions. This function is called only
+ when solving fixups. */
+
+static unsigned long long
+insert_Ybit (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value > 0)
+ insn |= 0x08;
+
+ return insn;
+}
+
+/* Insert Y-bit in bbit/br instructions. This function is called only
+ when solving fixups. */
+
+static unsigned long long
+insert_NYbit (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value < 0)
+ insn |= 0x08;
+
+ return insn;
+}
+
+/* Insert H register into a 16-bit opcode. */
+
+static unsigned long long
+insert_rhv1 (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
+}
+
+static long long
+extract_rhv1 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7);
+
+ return value;
+}
+
+/* Insert H register into a 16-bit opcode. */
+
+static unsigned long long
+insert_rhv2 (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value == 0x1E)
+ *errmsg = _("register R30 is a limm indicator");
+ else if (value < 0 || value > 31)
+ *errmsg = _("register out of range");
+ return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
+}
+
+static long long
+extract_rhv2 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
+
+ return value;
+}
+
+static unsigned long long
+insert_r0 (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 0)
+ *errmsg = _("register must be R0");
+ return insn;
+}
+
+static long long
+extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+
+static unsigned long long
+insert_r1 (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 1)
+ *errmsg = _("register must be R1");
+ return insn;
+}
+
+static long long
+extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool* invalid ATTRIBUTE_UNUSED)
+{
+ return 1;
+}
+
+static unsigned long long
+insert_r2 (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 2)
+ *errmsg = _("register must be R2");
+ return insn;
+}
+
+static long long
+extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return 2;
+}
+
+static unsigned long long
+insert_r3 (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 3)
+ *errmsg = _("register must be R3");
+ return insn;
+}
+
+static long long
+extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return 3;
+}
+
+static unsigned long long
+insert_sp (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 28)
+ *errmsg = _("register must be SP");
+ return insn;
+}
+
+static long long
+extract_sp (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return 28;
+}
+
+static unsigned long long
+insert_gp (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 26
+ && value != 30)
+ *errmsg = _("register must be GP");
+ return insn;
+}
+
+static long long
+extract_gp (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return 26;
+}
+
+static unsigned long long
+insert_pcl (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 63)
+ *errmsg = _("register must be PCL");
+ return insn;
+}
+
+static long long
+extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return 63;
+}
+
+static unsigned long long
+insert_blink (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 31)
+ *errmsg = _("register must be BLINK");
+ return insn;
+}
+
+static long long
+extract_blink (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return 31;
+}
+
+static unsigned long long
+insert_ilink1 (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 29)
+ *errmsg = _("register must be ILINK1");
+ return insn;
+}
+
+static long long
+extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return 29;
+}
+
+static unsigned long long
+insert_ilink2 (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 30)
+ *errmsg = _("register must be ILINK2");
+ return insn;
+}
+
+static long long
+extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return 30;
+}
+
+static unsigned long long
+insert_ras (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= (value - 8);
+ break;
+ default:
+ *errmsg = _("register must be either r0-r3 or r12-r15");
+ break;
+ }
+ return insn;
+}
+
+static long long
+extract_ras (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int value = insn & 0x07;
+
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static unsigned long long
+insert_rbs (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 8;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= ((value - 8)) << 8;
+ break;
+ default:
+ *errmsg = _("register must be either r0-r3 or r12-r15");
+ break;
+ }
+ return insn;
+}
+
+static long long
+extract_rbs (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 8) & 0x07;
+
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static unsigned long long
+insert_rcs (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 5;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= ((value - 8)) << 5;
+ break;
+ default:
+ *errmsg = _("register must be either r0-r3 or r12-r15");
+ break;
+ }
+ return insn;
+}
+
+static long long
+extract_rcs (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 5) & 0x07;
+
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static unsigned long long
+insert_simm3s (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ int tmp = 0;
+ switch (value)
+ {
+ case -1:
+ tmp = 0x07;
+ break;
+ case 0:
+ tmp = 0x00;
+ break;
+ case 1:
+ tmp = 0x01;
+ break;
+ case 2:
+ tmp = 0x02;
+ break;
+ case 3:
+ tmp = 0x03;
+ break;
+ case 4:
+ tmp = 0x04;
+ break;
+ case 5:
+ tmp = 0x05;
+ break;
+ case 6:
+ tmp = 0x06;
+ break;
+ default:
+ *errmsg = _("accepted values are from -1 to 6");
+ break;
+ }
+
+ insn |= tmp << 8;
+ return insn;
+}
+
+static long long
+extract_simm3s (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 8) & 0x07;
+
+ if (value == 7)
+ return -1;
+ else
+ return value;
+}
+
+static unsigned long long
+insert_rrange (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ int reg1 = (value >> 16) & 0xFFFF;
+ int reg2 = value & 0xFFFF;
+
+ if (reg1 != 13)
+ *errmsg = _("first register of the range should be r13");
+ else if (reg2 < 13 || reg2 > 26)
+ *errmsg = _("last register of the range doesn't fit");
+ else
+ insn |= ((reg2 - 12) & 0x0F) << 1;
+ return insn;
+}
+
+static long long
+extract_rrange (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return (insn >> 1) & 0x0F;
+}
+
+static unsigned long long
+insert_r13el (unsigned long long insn,
+ long long int value,
+ const char **errmsg)
+{
+ if (value != 13)
+ {
+ *errmsg = _("invalid register number, should be fp");
+ return insn;
+ }
+
+ insn |= 0x02;
+ return insn;
+}
+
+static unsigned long long
+insert_fpel (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 27)
+ {
+ *errmsg = _("invalid register number, should be fp");
+ return insn;
+ }
+
+ insn |= 0x0100;
+ return insn;
+}
+
+static long long
+extract_fpel (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return (insn & 0x0100) ? 27 : -1;
+}
+
+static unsigned long long
+insert_blinkel (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 31)
+ {
+ *errmsg = _("invalid register number, should be blink");
+ return insn;
+ }
+
+ insn |= 0x0200;
+ return insn;
+}
+
+static long long
+extract_blinkel (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return (insn & 0x0200) ? 31 : -1;
+}
+
+static unsigned long long
+insert_pclel (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value != 63)
+ {
+ *errmsg = _("invalid register number, should be pcl");
+ return insn;
+ }
+
+ insn |= 0x0400;
+ return insn;
+}
+
+static long long
+extract_pclel (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return (insn & 0x0400) ? 63 : -1;
+}
+
+#define INSERT_W6
+
+/* mask = 00000000000000000000111111000000
+ insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
+
+static unsigned long long
+insert_w6 (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ insn |= ((value >> 0) & 0x003f) << 6;
+
+ return insn;
+}
+
+#define EXTRACT_W6
+
+/* mask = 00000000000000000000111111000000. */
+
+static long long
+extract_w6 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int value = 0;
+
+ value |= ((insn >> 6) & 0x003f) << 0;
+
+ /* Extend the sign. */
+ int signbit = 1 << 5;
+ value = (value ^ signbit) - signbit;
+
+ return value;
+}
+
+#define INSERT_G_S
+
+/* mask = 0000011100022000
+ insn = 01000ggghhhGG0HH. */
+
+static unsigned long long
+insert_g_s (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ insn |= ((value >> 0) & 0x0007) << 8;
+ insn |= ((value >> 3) & 0x0003) << 3;
+
+ return insn;
+}
+
+#define EXTRACT_G_S
+
+/* mask = 0000011100022000. */
+
+static long long
+extract_g_s (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int value = 0;
+ int signbit = 1 << (6 - 1);
+
+ value |= ((insn >> 8) & 0x0007) << 0;
+ value |= ((insn >> 3) & 0x0003) << 3;
+
+ /* Extend the sign. */
+ value = (value ^ signbit) - signbit;
+
+ return value;
+}
+
+/* ARC NPS400 Support: See comment near head of file. */
+#define MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(NAME,OFFSET) \
+static unsigned long long \
+ insert_nps_3bit_reg_at_##OFFSET##_##NAME \
+ (unsigned long long insn, \
+ long long value, \
+ const char **errmsg) \
+{ \
+ switch (value) \
+ { \
+ case 0: \
+ case 1: \
+ case 2: \
+ case 3: \
+ insn |= value << (OFFSET); \
+ break; \
+ case 12: \
+ case 13: \
+ case 14: \
+ case 15: \
+ insn |= (value - 8) << (OFFSET); \
+ break; \
+ default: \
+ *errmsg = _("register must be either r0-r3 or r12-r15"); \
+ break; \
+ } \
+ return insn; \
+} \
+ \
+static long long \
+extract_nps_3bit_reg_at_##OFFSET##_##NAME \
+ (unsigned long long insn, \
+ bool *invalid ATTRIBUTE_UNUSED) \
+{ \
+ int value = (insn >> (OFFSET)) & 0x07; \
+ if (value > 3) \
+ value += 8; \
+ return value; \
+} \
+
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (dst,8)
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (dst,24)
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (dst,40)
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (dst,56)
+
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (src2,5)
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (src2,21)
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (src2,37)
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (src2,53)
+
+static unsigned long long
+insert_nps_bitop_size_2b (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ switch (value)
+ {
+ case 1:
+ value = 0;
+ break;
+ case 2:
+ value = 1;
+ break;
+ case 4:
+ value = 2;
+ break;
+ case 8:
+ value = 3;
+ break;
+ default:
+ value = 0;
+ *errmsg = _("invalid size, should be 1, 2, 4, or 8");
+ break;
+ }
+
+ insn |= value << 10;
+ return insn;
+}
+
+static long long
+extract_nps_bitop_size_2b (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return 1 << ((insn >> 10) & 0x3);
+}
+
+static unsigned long long
+insert_nps_bitop_uimm8 (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ insn |= ((value >> 5) & 7) << 12;
+ insn |= (value & 0x1f);
+ return insn;
+}
+
+static long long
+extract_nps_bitop_uimm8 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
+}
+
+static unsigned long long
+insert_nps_rflt_uimm6 (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ switch (value)
+ {
+ case 1:
+ case 2:
+ case 4:
+ break;
+
+ default:
+ *errmsg = _("invalid immediate, must be 1, 2, or 4");
+ value = 0;
+ }
+
+ insn |= (value << 6);
+ return insn;
+}
+
+static long long
+extract_nps_rflt_uimm6 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return (insn >> 6) & 0x3f;
+}
+
+static unsigned long long
+insert_nps_dst_pos_and_size (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
+ return insn;
+}
+
+static long long
+extract_nps_dst_pos_and_size (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return (insn & 0x1f);
+}
+
+static unsigned long long
+insert_nps_cmem_uimm16 (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ int top = (value >> 16) & 0xffff;
+
+ if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE)
+ *errmsg = _("invalid value for CMEM ld/st immediate");
+ insn |= (value & 0xffff);
+ return insn;
+}
+
+static long long
+extract_nps_cmem_uimm16 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
+}
+
+static unsigned long long
+insert_nps_imm_offset (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ switch (value)
+ {
+ case 0:
+ case 16:
+ case 32:
+ case 48:
+ case 64:
+ value = value >> 4;
+ break;
+ default:
+ *errmsg = _("invalid position, should be 0, 16, 32, 48 or 64.");
+ value = 0;
+ }
+ insn |= (value << 10);
+ return insn;
+}
+
+static long long
+extract_nps_imm_offset (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 10) & 0x7) * 16;
+}
+
+static unsigned long long
+insert_nps_imm_entry (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ switch (value)
+ {
+ case 16:
+ value = 0;
+ break;
+ case 32:
+ value = 1;
+ break;
+ case 64:
+ value = 2;
+ break;
+ case 128:
+ value = 3;
+ break;
+ default:
+ *errmsg = _("invalid position, should be 16, 32, 64 or 128.");
+ value = 0;
+ }
+ insn |= (value << 2);
+ return insn;
+}
+
+static long long
+extract_nps_imm_entry (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int imm_entry = ((insn >> 2) & 0x7);
+ return (1 << (imm_entry + 4));
+}
+
+static unsigned long long
+insert_nps_size_16bit (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if ((value < 1) || (value > 64))
+ {
+ *errmsg = _("invalid size value must be on range 1-64.");
+ value = 0;
+ }
+ value = value & 0x3f;
+ insn |= (value << 6);
+ return insn;
+}
+
+static long long
+extract_nps_size_16bit (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn & 0xfc0) >> 6) ? ((insn & 0xfc0) >> 6) : 64;
+}
+
+
+#define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
+ static unsigned long long \
+ insert_nps_##NAME##_pos (unsigned long long insn, \
+ long long value, \
+ const char **errmsg) \
+{ \
+ switch (value) \
+ { \
+ case 0: \
+ case 8: \
+ case 16: \
+ case 24: \
+ value = value / 8; \
+ break; \
+ default: \
+ *errmsg = _("invalid position, should be 0, 8, 16, or 24"); \
+ value = 0; \
+ } \
+ insn |= (value << SHIFT); \
+ return insn; \
+} \
+ \
+ static long long \
+ extract_nps_##NAME##_pos (unsigned long long insn, \
+ bool *invalid ATTRIBUTE_UNUSED) \
+ { \
+ return ((insn >> SHIFT) & 0x3) * 8; \
+ }
+
+MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12)
+MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10)
+
+#define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT) \
+static unsigned long long \
+insert_nps_##NAME (unsigned long long insn, \
+ long long value, \
+ const char **errmsg) \
+{ \
+ if (value < LOWER || value > UPPER) \
+ { \
+ *errmsg = _("invalid size, value must be " \
+ #LOWER " to " #UPPER "."); \
+ return insn; \
+ } \
+ value -= BIAS; \
+ insn |= (value << SHIFT); \
+ return insn; \
+} \
+ \
+static long long \
+extract_nps_##NAME (unsigned long long insn, \
+ bool *invalid ATTRIBUTE_UNUSED) \
+{ \
+ return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
+}
+
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0)
+
+static long long
+extract_nps_qcmp_m3 (unsigned long long insn,
+ bool *invalid)
+{
+ int m3 = (insn >> 5) & 0xf;
+ if (m3 == 0xf)
+ *invalid = true;
+ return m3;
+}
+
+static long long
+extract_nps_qcmp_m2 (unsigned long long insn,
+ bool *invalid)
+{
+ bool tmp_invalid = false;
+ int m2 = (insn >> 15) & 0x1;
+ int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
+
+ if (m2 == 0 && m3 == 0xf)
+ *invalid = true;
+ return m2;
+}
+
+static long long
+extract_nps_qcmp_m1 (unsigned long long insn,
+ bool *invalid)
+{
+ bool tmp_invalid = false;
+ int m1 = (insn >> 14) & 0x1;
+ int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid);
+ int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
+
+ if (m1 == 0 && m2 == 0 && m3 == 0xf)
+ *invalid = true;
+ return m1;
+}
+
+static unsigned long long
+insert_nps_calc_entry_size (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ unsigned pwr;
+
+ if (value < 1 || value > 256)
+ {
+ *errmsg = _("value out of range 1 - 256");
+ return 0;
+ }
+
+ for (pwr = 0; (value & 1) == 0; value >>= 1)
+ ++pwr;
+
+ if (value != 1)
+ {
+ *errmsg = _("value must be power of 2");
+ return 0;
+ }
+
+ return insn | (pwr << 8);
+}
+
+static long long
+extract_nps_calc_entry_size (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ unsigned entry_size = (insn >> 8) & 0xf;
+ return 1 << entry_size;
+}
+
+static unsigned long long
+insert_nps_bitop_mod4 (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x2) << 30) | ((value & 0x1) << 47);
+}
+
+static long long
+extract_nps_bitop_mod4 (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 30) & 0x2) | ((insn >> 47) & 0x1);
+}
+
+static unsigned long long
+insert_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
+ long long value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | (value << 42) | (value << 37);
+}
+
+static long long
+extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
+ bool *invalid)
+{
+ if (((insn >> 42) & 0x1f) != ((insn >> 37) & 0x1f))
+ *invalid = true;
+ return ((insn >> 37) & 0x1f);
+}
+
+static unsigned long long
+insert_nps_bitop_ins_ext (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value < 0 || value > 28)
+ *errmsg = _("value must be in the range 0 to 28");
+ return insn | (value << 20);
+}
+
+static long long
+extract_nps_bitop_ins_ext (unsigned long long insn,
+ bool *invalid)
+{
+ int value = (insn >> 20) & 0x1f;
+
+ if (value > 28)
+ *invalid = true;
+ return value;
+}
+
+#define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \
+static unsigned long long \
+insert_nps_##NAME (unsigned long long insn, \
+ long long value, \
+ const char **errmsg) \
+{ \
+ if (value < 1 || value > UPPER) \
+ *errmsg = _("value must be in the range 1 to " #UPPER); \
+ if (value == UPPER) \
+ value = 0; \
+ return insn | (value << SHIFT); \
+} \
+ \
+static long long \
+extract_nps_##NAME (unsigned long long insn, \
+ bool *invalid ATTRIBUTE_UNUSED) \
+{ \
+ int value = (insn >> SHIFT) & ((1 << BITS) - 1); \
+ if (value == 0) \
+ value = UPPER; \
+ return value; \
+}
+
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (proto_size, 16, 64, 6)
+
+static unsigned long long
+insert_nps_min_hofs (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value < 0 || value > 240)
+ *errmsg = _("value must be in the range 0 to 240");
+ if ((value % 16) != 0)
+ *errmsg = _("value must be a multiple of 16");
+ value = value / 16;
+ return insn | (value << 6);
+}
+
+static long long
+extract_nps_min_hofs (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 6) & 0xF;
+ return value * 16;
+}
+
+#define MAKE_INSERT_NPS_ADDRTYPE(NAME, VALUE) \
+ static unsigned long long \
+insert_nps_##NAME (unsigned long long insn, \
+ long long value, \
+ const char **errmsg) \
+{ \
+ if (value != ARC_NPS400_ADDRTYPE_##VALUE) \
+ *errmsg = _("invalid address type for operand"); \
+ return insn; \
+} \
+ \
+static long long \
+extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
+ bool *invalid ATTRIBUTE_UNUSED) \
+{ \
+ return ARC_NPS400_ADDRTYPE_##VALUE; \
+}
+
+MAKE_INSERT_NPS_ADDRTYPE (bd, BD)
+MAKE_INSERT_NPS_ADDRTYPE (jid, JID)
+MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD)
+MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD)
+MAKE_INSERT_NPS_ADDRTYPE (sd, SD)
+MAKE_INSERT_NPS_ADDRTYPE (sm, SM)
+MAKE_INSERT_NPS_ADDRTYPE (xa, XA)
+MAKE_INSERT_NPS_ADDRTYPE (xd, XD)
+MAKE_INSERT_NPS_ADDRTYPE (cd, CD)
+MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD)
+MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID)
+MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD)
+MAKE_INSERT_NPS_ADDRTYPE (cm, CM)
+MAKE_INSERT_NPS_ADDRTYPE (csd, CSD)
+MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA)
+MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD)
+
+static unsigned long long
+insert_nps_rbdouble_64 (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value < 0 || value > 31)
+ *errmsg = _("value must be in the range 0 to 31");
+ return insn | (value << 43) | (value << 48);
+}
+
+
+static long long
+extract_nps_rbdouble_64 (unsigned long long insn,
+ bool *invalid)
+{
+ int value1 = (insn >> 43) & 0x1F;
+ int value2 = (insn >> 48) & 0x1F;
+
+ if (value1 != value2)
+ *invalid = true;
+
+ return value1;
+}
+
+static unsigned long long
+insert_nps_misc_imm_offset (unsigned long long insn,
+ long long value,
+ const char **errmsg)
+{
+ if (value & 0x3)
+ {
+ *errmsg = _("invalid position, should be one of: 0,4,8,...124.");
+ value = 0;
+ }
+ insn |= (value << 6);
+ return insn;
+}
+
+static long long int
+extract_nps_misc_imm_offset (unsigned long long insn,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 8) & 0x1f) * 4;
+}
+
+static long long int
+extract_uimm12_20 (unsigned long long insn ATTRIBUTE_UNUSED,
+ bool *invalid ATTRIBUTE_UNUSED)
+{
+ int value = 0;
+
+ value |= ((insn >> 6) & 0x003f) << 0;
+ value |= ((insn >> 0) & 0x003f) << 6;
+
+ return value;
+}
+
+/* Include the generic extract/insert functions. Order is important
+ as some of the functions present in the .h may be disabled via
+ defines. */
+#include "arc-fxi.h"
+
+/* The flag operands enum. */
+#define FLAG(NAME, NAMESTR, CODE, BITS, SHIFT, FAVAIL) \
+ F_##NAME,
+enum arc_flag_operand_enum {
+ F_INVALID = -1,
+ F_NULL = 0,
+#include "arc-flag.def"
+ F_SIZE,
+};
+#undef FLAG
+
+/* The flag operands name. */
+#define FLAG(NAME, NAMESTR, CODE, BITS, SHIFT, FAVAIL) \
+ "F_" #NAME,
+const char *flag_operand_name[F_SIZE] = {
+ "F_NULL",
+#include "arc-flag.def"
+};
+#undef FLAG
+
+/* The flag operands table.
+
+ The format of the table is
+ NAME CODE BITS SHIFT FAVAIL. */
+#define FLAG(NAME, NAMESTR, CODE, BITS, SHIFT, FAVAIL) \
+ [F_##NAME] = { NAMESTR, CODE, BITS, SHIFT, FAVAIL },
+const struct arc_flag_operand arc_flag_operands[F_SIZE] =
+{
+ [F_NULL] = { 0, 0, 0, 0, 0 },
+ #include "arc-flag.def"
+};
+#undef FLAG
+
+const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
+
+/* Enum of the flag classes. */
+#define FLAG_CLASS(NAME, CLASS, INSERT_FN, EXTRACT_FN, ...) \
+ C_##NAME,
+enum arc_flag_class_enum {
+ C_INVALID = -1,
+ #include "arc-flag-classes.def"
+ C_SIZE
+};
+#undef FLAG_CLASS
+
+/* Table of the flag classes.
+
+ The format of the table is
+ CLASS {FLAG_CODE}. */
+#define FLAG_CLASS(NAME, CLASS, INSERT_FN, EXTRACT_FN, ...) \
+ [C_##NAME] = { \
+ .flag_class = CLASS, \
+ .insert = INSERT_FN, \
+ .extract = EXTRACT_FN, \
+ .flags = { __VA_ARGS__, F_NULL } \
+ },
+const struct arc_flag_class arc_flag_classes[C_SIZE] =
+{
+ #include "arc-flag-classes.def"
+};
+#undef FLAG_CLASS
+
+const unsigned char flags_none[] = { 0 };
+const unsigned char flags_f[] = { C_F };
+const unsigned char flags_cc[] = { C_CC };
+const unsigned char flags_ccf[] = { C_CC, C_F };
+
+/* The operands enum. */
+#define ARC_OPERAND(NAME, BITS, SHIFT, RELO, FLAGS, INSERT_FN, EXTRACT_FN) \
+ NAME,
+enum arc_operand_enum {
+ ARC_OPERAND_INVALID = -1,
+ UNUSED = 0,
+#include "arc-operands.def"
+ ARC_OPERAND_SIZE
+};
+#undef ARC_OPERAND
+
+/* The operands name. */
+#define ARC_OPERAND(NAME, BITS, SHIFT, RELO, FLAGS, INSERT_FN, EXTRACT_FN) \
+ #NAME,
+const char *arc_operand_name[ARC_OPERAND_SIZE] = {
+ "UNUSED",
+#include "arc-operands.def"
+};
+#undef ARC_OPERAND
+/* The operands table.
+
+ The format of the operands table is:
+
+ BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
+#define ARC_OPERAND(NAME, BITS, SHIFT, RELOC, FLAGS, INSERT_FN, EXTRACT_FN) \
+ [NAME] = { \
+ .bits = BITS, \
+ .shift = SHIFT, \
+ .default_reloc = RELOC, \
+ .flags = FLAGS, \
+ .insert = INSERT_FN, \
+ .extract = EXTRACT_FN \
+ },
+const struct arc_operand arc_operands[ARC_OPERAND_SIZE] =
+{
+ /* The fields are bits, shift, insert, extract, flags. The zero
+ index is used to indicate end-of-list. */
+ [UNUSED] = { 0, 0, 0, 0, 0, 0 },
+#include "arc-operands.def"
+};
+#undef ARC_OPERAND
+
+const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
+
+const unsigned arc_Toperand = FKT_T;
+const unsigned arc_NToperand = FKT_NT;
+
+const unsigned char arg_none[] = { 0 };
+const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC };
+const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC };
+const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC };
+const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 };
+const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 };
+const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 };
+const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 };
+const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC };
+const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM };
+const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC };
+const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM };
+
+const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM };
+const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 };
+const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 };
+
+const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 };
+const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup };
+const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup };
+
+const unsigned char arg_32bit_rbrc[] = { RB, RC };
+const unsigned char arg_32bit_zarc[] = { ZA, RC };
+const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 };
+const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 };
+const unsigned char arg_32bit_rblimm[] = { RB, LIMM };
+const unsigned char arg_32bit_zalimm[] = { ZA, LIMM };
+
+const unsigned char arg_32bit_limmrc[] = { LIMM, RC };
+const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 };
+const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 };
+const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup };
+
+const unsigned char arg_32bit_rc[] = { RC };
+const unsigned char arg_32bit_u6[] = { UIMM6_20 };
+const unsigned char arg_32bit_limm[] = { LIMM };
+
+/* List with special cases instructions and the applicable flags. */
+const struct arc_flag_special arc_flag_special_cases[] =
+{
+ { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM,
+ F_NO_T, F_NULL } },
+ { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ,
+ F_NULL } },
+ { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ,
+ F_NULL } },
+ { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ,
+ F_NULL } },
+ { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ,
+ F_NULL } },
+ { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ,
+ F_NULL } },
+ { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ,
+ F_NULL } },
+ { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
+ { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
+};
+
+const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
+
+/* Relocations. */
+const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
+{
+ { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
+ { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
+ { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
+ { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
+
+ /* Next two entries will cover the undefined behavior ldb/stb with
+ address scaling. */
+ { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
+ { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
+
+ { "sda", "ld", { F_ASFAKE, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
+ { "sda", "st", { F_ASFAKE, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
+ { "sda", "ldd", { F_ASFAKE, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
+ { "sda", "std", { F_ASFAKE, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
+
+ /* Short instructions. */
+ { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
+ { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
+ { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
+ { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
+
+ { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
+ { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
+
+ { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
+ BFD_RELOC_ARC_S25H_PCREL_PLT },
+ { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
+ BFD_RELOC_ARC_S21H_PCREL_PLT },
+ { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
+ BFD_RELOC_ARC_S25W_PCREL_PLT },
+ { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
+ BFD_RELOC_ARC_S21W_PCREL_PLT },
+
+ { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
+};
+
+const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
+
+const struct arc_pseudo_insn arc_pseudo_insns[] =
+{
+ { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
+ { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
+ { BRAKETdup, 1, 0, 4} } },
+ { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
+ { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
+ { BRAKETdup, 1, 0, 4} } },
+
+ { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+
+ { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+
+ { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+
+ { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+};
+
+const unsigned arc_num_pseudo_insn =
+ sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
+
+/* ARC64 pseudo instructions. */
+const struct arc_pseudo_insn arc64_pseudo_insns[] =
+{
+ { "pushl", "stl", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
+ { RB, 1, 28, 2 }, { SIMM9_8, 1, -8, 3 },
+ { BRAKETdup, 1, 0, 4} } },
+ { "popl", "ldl", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
+ { RB, 1, 28, 2 }, { SIMM9_8, 1, 8, 3 },
+ { BRAKETdup, 1, 0, 4} } },
+};
+
+const unsigned arc64_num_pseudo_insn =
+ sizeof (arc64_pseudo_insns) / sizeof (*arc64_pseudo_insns);
+
+const struct arc_aux_reg arc_aux_regs[] =
+{
+#undef DEF
+#define DEF(ADDR, CPU, SUBCLASS, NAME) \
+ { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
+
+#include "arc-regs.h"
+
+#undef DEF
+};
+
+const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
+
+/* NOTE: The order of this array MUST be consistent with 'enum
+ arc_rlx_types' located in tc-arc.h! */
+const struct arc_opcode arc_relax_opcodes[] =
+{
+ { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
+
+ /* bl_s s13 11111sssssssssss. */
+ { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
+ { SIMM13_A32_5_S }, { 0 }},
+
+ /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
+ { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
+ { SIMM25_A32_5 }, { C_D }},
+
+ /* b_s s10 1111000sssssssss. */
+ { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
+ { SIMM10_A16_7_S }, { 0 }},
+
+ /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
+ { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
+ { SIMM25_A16_5 }, { C_D }},
+
+ /* add_s c,b,u3 01101bbbccc00uuu. */
+ { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
+
+ /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */
+ { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RA, RB, UIMM6_20R }, { C_F }},
+
+ /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
+ { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RA, RB, LIMM }, { C_F }},
+
+ /* ld_s c,b,u7 10000bbbcccuuuuu. */
+ { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RC_S, BRAKET, RB_S, UIMM7_A32_11R_S, BRAKETdup }, { 0 }},
+
+ /* ld<.di><.aa><.x><zz> a,b,s9
+ 00010bbbssssssssSBBBDaaZZXAAAAAA. */
+ { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RA, BRAKET, RB, SIMM9_8R, BRAKETdup },
+ { C_ZZ23, C_DI20, C_AA21, C_X25 }},
+
+ /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
+ { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RA, BRAKET, RB, LIMM, BRAKETdup },
+ { C_ZZ13, C_DI16, C_AA8, C_X15 }},
+
+ /* mov_s b,u8 11011bbbuuuuuuuu. */
+ { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RB_S, UIMM8_8R_S }, { 0 }},
+
+ /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */
+ { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RB, SIMM12_20R }, { C_F }},
+
+ /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
+ { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RB, LIMM }, { C_F }},
+
+ /* sub_s c,b,u3 01101bbbccc01uuu. */
+ { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
+
+ /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */
+ { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RA, RB, UIMM6_20R }, { C_F }},
+
+ /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
+ { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RA, RB, LIMM }, { C_F }},
+
+ /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */
+ { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
+ | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20R }, { C_F }},
+
+ /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
+ { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
+ | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
+
+ /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */
+ { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RB, UIMM6_20R }, { C_F, C_CC }},
+
+ /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
+ { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RB, LIMM }, { C_F, C_CC }},
+
+ /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */
+ { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RB, RBdup, UIMM6_20R }, { C_F, C_CC }},
+
+ /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
+ { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RB, RBdup, LIMM }, { C_F, C_CC }}
+};
+
+const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
+
+/* Return length of an opcode in bytes. */
+
+int
+arc_opcode_len (const struct arc_opcode *opcode)
+{
+ if (opcode->mask < 0x10000ull)
+ return 2;
+
+ if (opcode->mask < 0x100000000ull)
+ return 4;
+
+ if (opcode->mask < 0x1000000000000ull)
+ return 6;
+
+ return 8;
+}
bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;;
bfd_amdgcn_arch) ;;
bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
+ bfd_arc64_arch) ta="$ta arc-dis.lo arc64-opc.lo arc-ext.lo" ;;
bfd_arm_arch) ta="$ta arm-dis.lo" ;;
bfd_avr_arch) ta="$ta avr-dis.lo" ;;
bfd_bfin_arch) ta="$ta bfin-dis.lo" ;;
bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;;
bfd_amdgcn_arch) ;;
bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
+ bfd_arc64_arch) ta="$ta arc-dis.lo arc64-opc.lo arc-ext.lo" ;;
bfd_arm_arch) ta="$ta arm-dis.lo" ;;
bfd_avr_arch) ta="$ta avr-dis.lo" ;;
bfd_bfin_arch) ta="$ta bfin-dis.lo" ;;
#define ARCH_tilegx
#endif
#define ARCH_arc
+#define ARCH_arc64
#define ARCH_arm
#define ARCH_avr
#define ARCH_bfin
disassemble = arc_get_disassembler (abfd);
break;
#endif
+#ifdef ARCH_arc64
+ case bfd_arch_arc64:
+ disassemble = arc_get_disassembler (abfd);
+ break;
+#endif
#ifdef ARCH_arm
case bfd_arch_arm:
if (big)
projects / binutils-gdb.git / commitdiff