Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 3bc0492b1375ec1e707bfd36bb8e6a1c410c278a..bf641d2fe4907e35c383d2d3441a16940d6a1826 100644 (file)
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -127,18 +127,6 @@ zeroRegisters(CPU *cpu)
     cpu->thread->setFloatReg(ZeroReg, 0.0);
 }
 
-int
-ISA::getInstAsid()
-{
-    return ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
-}
-
-int
-ISA::getDataAsid()
-{
-    return DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
-}
-
 #endif
 
 ////////////////////////////////////////////////////////////////////////

diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index dbd1c43a9decd2691dc4a536d84ecf9d5c01b715..622d1da4cc2ff3c63a3d60c3134f4c68d3a26bbe 100644 (file)
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -65,11 +65,6 @@ namespace AlphaISA
 
       public:
 
-        // These functions should be removed once the simplescalar cpu
-        // model has been replaced.
-        int getInstAsid();
-        int getDataAsid();
-
         MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
         MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
 

diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 7380ad9f9bb84af94fca5195585b6b19adf044b7..252c788a8d7e7295a06b0a02c496af04b5b7ed64 100644 (file)
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -57,16 +57,6 @@ namespace MipsISA
             miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
         }
 
-        int instAsid()
-        {
-            return miscRegFile.getInstAsid();
-        }
-
-        int dataAsid()
-        {
-            return miscRegFile.getDataAsid();
-        }
-
         void clear();
 
         MiscReg readMiscRegNoEffect(int miscReg);

diff --git a/src/arch/mips/mips_core_specific.cc b/src/arch/mips/mips_core_specific.cc
index 80d856b0c3f7e6bc33c0ab652ad555dd63547657..21847378fd01019c468c357aaaf365890394093b 100755 (executable)
--- a/src/arch/mips/mips_core_specific.cc
+++ b/src/arch/mips/mips_core_specific.cc
@@ -109,19 +109,4 @@ MipsISA::processInterrupts(CPU *cpu)
   */
 }
 
-
-/*int
-MipsISA::MiscRegFile::getInstAsid()
-{
-    return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
-}
-
-int
-MipsISA::MiscRegFile::getDataAsid()
-{
-    return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
-    }*/
-
-
-
 #endif // FULL_SYSTEM || BARE_IRON

diff --git a/src/arch/mips/misc_regfile.cc b/src/arch/mips/misc_regfile.cc
index bb4a361f7cb587571aa4d41a49e5e100210a17d8..da35dc66863d494a85b3d3c0f4909685cf659d62 100644 (file)
--- a/src/arch/mips/misc_regfile.cc
+++ b/src/arch/mips/misc_regfile.cc
@@ -167,17 +167,6 @@ MiscRegFile::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
     }
 
 }
-int MiscRegFile::getInstAsid()
-{
-  MiscReg Entry_Hi = readRegNoEffect(EntryHi);
-  return bits(Entry_Hi,EntryHi_ASID_HI,EntryHi_ASID_LO);
-}
-
-int MiscRegFile:: getDataAsid()
-{
-  MiscReg EHi = readRegNoEffect(EntryHi);
-  return bits(EHi,EntryHi_ASID_HI,EntryHi_ASID_LO);
-}
 //@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
 void
 MiscRegFile::reset(std::string core_name, ThreadID num_threads,

diff --git a/src/arch/mips/misc_regfile.hh b/src/arch/mips/misc_regfile.hh
index ab233abdefe4fba26cbeda92517d2b6ec250a197..4983feb88e108c66dc24ce109452397bde201cd7 100644 (file)
--- a/src/arch/mips/misc_regfile.hh
+++ b/src/arch/mips/misc_regfile.hh
@@ -103,9 +103,6 @@ namespace MipsISA
         void setReg(int misc_reg, const MiscReg &val,
                      ThreadContext *tc, ThreadID tid = 0);
 
-        int getInstAsid();
-        int getDataAsid();
-
         //////////////////////////////////////////////////////////
         //
         // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)

diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 1dbfe7a28d9f0274997ceec122366638902d07ca..bba578ef118248c0e198856fd7c7542e573f2a72 100644 (file)
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -45,17 +45,6 @@ namespace SparcISA
         MiscRegFile miscRegFile;
 
       public:
-
-        int instAsid()
-        {
-            return miscRegFile.getInstAsid();
-        }
-
-        int dataAsid()
-        {
-            return miscRegFile.getDataAsid();
-        }
-
         void clear();
 
         MiscReg readMiscRegNoEffect(int miscReg);

diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index c6ba27b9356590085a4d14af0fb3ec3e4b6339a4..36c309db28f4889a67d01a319a1a069959d43582 100644 (file)
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -158,16 +158,6 @@ namespace SparcISA
         void setReg(int miscReg,
                 const MiscReg &val, ThreadContext * tc);
 
-        int getInstAsid()
-        {
-            return priContext | (uint32_t)partId << 13;
-        }
-
-        int getDataAsid()
-        {
-            return priContext | (uint32_t)partId << 13;
-        }
-
         void serialize(EventManager *em, std::ostream & os);
 
         void unserialize(EventManager *em, Checkpoint *cp,

diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 34c803f0cea00b3f31cc4cb39ec3b4933a82c883..5b120d69e1162905c67d0e49c4f03198dad57a41 100644 (file)
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -45,18 +45,6 @@ namespace X86ISA
         MiscRegFile miscRegFile;
 
       public:
-        int instAsid()
-        {
-            //XXX This doesn't make sense in x86
-            return 0;
-        }
-
-        int dataAsid()
-        {
-            //XXX This doesn't make sense in x86
-            return 0;
-        }
-
         void clear();
 
         MiscReg readMiscRegNoEffect(int miscReg);

diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index fda0528ad4c4036b5af9e01290f198ced37efbe8..7dacc58ffef306fbbab4d7e7a59b29862ca4348e 100644 (file)
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -72,8 +72,7 @@ CheckerCPU::CheckerCPU(Params *p)
     systemPtr = NULL;
 #else
     process = p->process;
-    thread = new SimpleThread(this, /* thread_num */ 0, process,
-                              /* asid */ 0);
+    thread = new SimpleThread(this, /* thread_num */ 0, process);
 
     tc = thread->getTC();
     threadContexts.push_back(tc);

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 36de86986f03fa04a7a29e4b7a2fd8bde1d37e0d..a2367db6390f6b87fda1243db3b83d1b807b5e23 100644 (file)
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -207,12 +207,12 @@ InOrderCPU::InOrderCPU(Params *params)
             DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
                     tid, this->thread[tid]);
             this->thread[tid] =
-                new Thread(this, tid, params->workload[tid], tid);
+                new Thread(this, tid, params->workload[tid]);
         } else {
             //Allocate Empty thread so M5 can use later
             //when scheduling threads to CPU
             Process* dummy_proc = params->workload[0];
-            this->thread[tid] = new Thread(this, tid, dummy_proc, tid);
+            this->thread[tid] = new Thread(this, tid, dummy_proc);
         }
 
         // Setup the TC that will serve as the interface to the threads/CPU.

diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 595a38eccf1d5c9547fec94671cc461e9b31263c..75d77c81822fafe6430d63dd5493ea5e9687d4b2 100644 (file)
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -395,14 +395,6 @@ class InOrderCPU : public BaseCPU
         return cpuEventNum++;
     }
 
-    /** Get instruction asid. */
-    int getInstAsid(ThreadID tid)
-    { return thread[tid]->getInstAsid(); }
-
-    /** Get data asid. */
-    int getDataAsid(ThreadID tid)
-    { return thread[tid]->getDataAsid(); }
-
     /** Register file accessors  */
     uint64_t readIntReg(int reg_idx, ThreadID tid);
 

diff --git a/src/cpu/inorder/thread_state.hh b/src/cpu/inorder/thread_state.hh
index 803659487da3d63466a5768213fd34a24d45da72..9b3b39fcb489294550fa0e6b25aa42bc7eef0ffa 100644 (file)
--- a/src/cpu/inorder/thread_state.hh
+++ b/src/cpu/inorder/thread_state.hh
@@ -68,9 +68,9 @@ class InOrderThreadState : public ThreadState {
 
 
     InOrderThreadState(InOrderCPU *_cpu, ThreadID _thread_num,
-                       Process *_process, int _asid)
+                       Process *_process)
         : ThreadState(reinterpret_cast<BaseCPU*>(_cpu), 0/*_thread_num*/,
-                      _process, 0/*_asid*/),
+                      _process),
           cpu(_cpu), inSyscall(0), trapPending(0)
     { }
 

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 394efe16aa91d8cf214980a5d47c68294f011067..6722941e4be692cb4b332bd06695cc69d95eb46c 100644 (file)
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -361,7 +361,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
                     tid, this->thread[tid]);
             this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
                     (typename Impl::O3CPU *)(this),
-                    tid, params->workload[tid], tid);
+                    tid, params->workload[tid]);
 
             //usedTids[tid] = true;
             //threadMap[tid] = tid;
@@ -372,7 +372,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
 
             this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
                     (typename Impl::O3CPU *)(this),
-                    tid, dummy_proc, tid);
+                    tid, dummy_proc);
             //usedTids[tid] = false;
         }
 #endif // !FULL_SYSTEM

diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index c077b2493fa86aa84c911dda1ff54dae946fbf0a..0cc8eab785c2006115c127a2d279033fc6da0adf 100644 (file)
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -392,23 +392,6 @@ class FullO3CPU : public BaseO3CPU
 
     /** Check if this address is a valid data address. */
     bool validDataAddr(Addr addr) { return true; }
-
-    /** Get instruction asid. */
-    int getInstAsid(ThreadID tid)
-    { return isa[tid].instAsid(); }
-
-    /** Get data asid. */
-    int getDataAsid(ThreadID tid)
-    { return isa[tid].dataAsid(); }
-#else
-    /** Get instruction asid. */
-    int getInstAsid(ThreadID tid)
-    { return thread[tid]->getInstAsid(); }
-
-    /** Get data asid. */
-    int getDataAsid(ThreadID tid)
-    { return thread[tid]->getDataAsid(); }
-
 #endif
 
     /** Register accessors.  Index refers to the physical register index. */

diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh
index 1f0e7a3bb8c0d00a5190daba89ddb8dd5ce6bf49..1171053b9316d19f0b6c182660c8984cb29fb30b 100644 (file)
--- a/src/cpu/o3/thread_state.hh
+++ b/src/cpu/o3/thread_state.hh
@@ -95,8 +95,8 @@ struct O3ThreadState : public ThreadState {
         profilePC = 3;
     }
 #else
-    O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process, int _asid)
-        : ThreadState(_cpu, _thread_num, _process, _asid),
+    O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process)
+        : ThreadState(_cpu, _thread_num, _process),
           cpu(_cpu), inSyscall(0), trapPending(0)
     { }
 #endif

diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh
index 53776e7d97d5f5feee26b54c10165f76b225d3dc..971fba88603cb9cd29d30f690b069929f75a0740 100644 (file)
--- a/src/cpu/ozone/thread_state.hh
+++ b/src/cpu/ozone/thread_state.hh
@@ -86,9 +86,8 @@ struct OzoneThreadState : public ThreadState {
         miscRegFile.clear();
     }
 #else
-    OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process,
-                     int _asid)
-        : ThreadState(_cpu, -1, _thread_num, _process, _asid),
+    OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process)
+        : ThreadState(_cpu, -1, _thread_num, _process),
           cpu(_cpu), inSyscall(0), trapPending(0)
     {
         miscRegFile.clear();

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 279fb98b7ea19e3741383306cebe6ac88a87adaf..921c8c19d737cb936e646b9beec7cf341d4efa10 100644 (file)
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -78,7 +78,7 @@ BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
     thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
 #else
     thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
-            p->itb, p->dtb, /* asid */ 0);
+            p->itb, p->dtb);
 #endif // !FULL_SYSTEM
 
     thread->setStatus(ThreadContext::Halted);

diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index dde63d7d98dbec3d79955a8c07312a8026fd8a6f..22bc283a3ede04b7a5425f5b1e5562929f03ad06 100644 (file)
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -92,8 +92,8 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
 }
 #else
 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
-                           TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid)
-    : ThreadState(_cpu, _thread_num, _process, _asid),
+                           TheISA::TLB *_itb, TheISA::TLB *_dtb)
+    : ThreadState(_cpu, _thread_num, _process),
       cpu(_cpu), itb(_itb), dtb(_dtb)
 {
     clearArchRegs();
@@ -106,7 +106,7 @@ SimpleThread::SimpleThread()
 #if FULL_SYSTEM
     : ThreadState(NULL, -1)
 #else
-    : ThreadState(NULL, -1, NULL, -1)
+    : ThreadState(NULL, -1, NULL)
 #endif
 {
     tc = new ProxyThreadContext<SimpleThread>(this);

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 00263d455ab0769d16d009b1a4a15772fcb59ad7..d9d624e77dffdfd92f71443cd2a0ddd75a5bea15 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -145,7 +145,7 @@ class SimpleThread : public ThreadState
                  bool use_kernel_stats = true);
 #else
     SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
-                 TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid);
+                 TheISA::TLB *_itb, TheISA::TLB *_dtb);
 #endif
 
     SimpleThread();
@@ -191,9 +191,6 @@ class SimpleThread : public ThreadState
     }
 
 #if FULL_SYSTEM
-    int getInstAsid() { return isa.instAsid(); }
-    int getDataAsid() { return isa.dataAsid(); }
-
     void dumpFuncProfile();
 
     Fault hwrei();

diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index 53a56d9a68362930720ee00c1d09f6bb58cf9f9e..c62a7a3beba1957f6b9ada599f861b903674dfa4 100644 (file)
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -45,8 +45,7 @@
 #if FULL_SYSTEM
 ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid)
 #else
-ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid,
-                         Process *_process, short _asid)
+ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
 #endif
     : numInst(0), numLoad(0), _status(ThreadContext::Halted),
       baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
@@ -54,7 +53,7 @@ ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid,
       profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
       kernelStats(NULL), physPort(NULL), virtPort(NULL),
 #else
-      port(NULL), process(_process), asid(_asid),
+      port(NULL), process(_process),
 #endif
       funcExeInst(0), storeCondFailures(0)
 {

diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index ba61f431de768bdffce30eea396256788dfde1bd..5c7c0ea56c3e3cdf76c5fc17861e75ff97151dba 100644 (file)
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -68,7 +68,7 @@ struct ThreadState {
 #if FULL_SYSTEM
     ThreadState(BaseCPU *cpu, ThreadID _tid);
 #else
-    ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process, short _asid);
+    ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process);
 #endif
 
     ~ThreadState();
@@ -119,9 +119,6 @@ struct ThreadState {
     TranslatingPort *getMemPort();
 
     void setMemPort(TranslatingPort *_port) { port = _port; }
-
-    int getInstAsid() { return asid; }
-    int getDataAsid() { return asid; }
 #endif
 
     /** Sets the current instruction being committed. */
@@ -205,12 +202,6 @@ struct ThreadState {
     TranslatingPort *port;
 
     Process *process;
-
-    // Address space ID.  Note that this is used for TIMING cache
-    // simulation only; all functional memory accesses should use
-    // one of the FunctionalMemory pointers above.
-    short asid;
-
 #endif
 
     /** Current instruction the thread is committing.  Only set and