* <https://bugs.libre-soc.org/show_bug.cgi?id=568> TODO
* <https://bugs.libre-soc.org/show_bug.cgi?id=927> bug - RT>=32
* <https://bugs.libre-soc.org/show_bug.cgi?id=862> VF Predication
+* <https://bugs.libre-soc.org/show_bug.cgi?id=1222> Rc=1 enhancement needed
* <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vsetvlivsetvl-instructions>
* [[sv/svstep]]
* pseudocode [[openpower/isa/simplev]]