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added lhzsux instruction
authorShriya Sharma <shriya@redsemiconductor.com>
Thu, 19 Oct 2023 10:18:34 +0000 (11:18 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 22 Dec 2023 19:26:21 +0000 (19:26 +0000)
openpower/isa/fixedloadshift.mdwn patch | blob | history

diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn
index 45827e77f6c2324d65f2109df19a9b73674ddc1e..b401e12c76d9d82bc921405bb9a6765f6dd5c07b 100644 (file)
--- a/openpower/isa/fixedloadshift.mdwn
+++ b/openpower/isa/fixedloadshift.mdwn
@@ -67,22 +67,22 @@ X-Form
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (RB) (sm+1)
+    EA <- b + (RB) << (sm+1)
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 
 Special Registers Altered:
 
     None
 
-# Load Halfword and Zero with Update Indexed
+# Load Halfword and Zero Shifted with Update Indexed
 
 X-Form
 
-* lhzux RT,RA,RB
+* lhzsux RT,RA,RB,sm
 
 Pseudo-code:
 
-    EA <- (RA) + (RB)
+    EA <- (RA) + (RB) << (sm+1)
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
     RA <- EA