with pysim.Simulator(frag,
vcd_file=open("ctrl.vcd", "w"),
gtkw_file=open("ctrl.gtkw", "w"),
- gtkw_signals=[ctr.ce, ctr.v, ctr.o]) as sim:
+ traces=[ctr.ce, ctr.v, ctr.o]) as sim:
sim.add_clock(1e-6)
def ce_proc():
yield; yield; yield
class Simulator:
- def __init__(self, fragment, vcd_file=None, gtkw_file=None, gtkw_signals=()):
+ def __init__(self, fragment, vcd_file=None, gtkw_file=None, traces=()):
self._fragment = fragment
self._domains = {} # str/domain -> ClockDomain
self._vcd_writer = None
self._vcd_signals = ValueDict() # signal -> set(vcd_signal)
self._vcd_names = ValueDict() # signal -> str/name
-
self._gtkw_file = gtkw_file
- self._gtkw_signals = gtkw_signals
+ self._traces = traces
def _check_process(self, process):
if inspect.isgeneratorfunction(process):
add_trace(cd.rst)
add_trace(cd.clk)
- for signal in self._gtkw_signals:
+ for signal in self._traces:
add_trace(signal)
if self._vcd_file:
with Simulator(frag,
vcd_file =open("test.vcd", "w"),
gtkw_file=open("test.gtkw", "w"),
- gtkw_signals=[*isigs, osig]) as sim:
+ traces=[*isigs, osig]) as sim:
def process():
for isig, input in zip(isigs, inputs):
yield isig.eq(input)