#MEMORY_SIZE=536870912
#RAM_INIT_FILE=dtbImage.microwatt.hex
#SIM_MAIN_BRAM=false
-#SIM_BRAM_CHAINBOOT=5242880 # 0x500000
+#SIM_BRAM_CHAINBOOT=6291456 # 0x600000
FPGA_TARGET ?= ORANGE-CRAB
# Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
- verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT --trace
+ verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT # --trace
make -C obj_dir -f Vmicrowatt.mk
@cp -f obj_dir/microwatt-verilator microwatt-verilator
mem = _mem;
size_t offs = 0x0; // normal start
if (i == 2) {
- offs = 0x500000; // hard-coded offset of the linux binary
+ offs = 0x600000; // hard-coded offset of the linux binary
}
printf("loading %s at 0x%x size 0x%x\n", bram_file, offs,
statbuf.st_size);