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diff --git a/openpower/sv/rfc/ls002.mdwn b/openpower/sv/rfc/ls002.mdwn
index 03ebf2e6e309d207a87ca49ce80b358574420112..4d1823d66753dd6be8bc3deaee9d70cc8fdb4040 100644 (file)
--- a/openpower/sv/rfc/ls002.mdwn
+++ b/openpower/sv/rfc/ls002.mdwn
@@ -1,48 +1,48 @@
 # RFC ls002 Floating-Point Load-Immediate
 
-Severity: Major
+**Severity**: Major
 
-Status: New
+**Status**: New
 
-Date: 03 Oct 2022
+**Date**: 03 Oct 2022
 
-Target: v3.2
+**Target**: v3.2
 
-Source: v3.0B
+**Source: v3.0B**
 
-Books and Section affected:
+**Books and Section affected**:
 
     Book I Scalar Floating-Point 4.6.2.1
     Appendix D opcode
     Appendix E version
     Appendix F mnemonic
 
-Summary
+**Summary**
 
     Instructions added
     fmvis - Floating-Point Move Immediate, Single
     fishmv - Floating-Point Immediate, Second-half Move
     (Potentially 64-bit prefixed of the same)
 
-Submitter: Luke Leighton (Libre-SOC)
+**Submitter**: Luke Leighton (Libre-SOC)
 
-Requester: Libre-SOC
+**Requester**: Libre-SOC
 
-Impact on processor:
+**Impact on processor**:
 
     Addition of two new FPR-based instructions
     (potentially 4 if EXT001 Prefixed variants added)
 
-Impact on software:
+**Impact on software**:
 
     Requires support for new instructions in assembler, debuggers,
     and related tools.
 
-Keywords:
+**Keywords**:
 
     FPR, Floating-point, Load-immediate, BF16, FP32
 
-Motivation
+**Motivation**
 
 Similar to `lxvkq` but extended to a full BF16 with one
 32-bit instruction and a full FP32 in two 32-bit instructions