sim.pysim: avoid redundant VCD updates.

This commit properly addresses a bug introduced in 2efeb05c and then
temporarily fixed in 58f1d4bc.

Fixes #429.

diff --git a/nmigen/sim/pysim.py b/nmigen/sim/pysim.py
index c3fc1769a6a79ab4508f7caacc159d947bbf80ee..ec98fb0e8b3bf569d14fa0b6b52ed7fd619ab4ea 100644 (file)
--- a/nmigen/sim/pysim.py
+++ b/nmigen/sim/pysim.py
@@ -262,11 +262,13 @@ class _PySimulation(BaseSimulation):
     def wait_interval(self, process, interval):
         self.timeline.delay(interval, process)
 
-    def commit(self):
+    def commit(self, changed=None):
         converged = True
         for signal_state in self.pending:
             if signal_state.commit():
                 converged = False
+        if changed is not None:
+            changed.update(self.pending)
         self.pending.clear()
         return converged
 
@@ -294,6 +296,8 @@ class PySimEngine(BaseEngine):
             process.reset()
 
     def _step(self):
+        changed = set() if self._vcd_writers else None
+
         # Performs the two phases of a delta cycle in a loop:
         converged = False
         while not converged:
@@ -303,13 +307,13 @@ class PySimEngine(BaseEngine):
                     process.runnable = False
                     process.run()
 
-            for vcd_writer in self._vcd_writers:
-                for signal_state in self._state.pending:
-                    vcd_writer.update(self._timeline.now,
-                        signal_state.signal, signal_state.next)
-
             # 2. commit: apply every queued signal change, waking up any waiting processes
-            converged = self._state.commit()
+            converged = self._state.commit(changed)
+
+        for vcd_writer in self._vcd_writers:
+            for signal_state in changed:
+                vcd_writer.update(self._timeline.now,
+                    signal_state.signal, signal_state.curr)
 
     def advance(self):
         self._step()