add bugzilla backlinks

diff --git a/shakti/m_class/AXI.mdwn b/shakti/m_class/AXI.mdwn
index 534538bda8fdfbb51ec4d459280b59c164a7cb60..bb1827f511c182f706cabf224c3d82e662e5ea3b 100644 (file)
--- a/shakti/m_class/AXI.mdwn
+++ b/shakti/m_class/AXI.mdwn
@@ -2,5 +2,5 @@
 
 See also [[wishbone]] Bus
 
-*
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=10>
 * <https://github.com/alexforencich/verilog-axis>

diff --git a/shakti/m_class/RGMII.mdwn b/shakti/m_class/RGMII.mdwn
index 33090026c747ff4de260b60d7edf44aec015d117..e475a7be9bc4d8d415dfb3a6f1f1d68fe18a3484 100644 (file)
--- a/shakti/m_class/RGMII.mdwn
+++ b/shakti/m_class/RGMII.mdwn
@@ -1,4 +1,4 @@
 # RGMII Gigabit Ethernet PHY
 
-* 
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=9>
 * <https://github.com/alexforencich/verilog-ethernet/blob/master/rtl/eth_mac_1g_rgmii.v>

diff --git a/shakti/m_class/wishbone.mdwn b/shakti/m_class/wishbone.mdwn
index 8606bac427776451d230820802984981fee9985d..e623b71fd6ae5218ae574c13dead90a659d8a3af 100644 (file)
--- a/shakti/m_class/wishbone.mdwn
+++ b/shakti/m_class/wishbone.mdwn
@@ -1,6 +1,5 @@
 # Wishbone Bridge
 
 See also [[AXI]] Bus
-
-*
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=11>
 * <https://github.com/alexforencich/verilog-wishbone>