(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 4a6f610602cc611228c4c470a84123f014e6fa22..ef3fac685ea99ee67fd44e76acb99e4cf40d3c8e 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -596,4 +596,14 @@ the destination which can be automatic Store-and-increment.
 
 On top of a barrel-architecture the slowness of Memory access
 was not a problem because the Deterministic nature of classic
-Load-Store-Increment
+Load-Store-Increment can be compensated for by having 8 Memory
+accesses scheduled underway and interleaved in a time-sliced
+fashion with an FPU that is correspondingly 8 times faster than
+Memory accesses.
+
+This design is almost identical to the early Vector Processors
+of the late 1950s and early 1960s. The barrel-archutecture neatly
+solves one of the inherent problems with those designs (memory
+speed) and the presence of a full register file caters for a
+second limitation of pure Memory-based Vector Processors: temporary
+variables needed in the computation of