cpu.createThreads()
cpu.createInterruptController()
- cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
- cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
-
- cpu.mmu.connectWalkerPorts(
- test_sys.ruby._cpu_ports[i].slave,
- test_sys.ruby._cpu_ports[i].slave)
-
- if buildEnv['TARGET_ISA'] in "x86":
- cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
- cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
- cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
+ test_sys.ruby._cpu_ports[i].connectCpuPorts(cpu)
else:
if options.caches or options.l2cache:
system.cpu[i].createInterruptController()
# Connect the cpu's cache ports to Ruby
- system.cpu[i].icache_port = ruby_port.slave
- system.cpu[i].dcache_port = ruby_port.slave
- if buildEnv['TARGET_ISA'] == 'x86':
- system.cpu[i].interrupts[0].pio = ruby_port.master
- system.cpu[i].interrupts[0].int_master = ruby_port.slave
- system.cpu[i].interrupts[0].int_slave = ruby_port.master
- system.cpu[i].mmu.connectWalkerPorts(
- ruby_port.slave, ruby_port.slave)
+ ruby_port.connectCpuPorts(system.cpu[i])
else:
MemClass = Simulation.setMemClass(options)
system.membus = SystemXBar()
# Connect the cpu's cache, interrupt, and TLB ports to Ruby
for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].slave
- cpu.dcache_port = self.sequencers[i].slave
- cpu.mmu.connectWalkerPorts(
- self.sequencers[i].slave, self.sequencers[i].slave)
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].master
- cpu.interrupts[0].int_master = self.sequencers[i].slave
- cpu.interrupts[0].int_slave = self.sequencers[i].master
+ self.sequencers[i].connectCpuPorts(cpu)
class L1Cache(L1Cache_Controller):
# Connect the cpu's cache, interrupt, and TLB ports to Ruby
for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].slave
- cpu.dcache_port = self.sequencers[i].slave
- cpu.mmu.connectWalkerPorts(
- self.sequencers[i].slave, self.sequencers[i].slave)
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].master
- cpu.interrupts[0].int_master = self.sequencers[i].slave
- cpu.interrupts[0].int_slave = self.sequencers[i].master
+ self.sequencers[i].connectCpuPorts(cpu)
class L1Cache(L1Cache_Controller):
# Connect the cpu sequencers and the piobus
if piobus != None:
for cpu_seq in cpu_sequencers:
- cpu_seq.pio_master_port = piobus.slave
- cpu_seq.mem_master_port = piobus.slave
-
- if buildEnv['TARGET_ISA'] == "x86":
- cpu_seq.pio_slave_port = piobus.master
+ cpu_seq.connectIOPorts(piobus)
ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks
ruby._cpu_ports = cpu_sequencers
# create the interrupt controller
cpu.createInterruptController()
# Tie the cpu ports to the correct ruby system ports
- cpu.icache_port = system.ruby._cpu_ports[i].slave
- cpu.dcache_port = system.ruby._cpu_ports[i].slave
- cpu.mmu.connectWalkerPorts(
- system.ruby._cpu_ports[i].slave, system.ruby._cpu_ports[i].slave)
-
- cpu.interrupts[0].pio = system.ruby._cpu_ports[i].master
- cpu.interrupts[0].int_master = system.ruby._cpu_ports[i].slave
- cpu.interrupts[0].int_slave = system.ruby._cpu_ports[i].master
+ system.ruby._cpu_ports[i].connectCpuPorts(cpu)
root = Root(full_system = True, system = system)
m5.ticks.setGlobalFrequency('1THz')