Fix ECP5 cells_sim for iverilog

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 8320ee70a28dc670183d896a21bce85c4dab73bd..1e4002ee0ecf3bcec942957ff7649905854888ee 100644 (file)
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -223,11 +223,12 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
 
        wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
        wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
+       wire srval;
        generate
                if (LSRMODE == "PRLD")
-                       wire srval = M;
+                       assign srval = M;
                else
-                       localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+                       assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
        endgenerate
 
        initial Q = srval;