add fpgaprog programmer

diff --git a/mibuild/xilinx/programmer.py b/mibuild/xilinx/programmer.py
index 50e98b4ab854eaeaf73d4c78c1064bb38cb5c6f8..eb9f5141bfe8574468f71500cb11a94b3e98af8d 100644 (file)
--- a/mibuild/xilinx/programmer.py
+++ b/mibuild/xilinx/programmer.py
@@ -45,6 +45,24 @@ class XC3SProg(GenericProgrammer):
                flash_proxy = self.find_flash_proxy()
                subprocess.call(["xc3sprog", "-v", "-c", self.cable, "-I"+flash_proxy, "{}:w:0x{:x}:BIN".format(data_file, address)])
 
+
+class FpgaProg(GenericProgrammer):
+       needs_bitreverse = False
+
+       def __init__(self, flash_proxy_basename=None):
+               GenericProgrammer.__init__(self, flash_proxy_basename)
+
+       def load_bitstream(self, bitstream_file):
+               subprocess.call(["fpgaprog", "-v", "-f", bitstream_file])
+
+       def flash(self, address, data_file):
+               if address != 0:
+                       raise ValueError("fpga prog needs a main bitstream at address 0")
+               flash_proxy = self.find_flash_proxy()
+               subprocess.call(["fpgaprog", "-v", "-sa", "-r", "-b", flash_proxy,
+                                  "-f", data_file])
+
+
 def _run_vivado(cmds):
        with subprocess.Popen("vivado -mode tcl", stdin=subprocess.PIPE, shell=True) as process:
                process.stdin.write(cmds.encode("ASCII"))