Pay a bit more attention to PEP8

diff --git a/build.py b/build.py
index 0eb19cd89068c8403efc4c687a3ba455e12a16ee..661114f73a09f434267af471c1676fdd5658b46d 100644 (file)
--- a/build.py
+++ b/build.py
@@ -27,7 +27,7 @@ def str2file(filename, contents):
        f.close()
 
 # generate source
-(src_verilog, src_ucf) = top.Get()
+(src_verilog, src_ucf) = top.get()
 str2file("soc.v", src_verilog)
 str2file("soc.ucf", src_ucf)
 verilog_sources.append("build/soc.v")

diff --git a/constraints.py b/constraints.py
index 7d949d3e86aa5a9f69e51d3552c8725634556a8b..12eba657ff196e86c9b598062155f69fa15bb010 100644 (file)
--- a/constraints.py
+++ b/constraints.py
@@ -1,7 +1,7 @@
-def Get(ns, norflash0, uart0):
+def get(ns, norflash0, uart0):
        constraints = []
        def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
-               constraints.append((ns.GetName(signal), vec, pin, iostandard, extra))
+               constraints.append((ns.get_name(signal), vec, pin, iostandard, extra))
        def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
                i = 0
                for p in pins:

diff --git a/milkymist/lm32/__init__.py b/milkymist/lm32/__init__.py
index 3a26c42375f33326e00dea9396460718a8c97345..46157f24283900f82975ae0fcf791c7e8455c054 100644 (file)
--- a/milkymist/lm32/__init__.py
+++ b/milkymist/lm32/__init__.py
@@ -5,8 +5,8 @@ class Inst:
        def __init__(self):
                self.ibus = i = wishbone.Master("lm32i")
                self.dbus = d = wishbone.Master("lm32d")
-               f.Declare(self, "interrupt", f.BV(32))
-               f.Declare(self, "ext_break")
+               f.declare_signal(self, "interrupt", f.BV(32))
+               f.declare_signal(self, "ext_break")
                self._inst = f.Instance("lm32_top",
                        [("I_ADR_O", i.adr_o),
                        ("I_DAT_O", i.dat_o),
@@ -41,7 +41,7 @@ class Inst:
                        "rst_i",
                        "lm32")
 
-       def GetFragment(self):
+       def get_fragment(self):
                comb = [
                        f.Assign(self._inst.ins["I_RTY_I"], 0),
                        f.Assign(self._inst.ins["D_RTY_I"], 0)

diff --git a/milkymist/norflash/__init__.py b/milkymist/norflash/__init__.py
index abec8d82781104c2f4d664a199ed3116029cbfee..5557e2529454b7eb362d29debdb801e74e25beae 100644 (file)
--- a/milkymist/norflash/__init__.py
+++ b/milkymist/norflash/__init__.py
@@ -1,12 +1,13 @@
+from functools import partial
+
 from migen.fhdl import structure as f
 from migen.bus import wishbone
 from migen.corelogic import timeline
-from functools import partial
 
 class Inst:
        def __init__(self, adr_width, rd_timing):
                self.bus = wishbone.Slave("norflash")
-               d = partial(f.Declare, self)
+               d = partial(f.declare_signal, self)
                d("adr", f.BV(adr_width-1))
                d("d", f.BV(16))
                d("oe_n")
@@ -24,8 +25,8 @@ class Inst:
                        (2*rd_timing+1, [
                                f.Assign(self.bus.ack_o, 0)])])
        
-       def GetFragment(self):
+       def get_fragment(self):
                comb = [f.Assign(self.oe_n, 0), f.Assign(self.we_n, 1),
                        f.Assign(self.ce_n, 0), f.Assign(self.rst_n, 1)]
                return f.Fragment(comb, pads={self.adr, self.d, self.oe_n, self.we_n, self.ce_n, self.rst_n}) \
-                       + self.timeline.GetFragment()
+                       + self.timeline.get_fragment()

diff --git a/milkymist/uart/__init__.py b/milkymist/uart/__init__.py
index ed85e95137cbf7ecd6366bc7d266d867c17d609c..87a4e2417c943a1be3db17f88a011387ededc19f 100644 (file)
--- a/milkymist/uart/__init__.py
+++ b/milkymist/uart/__init__.py
@@ -4,10 +4,10 @@ from migen.bus import csr
 class Inst:
        def __init__(self, csr_addr, clk_freq, baud=115200, break_en_default=f.Constant(0)):
                self.bus = csr.Slave("uart")
-               f.Declare(self, "tx")
-               f.Declare(self, "rx")
-               f.Declare(self, "irq")
-               f.Declare(self, "brk")
+               f.declare_signal(self, "tx")
+               f.declare_signal(self, "rx")
+               f.declare_signal(self, "irq")
+               f.declare_signal(self, "brk")
                self._inst = f.Instance("uart",
                        [("csr_do", self.bus.d_o),
                        ("uart_tx", self.tx),
@@ -24,5 +24,5 @@ class Inst:
                        "sys_clk",
                        "sys_rst")
        
-       def GetFragment(self):
+       def get_fragment(self):
                return f.Fragment(instances=[self._inst], pads={self.tx, self.rx})

diff --git a/top.py b/top.py
index 69439a4af2e42b27414f2559a37386a13cd2f654..f91cb75d59856fdbce7581f0c148516db5adfe9c 100644 (file)
--- a/top.py
+++ b/top.py
@@ -1,9 +1,10 @@
 from migen.fhdl import convtools, verilog, autofragment
 from migen.bus import wishbone, csr, wishbone2csr
+
 from milkymist import lm32, norflash, uart
 import constraints
 
-def Get():
+def get():
        cpu0 = lm32.Inst()
        norflash0 = norflash.Inst(25, 12)
        wishbone2csr0 = wishbone2csr.Inst()
@@ -15,8 +16,8 @@ def Get():
        uart0 = uart.Inst(0, 50*1000*1000, baud=115200)
        csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bus])
        
-       frag = autofragment.FromLocal()
+       frag = autofragment.from_local()
        vns = convtools.Namespace()
        src_verilog = verilog.Convert(frag, name="soc", ns=vns)
-       src_ucf = constraints.Get(vns, norflash0, uart0)
+       src_ucf = constraints.get(vns, norflash0, uart0)
        return (src_verilog, src_ucf)