boards/targets: add default rom/ram configuration for arty

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index eb07d1ae5458f2f8df301e606d798f4275453002..35b67026b6df7681326de7226273a0be79635de4 100644 (file)
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -72,7 +72,11 @@ class _CRG(Module):
 class BaseSoC(SoCCore):
     def __init__(self, **kwargs):
         platform = arty.Platform()
-        SoCCore.__init__(self, platform, clk_freq=100*1000000, **kwargs)
+        SoCCore.__init__(self, platform, clk_freq=100*1000000,
+                         integrated_rom_size=0x8000,
+                         integrated_sram_size=0x8000,
+                         integrated_main_ram_size=0x10000,
+                         **kwargs)
 
         self.submodules.crg = _CRG(platform)