(no commit message)

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index cbd3edfe7df25ed711e642a11fa21bc4a1b3a271..9dfc91e3d48c01f731cd6314de3c0975c11d9810 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -19,15 +19,15 @@ results that also, as an aside, produce a corresponding
 CR Field (such as when Rc=1).
 Instructions that involve Rc=1 are definitively arithmetic in nature,
 where the corresponding Condition Register Field can be considered to
-be a "co-result". Thus, if the arithmetic result is Vectorised, so
-is the CR Field "co-result", which puts both firmly out of scope for
+be a "co-result". Such CR Field "co-result" arithmeric operations
+are firmly out of scope for
 this section.
 
-Examples of v3.0B instructions to which this section does
-apply is `mfcr` (3 bit operands) and `crnor` (5 bit operands).
-Examples to which this section does **not** apply include
-`fadds.` and `subf.` which both produce arithmetic results
-(and a CR Field co-result).
+* Examples of v3.0B instructions to which this section does
+  apply is `mfcr` (3 bit operands) and `crnor` (5 bit operands).
+* Examples to which this section does **not** apply include
+  `fadds.` and `subf.` which both produce arithmetic results
+  (and a CR Field co-result).
 
 Other modes are still applicable and include: