More idstring sort_by_* helpers and fixed tpl ordering in techmap

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 3a0f0ff8c7cb79806878c3af13ca52e90a7bbf5c..2c4b26f53a0b2144b7b9dcfa1c6dc59adcc28346 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -255,12 +255,24 @@ namespace RTLIL
                return log_id(str);
        }
 
-       template <typename T> struct sort_by_name {
+       template <typename T> struct sort_by_name_id {
                bool operator()(T *a, T *b) const {
                        return a->name < b->name;
                }
        };
 
+       template <typename T> struct sort_by_name_str {
+               bool operator()(T *a, T *b) const {
+                       return strcmp(a->name.c_str(), b->name.c_str()) < 0;
+               }
+       };
+
+       struct sort_by_id_str {
+               bool operator()(RTLIL::IdString a, RTLIL::IdString b) const {
+                       return strcmp(a.c_str(), b.c_str()) < 0;
+               }
+       };
+
        // see calc.cc for the implementation of this functions
        RTLIL::Const const_not         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
        RTLIL::Const const_and         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);

diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc
index 77821326d2f7dbea497cbab4edaba35f95a95e14..d13643911b9b41629f05b55cc5bd328767f3a61d 100644 (file)
--- a/passes/fsm/fsm_expand.cc
+++ b/passes/fsm/fsm_expand.cc
@@ -30,12 +30,12 @@ struct FsmExpand
        RTLIL::Module *module;
        RTLIL::Cell *fsm_cell;
        SigMap assign_map;
-       SigSet<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> sig2driver, sig2user;
+       SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> sig2driver, sig2user;
        CellTypes ct;
 
-       std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> merged_set;
-       std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> current_set;
-       std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> no_candidate_set;
+       std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> merged_set;
+       std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> current_set;
+       std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> no_candidate_set;
 
        bool already_optimized;
        int limit_transitions;

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index c620531e370001c0c77ef998a11b045ec3570161..d47e4513e5ff9cc88beb0fff686166ae81ab245c 100644 (file)
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -34,7 +34,7 @@ static int count_rm_cells, count_rm_wires;
 static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
 {
        SigMap assign_map(module);
-       std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> queue, unused;
+       std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> queue, unused;
 
        SigSet<RTLIL::Cell*> wire2driver;
        for (auto &it : module->cells_) {
@@ -65,7 +65,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
 
        while (queue.size() > 0)
        {
-               std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> new_queue;
+               std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> new_queue;
                for (auto cell : queue)
                        unused.erase(cell);
                for (auto cell : queue) {

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index a7f91e8628a05749239207ac6198b04f89e11d6d..59173393cb7faf562894afbcabe63e1306532d02 100644 (file)
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -251,7 +251,7 @@ struct TechmapWorker
        }
 
        bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
-                       const std::map<RTLIL::IdString, std::set<RTLIL::IdString>> &celltypeMap, bool in_recursion)
+                       const std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> &celltypeMap, bool in_recursion)
        {
                std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping";
 
@@ -898,7 +898,7 @@ struct TechmapPass : public Pass {
                }
                map->modules_.swap(modules_new);
 
-               std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
+               std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
                for (auto &it : map->modules_) {
                        if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) {
                                char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str());
@@ -960,7 +960,7 @@ struct FlattenPass : public Pass {
                TechmapWorker worker;
                worker.flatten_mode = true;
 
-               std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
+               std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
                for (auto &it : design->modules_)
                        celltypeMap[it.first].insert(it.first);