Added "deminout"

diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index 1b6fb2e6779e83d7ef47cef440f83f165f5be800..96fa0d92a1e552de4f45a5a2435b4a4455e1e4a5 100644 (file)
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -27,6 +27,7 @@ OBJS += passes/techmap/lut2mux.o
 OBJS += passes/techmap/nlutmap.o
 OBJS += passes/techmap/dffsr2dff.o
 OBJS += passes/techmap/shregmap.o
+OBJS += passes/techmap/deminout.o
 endif
 
 GENFILES += passes/techmap/techmap.inc

diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc
new file mode 100644 (file)
index 0000000..ed4e457
--- /dev/null
+++ b/passes/techmap/deminout.cc
@@ -0,0 +1,116 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct DeminoutPass : public Pass {
+       DeminoutPass() : Pass("deminout", "demote inout ports to input or output") { }
+       virtual void help()
+       {
+               log("\n");
+               log("    deminout [options] [selection]\n");
+               log("\n");
+               log("\"Demote\" inout ports to input or output ports, if possible.\n");
+               log("\n");
+       }
+       virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+       {
+               log_header(design, "Executing DEMINOUT pass (demote inout ports to input or output).\n");
+
+               size_t argidx;
+               for (argidx = 1; argidx < args.size(); argidx++)
+               {
+                       // if (args[argidx] == "-bits") {
+                       //      flag_bits = true;
+                       //      continue;
+                       // }
+                       break;
+               }
+               extra_args(args, argidx, design);
+
+               bool keep_running = true;
+
+               while (keep_running)
+               {
+                       keep_running = false;
+
+                       for (auto module : design->selected_modules())
+                       {
+                               SigMap sigmap(module);
+                               pool<SigBit> bits_written, bits_used, bits_inout;
+                               dict<SigBit, int> bits_numports;
+
+                               for (auto wire : module->wires())
+                                       if (wire->port_id)
+                                               for (auto bit : sigmap(wire))
+                                                       bits_numports[bit]++;
+
+                               for (auto cell : module->cells())
+                               for (auto &conn : cell->connections())
+                               {
+                                       bool cellport_out = cell->output(conn.first) || !cell->known();
+                                       bool cellport_in = cell->input(conn.first) || !cell->known();
+
+                                       if (cellport_out && cellport_in)
+                                               for (auto bit : sigmap(conn.second))
+                                                       bits_inout.insert(bit);
+
+                                       if (cellport_out)
+                                               for (auto bit : sigmap(conn.second))
+                                                       bits_written.insert(bit);
+
+                                       if (cellport_in)
+                                               for (auto bit : sigmap(conn.second))
+                                                       bits_used.insert(bit);
+                               }
+
+                               for (auto wire : module->selected_wires())
+                                       if (wire->port_input && wire->port_output)
+                                       {
+                                               bool new_input = false;
+                                               bool new_output = false;
+
+                                               for (auto bit : sigmap(wire))
+                                               {
+                                                       if (bits_numports[bit] > 1 || bits_inout.count(bit))
+                                                               new_input = true, new_output = true;
+
+                                                       if (bits_written.count(bit))
+                                                               new_output = true;
+                                                       else if (bits_used.count(bit))
+                                                               new_input = true;
+                                               }
+
+                                               if (new_input != new_output) {
+                                                       log("Demoting inout port %s.%s to %s.\n", log_id(module), log_id(wire), new_input ? "input" : "output");
+                                                       wire->port_input = new_input;
+                                                       wire->port_output = new_output;
+                                                       keep_running = true;
+                                               }
+                                       }
+                       }
+               }
+       }
+} DeminoutPass;
+
+PRIVATE_NAMESPACE_END

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 0134c13c109b4b98f6b11e2341a3a2729842ab23..38a9cf9d6107db98a9d567ede4a3479d2c1b57d4 100644 (file)
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -169,6 +169,7 @@ struct SynthIce40Pass : public ScriptPass
                        run("proc");
                        run("flatten");
                        run("tribuf -logic");
+                       run("deminout");
                }
 
                if (check_label("coarse"))