---------- Begin Simulation Statistics ----------
sim_seconds 1.982593 # Number of seconds simulated
-sim_ticks 1982593132000 # Number of ticks simulated
-final_tick 1982593132000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 1982592736000 # Number of ticks simulated
+final_tick 1982592736000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1109655 # Simulator instruction rate (inst/s)
-host_op_rate 1109654 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 36063876778 # Simulator tick rate (ticks/s)
-host_mem_usage 333984 # Number of bytes of host memory used
-host_seconds 54.97 # Real time elapsed on the host
-sim_insts 61002651 # Number of instructions simulated
-sim_ops 61002651 # Number of ops (including micro ops) simulated
+host_inst_rate 753764 # Simulator instruction rate (inst/s)
+host_op_rate 753764 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 24497172234 # Simulator tick rate (ticks/s)
+host_mem_usage 320072 # Number of bytes of host memory used
+host_seconds 80.93 # Real time elapsed on the host
+sim_insts 61003209 # Number of instructions simulated
+sim_ops 61003209 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst 800256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24686464 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 59392 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 523264 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 800192 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24686016 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 59328 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 523328 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 26070336 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 800256 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 59392 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 859648 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7739904 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7739904 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 12504 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 385726 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 928 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 8176 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 26069824 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 800192 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 59328 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 859520 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7739392 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7739392 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 12503 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 385719 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 927 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 8177 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 407349 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 120936 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 120936 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 403641 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 12451604 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 29957 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 263929 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total 407341 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 120928 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 120928 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 403609 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 12451380 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 29924 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 263961 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 484 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 13149615 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 403641 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 29957 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 433598 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3903930 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3903930 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3903930 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 403641 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 12451604 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 29957 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 263929 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total 13149359 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 403609 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 29924 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 433533 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3903672 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3903672 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3903672 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 403609 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 12451380 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 29924 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 263961 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 484 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 17053544 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 407349 # Number of read requests accepted
-system.physmem.writeReqs 120936 # Number of write requests accepted
-system.physmem.readBursts 407349 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 120936 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 26062656 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7738112 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 26070336 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7739904 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total 17053031 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 407341 # Number of read requests accepted
+system.physmem.writeReqs 120928 # Number of write requests accepted
+system.physmem.readBursts 407341 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 120928 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 26061824 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7737600 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 26069824 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7739392 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 25226 # Per bank write bursts
system.physmem.perBankRdBursts::1 25379 # Per bank write bursts
-system.physmem.perBankRdBursts::2 25428 # Per bank write bursts
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system.physmem.perBankRdBursts::3 24855 # Per bank write bursts
system.physmem.perBankRdBursts::4 25157 # Per bank write bursts
system.physmem.perBankRdBursts::5 25423 # Per bank write bursts
-system.physmem.perBankRdBursts::6 25496 # Per bank write bursts
-system.physmem.perBankRdBursts::7 25345 # Per bank write bursts
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system.physmem.perBankRdBursts::8 25239 # Per bank write bursts
system.physmem.perBankRdBursts::9 25589 # Per bank write bursts
system.physmem.perBankRdBursts::10 25733 # Per bank write bursts
-system.physmem.perBankRdBursts::11 25919 # Per bank write bursts
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system.physmem.perBankRdBursts::12 25947 # Per bank write bursts
system.physmem.perBankRdBursts::13 25572 # Per bank write bursts
system.physmem.perBankRdBursts::14 25277 # Per bank write bursts
system.physmem.perBankWrBursts::3 6886 # Per bank write bursts
system.physmem.perBankWrBursts::4 7104 # Per bank write bursts
system.physmem.perBankWrBursts::5 7345 # Per bank write bursts
-system.physmem.perBankWrBursts::6 7430 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7161 # Per bank write bursts
system.physmem.perBankWrBursts::9 7315 # Per bank write bursts
system.physmem.perBankWrBursts::10 7729 # Per bank write bursts
-system.physmem.perBankWrBursts::11 8152 # Per bank write bursts
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system.physmem.perBankWrBursts::12 8256 # Per bank write bursts
system.physmem.perBankWrBursts::13 7924 # Per bank write bursts
system.physmem.perBankWrBursts::14 7541 # Per bank write bursts
system.physmem.perBankWrBursts::15 7815 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
-system.physmem.totGap 1982585764500 # Total gap between requests
+system.physmem.numWrRetry 9 # Number of times write queue was full causing retry
+system.physmem.totGap 1982585344500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 407349 # Read request sizes (log2)
+system.physmem.readPktSize::6 407341 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 120936 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 407149 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 67582 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 500.144536 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 302.732498 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 404.890859 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 16271 24.08% 24.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 12393 18.34% 42.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 5170 7.65% 50.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3294 4.87% 54.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2518 3.73% 58.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 4277 6.33% 64.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1487 2.20% 67.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 2102 3.11% 70.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 20070 29.70% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 67582 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5413 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 75.229078 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 2867.379606 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191 5410 99.94% 99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 67562 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 500.272698 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 302.933598 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 404.928891 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 16219 24.01% 24.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 12429 18.40% 42.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 5206 7.71% 50.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3267 4.84% 54.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2499 3.70% 58.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 4251 6.29% 64.93% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::896-1023 2122 3.14% 70.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 20064 29.70% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 67562 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5401 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 75.393816 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 2870.561720 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191 5398 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5413 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5413 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 22.336597 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::stdev 20.176387 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::24-31 29 0.54% 89.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39 21 0.39% 89.75% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::72-79 26 0.48% 95.53% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::88-95 5 0.09% 99.11% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::168-175 8 0.15% 99.67% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::total 5413 # Writes before turning the bus around for reads
-system.physmem.totQLat 2790032750 # Total ticks spent queuing
-system.physmem.totMemAccLat 10425576500 # Total ticks spent from burst creation until serviced by the DRAM
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-system.physmem.avgQLat 6851.26 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 5401 # Reads before turning the bus around for writes
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+system.physmem.wrPerTurnAround::total 5401 # Writes before turning the bus around for reads
+system.physmem.totQLat 2785960750 # Total ticks spent queuing
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 25601.26 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 25591.48 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 13.15 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.90 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 13.15 # Average system read bandwidth in MiByte/s
system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing
-system.physmem.readRowHits 363813 # Number of row buffer hits during reads
-system.physmem.writeRowHits 96742 # Number of row buffer hits during writes
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+system.physmem.writeRowHits 96765 # Number of row buffer hits during writes
system.physmem.readRowHitRate 89.34 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 79.99 # Row buffer hit rate for writes
-system.physmem.avgGap 3752871.58 # Average gap between requests
+system.physmem.writeRowHitRate 80.02 # Row buffer hit rate for writes
+system.physmem.avgGap 3752984.45 # Average gap between requests
system.physmem.pageHitRate 87.20 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 244006560 # Energy for activate commands per rank (pJ)
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system.physmem_0.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ)
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-system.physmem_0.totalEnergy 1330342003950 # Total energy per rank (pJ)
-system.physmem_0.averagePower 671.012251 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::REF 66203020000 # Time in different power states
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-system.physmem_1.actEnergy 266913360 # Energy for activate commands per rank (pJ)
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-system.physmem_1.totalEnergy 1330526848980 # Total energy per rank (pJ)
-system.physmem_1.averagePower 671.105490 # Core power per rank (mW)
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system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dtb.fetch_hits 0 # ITB hits
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system.cpu0.dtb.fetch_accesses 0 # ITB accesses
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system.cpu0.dtb.read_misses 7442 # DTB read misses
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system.cpu0.dtb.read_accesses 490672 # DTB read accesses
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+system.cpu0.dtb.write_hits 5004426 # DTB write hits
system.cpu0.dtb.write_misses 812 # DTB write misses
system.cpu0.dtb.write_acv 134 # DTB write access violations
system.cpu0.dtb.write_accesses 187451 # DTB write accesses
-system.cpu0.dtb.data_hits 12420998 # DTB hits
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system.cpu0.dtb.data_misses 8254 # DTB misses
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-system.cpu0.itb.fetch_hits 3482402 # ITB hits
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system.cpu0.itb.fetch_misses 3871 # ITB misses
system.cpu0.itb.fetch_acv 184 # ITB acv
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system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 3964851877 # number of cpu cycles simulated
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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system.cpu0.kern.ipl_count::0 55926 40.12% 40.12% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 133 0.10% 40.21% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1977 1.42% 41.63% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 435 0.31% 41.94% # number of times we switched to this ipl
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system.cpu0.kern.ipl_good::0 55417 49.07% 49.07% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 133 0.12% 49.18% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1977 1.75% 50.93% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 435 0.39% 51.32% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 54983 48.68% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 112945 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1904793300500 96.08% 96.08% # number of cycles we spent at this ipl
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system.cpu0.kern.ipl_ticks::30 326474000 0.02% 96.15% # number of cycles we spent at this ipl
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system.cpu0.kern.ipl_used::0 0.990899 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
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system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
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system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed
system.cpu0.kern.callpal::rti 4325 2.93% 99.65% # number of callpals executed
system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 147602 # number of callpals executed
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system.cpu0.kern.mode_switch::kernel 6863 # number of protection mode switches
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-system.cpu0.kern.mode_good::kernel 1282
-system.cpu0.kern.mode_good::user 1282
+system.cpu0.kern.mode_good::kernel 1283
+system.cpu0.kern.mode_good::user 1283
system.cpu0.kern.mode_good::idle 0
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system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
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system.cpu0.kern.swap_context 3025 # number of times the context was actually changed
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system.cpu0.num_fp_alu_accesses 206939 # Number of float alu accesses
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-system.cpu0.num_conditional_control_insts 5565345 # number of instructions that are conditional controls
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system.cpu0.num_fp_register_reads 100516 # number of times the floating registers were read
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-system.cpu0.not_idle_fraction 0.066811 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.933189 # Percentage of idle cycles
-system.cpu0.Branches 7133641 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 2703037 5.71% 5.71% # Class of executed instruction
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+system.cpu0.not_idle_fraction 0.066808 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.933192 # Percentage of idle cycles
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+system.cpu0.op_class::No_OpClass 2703031 5.71% 5.71% # Class of executed instruction
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system.cpu0.op_class::IntDiv 0 0.00% 71.70% # Class of executed instruction
system.cpu0.op_class::FloatAdd 25566 0.05% 71.75% # Class of executed instruction
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system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 2511145 # DTB read hits
+system.cpu1.dtb.read_hits 2511191 # DTB read hits
system.cpu1.dtb.read_misses 2993 # DTB read misses
system.cpu1.dtb.read_acv 0 # DTB read access violations
system.cpu1.dtb.read_accesses 239364 # DTB read accesses
-system.cpu1.dtb.write_hits 1829996 # DTB write hits
+system.cpu1.dtb.write_hits 1830032 # DTB write hits
system.cpu1.dtb.write_misses 342 # DTB write misses
system.cpu1.dtb.write_acv 29 # DTB write access violations
system.cpu1.dtb.write_accesses 105248 # DTB write accesses
-system.cpu1.dtb.data_hits 4341141 # DTB hits
+system.cpu1.dtb.data_hits 4341223 # DTB hits
system.cpu1.dtb.data_misses 3335 # DTB misses
system.cpu1.dtb.data_acv 29 # DTB access violations
system.cpu1.dtb.data_accesses 344612 # DTB accesses
-system.cpu1.itb.fetch_hits 1990273 # ITB hits
+system.cpu1.itb.fetch_hits 1990291 # ITB hits
system.cpu1.itb.fetch_misses 1216 # ITB misses
system.cpu1.itb.fetch_acv 0 # ITB acv
-system.cpu1.itb.fetch_accesses 1991489 # ITB accesses
+system.cpu1.itb.fetch_accesses 1991507 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 3965186264 # number of cpu cycles simulated
+system.cpu1.numCycles 3965185472 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2869 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 81047 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 27546 38.52% 38.52% # number of times we switched to this ipl
+system.cpu1.kern.inst.hwrei 81049 # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0 27547 38.53% 38.53% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1971 2.76% 41.28% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30 524 0.73% 42.01% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 41461 57.99% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 71502 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 26678 48.22% 48.22% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_count::31 41462 57.99% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 71504 # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0 26679 48.22% 48.22% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22 1971 3.56% 51.78% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30 524 0.95% 52.73% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 26154 47.27% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 55327 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1912240588500 96.45% 96.45% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 731240000 0.04% 96.49% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_good::31 26155 47.27% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 55329 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1912239584500 96.45% 96.45% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 731206500 0.04% 96.49% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 374509500 0.02% 96.51% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 69246057000 3.49% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1982592395000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.968489 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_ticks::31 69246698500 3.49% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1982591999000 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.968490 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.630810 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.773783 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31 0.630819 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total 0.773789 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
system.cpu1.kern.callpal::swpctx 2066 2.79% 3.39% # number of callpals executed
system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed
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+system.cpu1.kern.callpal::swpipl 65182 88.12% 91.52% # number of callpals executed
system.cpu1.kern.callpal::rdps 2261 3.06% 94.57% # number of callpals executed
system.cpu1.kern.callpal::wrkgp 1 0.00% 94.57% # number of callpals executed
system.cpu1.kern.callpal::wrusp 4 0.01% 94.58% # number of callpals executed
system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed
system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 73970 # number of callpals executed
+system.cpu1.kern.callpal::total 73972 # number of callpals executed
system.cpu1.kern.mode_switch::kernel 2115 # number of protection mode switches
system.cpu1.kern.mode_switch::user 464 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 2921 # number of protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle 0.153372 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 0.331636 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 19470103000 0.98% 0.98% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 1729907500 0.09% 1.07% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1961392382500 98.93% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::kernel 19469811000 0.98% 0.98% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user 1729387000 0.09% 1.07% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle 1961392799000 98.93% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 2067 # number of times the context was actually changed
-system.cpu1.committedInsts 13686479 # Number of instructions committed
-system.cpu1.committedOps 13686479 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 12624111 # Number of integer alu accesses
+system.cpu1.committedInsts 13686745 # Number of instructions committed
+system.cpu1.committedOps 13686745 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 12624358 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 178612 # Number of float alu accesses
-system.cpu1.num_func_calls 430158 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 1359705 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 12624111 # number of integer instructions
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+system.cpu1.num_int_insts 12624358 # number of integer instructions
system.cpu1.num_fp_insts 178612 # number of float instructions
-system.cpu1.num_int_register_reads 17383206 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 9260208 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 17383561 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 9260404 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 93246 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 95234 # number of times the floating registers were written
-system.cpu1.num_mem_refs 4365297 # number of memory refs
-system.cpu1.num_load_insts 2525800 # Number of load instructions
-system.cpu1.num_store_insts 1839497 # Number of store instructions
-system.cpu1.num_idle_cycles 3912233484.998027 # Number of idle cycles
-system.cpu1.num_busy_cycles 52952779.001973 # Number of busy cycles
+system.cpu1.num_mem_refs 4365379 # number of memory refs
+system.cpu1.num_load_insts 2525846 # Number of load instructions
+system.cpu1.num_store_insts 1839533 # Number of store instructions
+system.cpu1.num_idle_cycles 3912234287.998026 # Number of idle cycles
+system.cpu1.num_busy_cycles 52951184.001973 # Number of busy cycles
system.cpu1.not_idle_fraction 0.013354 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.986646 # Percentage of idle cycles
-system.cpu1.Branches 1950120 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 733810 5.36% 5.36% # Class of executed instruction
-system.cpu1.op_class::IntAlu 8101284 59.18% 64.54% # Class of executed instruction
-system.cpu1.op_class::IntMult 23184 0.17% 64.71% # Class of executed instruction
+system.cpu1.Branches 1950147 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 733822 5.36% 5.36% # Class of executed instruction
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system.cpu1.op_class::IntDiv 0 0.00% 64.71% # Class of executed instruction
system.cpu1.op_class::FloatAdd 14372 0.10% 64.81% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 64.81% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 64.83% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.83% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.83% # Class of executed instruction
-system.cpu1.op_class::MemRead 2600475 19.00% 83.82% # Class of executed instruction
-system.cpu1.op_class::MemWrite 1840521 13.44% 97.27% # Class of executed instruction
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+system.cpu1.op_class::IprAccess 374219 2.73% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 13689843 # Class of executed instruction
-system.cpu1.dcache.tags.replacements 173686 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 481.983606 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 4164884 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 174198 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 23.908908 # Average number of references to valid blocks.
+system.cpu1.op_class::total 13690109 # Class of executed instruction
+system.cpu1.dcache.tags.replacements 173692 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 481.984896 # Cycle average of tags in use
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+system.cpu1.dcache.tags.sampled_refs 174204 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 23.908550 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 90321767000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.983606 # Average occupied blocks per requestor
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system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu1.dcache.tags.data_accesses 17608316 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 2339523 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 2339523 # number of ReadReq hits
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-system.cpu1.dcache.LoadLockedReq_misses::total 9256 # number of LoadLockedReq misses
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-system.cpu1.dcache.overall_misses::total 189074 # number of overall misses
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+system.cpu1.dcache.StoreCondReq_accesses::total 59189 # number of StoreCondReq accesses(hits+misses)
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+system.cpu1.dcache.demand_accesses::total 4235852 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 4235852 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 4235852 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050137 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.050137 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036996 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.036996 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155072 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155072 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103212 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103212 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044637 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.044637 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044637 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.044637 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12600.433251 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12600.433251 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28523.151748 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 28523.151748 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9191.335350 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9191.335350 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15870.928139 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15870.928139 # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18123.959402 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 18123.959402 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18123.959402 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 18123.959402 # average overall miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12596.760088 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12596.760088 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28534.679657 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 28534.679657 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9167.477039 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9167.477039 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15872.565068 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15872.565068 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18125.218826 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 18125.218826 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18125.218826 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 18125.218826 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 119736 # number of writebacks
-system.cpu1.dcache.writebacks::total 119736 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123485 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 123485 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65589 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 65589 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9256 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9256 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.writebacks::writebacks 119726 # number of writebacks
+system.cpu1.dcache.writebacks::total 119726 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123491 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 123491 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65586 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 65586 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9255 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9255 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6109 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 6109 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 189074 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 189074 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 189074 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 189074 # number of overall MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 189077 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 189077 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 189077 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 189077 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 118 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3348 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3348 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3466 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3466 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1432479500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1432479500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1805216000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1805216000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 75819000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 75819000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 90846500 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 90846500 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3237695500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 3237695500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3237695500 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 3237695500 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1432095500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1432095500 # number of ReadReq MSHR miss cycles
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+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1805889500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 75590000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 75590000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 90856500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 90856500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3237985000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 3237985000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3237985000 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 3237985000 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 25051000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 25051000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 789482000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 789482000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 814533000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 814533000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050136 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050136 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036998 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036998 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155091 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155091 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103215 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103215 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 789482500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 789482500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 814533500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 814533500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050137 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050137 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036996 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036996 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155072 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155072 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103212 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103212 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044637 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.044637 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044637 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.044637 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11600.433251 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11600.433251 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27523.151748 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27523.151748 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8191.335350 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8191.335350 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14870.928139 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14870.928139 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17123.959402 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17123.959402 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17123.959402 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17123.959402 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11596.760088 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11596.760088 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27534.679657 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27534.679657 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8167.477039 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8167.477039 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14872.565068 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14872.565068 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17125.218826 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17125.218826 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17125.218826 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17125.218826 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 212296.610169 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212296.610169 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.048984 # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.048984 # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235006.635892 # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235006.635892 # average overall mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.198327 # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.198327 # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235006.780150 # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235006.780150 # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements 331505 # number of replacements
-system.cpu1.icache.tags.tagsinuse 442.932847 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 13357787 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 332017 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 40.232238 # Average number of references to valid blocks.
+system.cpu1.icache.tags.replacements 331529 # number of replacements
+system.cpu1.icache.tags.tagsinuse 442.932822 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 13358029 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 332041 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 40.230059 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 1975288394500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.932847 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.932822 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865103 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.865103 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 405 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 403 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 14021901 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 14021901 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 13357787 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 13357787 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 13357787 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 13357787 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 13357787 # number of overall hits
-system.cpu1.icache.overall_hits::total 13357787 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 332057 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 332057 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 332057 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 332057 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 332057 # number of overall misses
-system.cpu1.icache.overall_misses::total 332057 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4541544500 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 4541544500 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 4541544500 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 4541544500 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 4541544500 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 4541544500 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 13689844 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 13689844 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 13689844 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 13689844 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 13689844 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 13689844 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024256 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.024256 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024256 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.024256 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024256 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.024256 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13677.002744 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13677.002744 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13677.002744 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13677.002744 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13677.002744 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13677.002744 # average overall miss latency
+system.cpu1.icache.tags.tag_accesses 14022191 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 14022191 # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst 13358029 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 13358029 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 13358029 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 13358029 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 13358029 # number of overall hits
+system.cpu1.icache.overall_hits::total 13358029 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 332081 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 332081 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 332081 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 332081 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 332081 # number of overall misses
+system.cpu1.icache.overall_misses::total 332081 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4540351000 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 4540351000 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 4540351000 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 4540351000 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 4540351000 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 4540351000 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 13690110 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 13690110 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 13690110 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 13690110 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 13690110 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 13690110 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024257 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.024257 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024257 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.024257 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024257 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.024257 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13672.420283 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13672.420283 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13672.420283 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13672.420283 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13672.420283 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13672.420283 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks 331505 # number of writebacks
-system.cpu1.icache.writebacks::total 331505 # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 332057 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 332057 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 332057 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 332057 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 332057 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 332057 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4209487500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 4209487500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4209487500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 4209487500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4209487500 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 4209487500 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024256 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024256 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024256 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.024256 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024256 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.024256 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12677.002744 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12677.002744 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12677.002744 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 12677.002744 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12677.002744 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 12677.002744 # average overall mshr miss latency
+system.cpu1.icache.writebacks::writebacks 331529 # number of writebacks
+system.cpu1.icache.writebacks::total 331529 # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 332081 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 332081 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 332081 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 332081 # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 332081 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total 332081 # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4208270000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 4208270000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4208270000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 4208270000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4208270000 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 4208270000 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024257 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.024257 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.024257 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12672.420283 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq 7379 # Transaction distribution
-system.iobus.trans_dist::ReadResp 7379 # Transaction distribution
-system.iobus.trans_dist::WriteReq 55684 # Transaction distribution
-system.iobus.trans_dist::WriteResp 55684 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14066 # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq 7376 # Transaction distribution
+system.iobus.trans_dist::ReadResp 7376 # Transaction distribution
+system.iobus.trans_dist::WriteReq 55683 # Transaction distribution
+system.iobus.trans_dist::WriteResp 55683 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14050 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 188 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18150 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 42672 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 42664 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 126126 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56264 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 126118 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56200 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 171 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9075 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 82507 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 82454 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2744131 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 15127500 # Layer occupancy (ticks)
+system.iobus.pkt_size::total 2744078 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 15116500 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 758000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer22.occupancy 175000 # Layer occupancy (ticks)
+system.iobus.reqLayer22.occupancy 183000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 15843000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 15844000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 2460000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 6055000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 6055500 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 83000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 215669663 # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy 215674412 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 28540000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 28533000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 41695 # number of replacements
-system.iocache.tags.tagsinuse 0.566874 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 0.566860 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 1775103309000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide 0.566874 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide 0.035430 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.035430 # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::tsunami.ide 0.566860 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide 0.035429 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.035429 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.overall_misses::total 175 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 21956883 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21956883 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245212780 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 5245212780 # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245146529 # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total 5245146529 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 21956883 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 21956883 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 21956883 # number of overall miss cycles
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125467.902857 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 125467.902857 # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126232.498556 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 126232.498556 # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.904144 # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 126230.904144 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125467.902857 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency
system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13206883 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 13206883 # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165805993 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 3165805993 # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165739741 # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total 3165739741 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 13206883 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 13206883 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 13206883 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 75467.902857 # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76189.016004 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76189.016004 # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.421568 # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.421568 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 342144 # number of replacements
-system.l2c.tags.tagsinuse 65164.214079 # Cycle average of tags in use
-system.l2c.tags.total_refs 3686310 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 407150 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 9.053936 # Average number of references to valid blocks.
+system.l2c.tags.replacements 342136 # number of replacements
+system.l2c.tags.tagsinuse 65163.366749 # Cycle average of tags in use
+system.l2c.tags.total_refs 3685387 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 407142 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 9.051847 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 12928623000 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 54851.914684 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 4798.806705 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 5354.570072 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 119.591740 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 39.330879 # Average occupied blocks per requestor
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-system.l2c.overall_mshr_miss_rate::cpu1.data 0.048176 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.172959 # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68753.701211 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68858.917725 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68793.539619 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941997 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.767797 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.867452 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.957601 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.974843 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.966163 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480857 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.139589 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.415692 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018195 # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002791 # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013177 # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.291674 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002963 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260158 # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018195 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.330332 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002791 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.048180 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.172961 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018195 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.330332 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002791 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.048180 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.172961 # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68754.374159 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68857.615894 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68793.478261 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68479.481641 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68922.043011 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68701.239224 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117141.871853 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121624.666751 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 117429.294121 # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121368.002239 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122773.707974 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121465.120682 # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113994.501670 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 118394.658754 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113999.955862 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121368.002239 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114930.755419 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122773.707974 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121492.147553 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 115277.837125 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121368.002239 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114930.755419 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122773.707974 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121492.147553 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 115277.837125 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208711.191081 # average ReadReq mshr uncacheable latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117149.547708 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121705.725657 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 117441.691706 # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121152.163481 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121352.751888 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121166.009010 # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113991.494713 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 115926.035503 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113993.899770 # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121152.163481 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114930.886116 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121352.751888 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121467.924650 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 115267.622116 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121152.163481 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114930.886116 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121352.751888 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121467.924650 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 115267.622116 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208714.810109 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199792.372881 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208565.102721 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215871.939911 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.166069 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217869.374469 # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213032.484611 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223468.695903 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 214727.830896 # average overall mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208568.601583 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215874.478438 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.315412 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217871.488288 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213036.018191 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223468.840162 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 214731.131680 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 7204 # Transaction distribution
-system.membus.trans_dist::ReadResp 292685 # Transaction distribution
-system.membus.trans_dist::WriteReq 14132 # Transaction distribution
-system.membus.trans_dist::WriteResp 14132 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 120936 # Transaction distribution
+system.membus.trans_dist::ReadReq 7201 # Transaction distribution
+system.membus.trans_dist::ReadResp 292681 # Transaction distribution
+system.membus.trans_dist::WriteReq 14131 # Transaction distribution
+system.membus.trans_dist::WriteResp 14131 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 120928 # Transaction distribution
system.membus.trans_dist::CleanEvict 262098 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 16894 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 11785 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 16893 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 11783 # Transaction distribution
system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
-system.membus.trans_dist::ReadExReq 123162 # Transaction distribution
-system.membus.trans_dist::ReadExResp 122291 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 285481 # Transaction distribution
+system.membus.trans_dist::ReadExReq 123156 # Transaction distribution
+system.membus.trans_dist::ReadExResp 122284 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 285480 # Transaction distribution
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42672 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1185820 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 1228492 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42664 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1185794 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 1228458 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83437 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 83437 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1311929 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82507 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31152000 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 31234507 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total 1311895 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82454 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31150976 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 31233430 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 33892747 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 22774 # Total snoops (count)
-system.membus.snoop_fanout::samples 883255 # Request fanout histogram
+system.membus.pkt_size::total 33891670 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 22771 # Total snoops (count)
+system.membus.snoop_fanout::samples 883231 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 883255 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 883231 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 883255 # Request fanout histogram
-system.membus.reqLayer0.occupancy 40521000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 883231 # Request fanout histogram
+system.membus.reqLayer0.occupancy 40519500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 1327609723 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 1327558723 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2178253250 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2178214500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer2.occupancy 898617 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests 4790864 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 2395593 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 361656 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_requests 4790762 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 2395545 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 361654 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 1242 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 1182 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 7204 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2107176 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 14132 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 14132 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 913504 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean 1018097 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 816785 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 17065 # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq 7201 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2107124 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 14131 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 14131 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 913453 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean 1018074 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 816802 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 17061 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 11848 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 28913 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 297603 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 297603 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 1019283 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 1080704 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 28909 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 297601 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 297601 # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq 1019260 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 1080678 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2061018 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3585479 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 995618 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 558881 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 7200996 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 87922688 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118013949 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 42467904 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18601358 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 267005899 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 484765 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 2873241 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.136986 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.344076 # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2060877 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3585353 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 995690 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 558897 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 7200817 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 87916672 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118008584 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 42470976 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18601102 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 266997334 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 484769 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 2873172 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.136988 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.344078 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 2479885 86.31% 86.31% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 393120 13.68% 99.99% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 2479819 86.31% 86.31% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 393117 13.68% 99.99% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 234 0.01% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 2873241 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 4223821996 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 2873172 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 4223704496 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 297883 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 1031213250 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 1031139756 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1802267282 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 1802215285 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 499176813 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 499214310 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 293823888 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 293827886 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
---------- Begin Simulation Statistics ----------
-sim_seconds 2.871782 # Number of seconds simulated
-sim_ticks 2871782342000 # Number of ticks simulated
-final_tick 2871782342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.871806 # Number of seconds simulated
+sim_ticks 2871806231000 # Number of ticks simulated
+final_tick 2871806231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 937604 # Simulator instruction rate (inst/s)
host_op_rate 1134083 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 20478123685 # Simulator tick rate (ticks/s)
host_mem_usage 614632 # Number of bytes of host memory used
host_seconds 140.24 # Real time elapsed on the host
-sim_insts 131486349 # Number of instructions simulated
-sim_ops 159039994 # Number of ops (including micro ops) simulated
+sim_insts 131483712 # Number of instructions simulated
+sim_ops 159036662 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 1156004 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 1264932 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 8602496 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 151508 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 548500 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 349120 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 1158756 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 1268260 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 8634112 # Number of bytes read from this memory
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system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 12074032 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 1156004 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 151508 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1307512 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8524352 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8541916 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
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-system.physmem.num_reads::cpu0.data 20284 # Number of read requests responded to by this memory
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-system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
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-system.physmem.num_reads::cpu1.data 8591 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 197805 # Number of read requests responded to by this memory
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system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 137584 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 111 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_read::cpu0.data 440469 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 2995525 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 52757 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 190996 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 121569 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4204369 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 402539 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.bw_inst_read::total 455296 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2968314 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 6102 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2974430 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2968314 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 111 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 402539 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 446571 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 2995525 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 52757 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 191010 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7178799 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 197805 # Number of read requests accepted
-system.physmem.writeReqs 137584 # Number of write requests accepted
-system.physmem.readBursts 197805 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 137584 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 12650304 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue
-system.physmem.bytesWritten 8554240 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 12074032 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 8541916 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue
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+system.physmem.readReqs 198346 # Number of read requests accepted
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+system.physmem.bytesReadDRAM 12684736 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue
+system.physmem.bytesWritten 8566272 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 12108656 # Total read bytes from the system interface side
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system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 11699 # Per bank write bursts
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-system.physmem.perBankWrBursts::15 7348 # Per bank write bursts
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+system.physmem.perBankWrBursts::13 7999 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 27 # Number of times write queue was full causing retry
-system.physmem.totGap 2871781902000 # Total gap between requests
+system.physmem.numWrRetry 23 # Number of times write queue was full causing retry
+system.physmem.totGap 2871805791000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 9732 # Read request sizes (log2)
system.physmem.readPktSize::3 28 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 188045 # Read request sizes (log2)
+system.physmem.readPktSize::6 188586 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4391 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::42 151 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 92 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 103 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 60 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 92 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 63 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 107 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 87582 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 242.110023 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 136.595388 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 304.444001 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 46635 53.25% 53.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 17297 19.75% 73.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6011 6.86% 79.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3421 3.91% 83.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2493 2.85% 86.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1531 1.75% 88.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 857 0.98% 89.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 971 1.11% 90.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 8366 9.55% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 87582 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6415 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 30.812159 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 590.882305 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6413 99.97% 99.97% # Reads before turning the bus around for writes
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+system.physmem.bytesPerActivate::256-383 6112 6.95% 80.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3386 3.85% 83.85% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::640-767 1473 1.68% 88.33% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::896-1023 929 1.06% 90.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 8478 9.64% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 87931 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6424 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 30.852584 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6415 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6415 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.835542 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.951972 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 14.109397 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 5337 83.20% 83.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 463 7.22% 90.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 65 1.01% 91.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 41 0.64% 92.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 43 0.67% 92.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 15 0.23% 92.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 61 0.95% 93.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 12 0.19% 94.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 120 1.87% 95.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 12 0.19% 96.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 8 0.12% 96.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 12 0.19% 96.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 75 1.17% 97.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 9 0.14% 97.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 4 0.06% 97.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 25 0.39% 98.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 75 1.17% 99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 1 0.02% 99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 2 0.03% 99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 1 0.02% 99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 3 0.05% 99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 1 0.02% 99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 2 0.03% 99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 1 0.02% 99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 11 0.17% 99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 3 0.05% 99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 1 0.02% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 5 0.08% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 1 0.02% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 2 0.03% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 1 0.02% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211 2 0.03% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6415 # Writes before turning the bus around for reads
-system.physmem.totQLat 4510532456 # Total ticks spent queuing
-system.physmem.totMemAccLat 8216676206 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 988305000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 22819.54 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 6424 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6424 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 20.835616 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.963518 # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::128-131 10 0.16% 99.80% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::total 6424 # Writes before turning the bus around for reads
+system.physmem.totQLat 4482627455 # Total ticks spent queuing
+system.physmem.totMemAccLat 8198858705 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 990995000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 22616.80 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 41569.54 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 4.41 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 41366.80 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 4.20 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.97 # Average system write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.88 # Average write queue length when enqueuing
-system.physmem.readRowHits 165067 # Number of row buffer hits during reads
-system.physmem.writeRowHits 78671 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.51 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 58.85 # Row buffer hit rate for writes
-system.physmem.avgGap 8562540.52 # Average gap between requests
-system.physmem.pageHitRate 73.56 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 341273520 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 186210750 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 814335600 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 441495360 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 187570659120 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 86023351485 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1647608604750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1922985930585 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.614762 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2740794855198 # Time in different power states
-system.physmem_0.memoryStateTime::REF 95895020000 # Time in different power states
+system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing
+system.physmem.readRowHits 165480 # Number of row buffer hits during reads
+system.physmem.writeRowHits 78635 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 83.49 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 58.74 # Row buffer hit rate for writes
+system.physmem.avgGap 8544116.72 # Average gap between requests
+system.physmem.pageHitRate 73.51 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 342929160 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 187114125 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 816004800 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 442350720 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 187572184800 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 85984866225 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1647656379000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1923001828830 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.614852 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2740877422516 # Time in different power states
+system.physmem_0.memoryStateTime::REF 95895800000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 35089613552 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 35029624984 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 320846400 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 175065000 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 727412400 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 424621440 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 187570659120 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 84787415640 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1648692759000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1922698779000 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.514771 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2742610583350 # Time in different power states
-system.physmem_1.memoryStateTime::REF 95895020000 # Time in different power states
+system.physmem_1.actEnergy 321829200 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 175601250 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 729939600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 424984320 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 187572184800 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 85018582845 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1648503996000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1922747118015 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.526158 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2742296701194 # Time in different power states
+system.physmem_1.memoryStateTime::REF 95895800000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 33276576650 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 33613567806 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 8793 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 8793 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1631 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7162 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples 8793 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 8793 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 8793 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 7275 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 12044.604811 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 11100.960867 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 5725.376750 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383 6764 92.98% 92.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767 475 6.53% 99.51% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151 28 0.38% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.05% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-147455 2 0.03% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 7275 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks 8733 # Table walker walks requested
+system.cpu0.dtb.walker.walksShort 8733 # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1652 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7081 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples 8733 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 8733 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 8733 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 7215 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 12160.221760 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 11349.326630 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 6137.175819 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767 7184 99.57% 99.57% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535 27 0.37% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 7215 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 1809726500 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 1809726500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 1809726500 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 5691 78.23% 78.23% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1584 21.77% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 7275 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8793 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K 5610 77.75% 77.75% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M 1605 22.25% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 7215 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8733 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8793 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7275 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8733 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7215 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7275 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 16068 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7215 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 15948 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 25747110 # DTB read hits
-system.cpu0.dtb.read_misses 7587 # DTB read misses
-system.cpu0.dtb.write_hits 19248161 # DTB write hits
-system.cpu0.dtb.write_misses 1206 # DTB write misses
+system.cpu0.dtb.read_hits 25746594 # DTB read hits
+system.cpu0.dtb.read_misses 7520 # DTB read misses
+system.cpu0.dtb.write_hits 19247313 # DTB write hits
+system.cpu0.dtb.write_misses 1213 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3752 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 3753 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 1822 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 1863 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 321 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 25754697 # DTB read accesses
-system.cpu0.dtb.write_accesses 19249367 # DTB write accesses
+system.cpu0.dtb.read_accesses 25754114 # DTB read accesses
+system.cpu0.dtb.write_accesses 19248526 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 44995271 # DTB hits
-system.cpu0.dtb.misses 8793 # DTB misses
-system.cpu0.dtb.accesses 45004064 # DTB accesses
+system.cpu0.dtb.hits 44993907 # DTB hits
+system.cpu0.dtb.misses 8733 # DTB misses
+system.cpu0.dtb.accesses 45002640 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkWaitTime::0 3674 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 3674 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 2576 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 12540.566770 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11604.890292 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 7309.377161 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767 2541 98.64% 98.64% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-65535 33 1.28% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-163839 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-294911 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 12667.119565 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11857.484982 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 6117.849264 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-16383 2266 87.97% 87.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-32767 279 10.83% 98.80% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-49151 28 1.09% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 2576 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 1809154500 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 1809154500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2576 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2576 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 6250 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 121581439 # ITB inst hits
+system.cpu0.itb.inst_hits 121577578 # ITB inst hits
system.cpu0.itb.inst_misses 3674 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 121585113 # ITB inst accesses
-system.cpu0.itb.hits 121581439 # DTB hits
+system.cpu0.itb.inst_accesses 121581252 # ITB inst accesses
+system.cpu0.itb.hits 121577578 # DTB hits
system.cpu0.itb.misses 3674 # DTB misses
-system.cpu0.itb.accesses 121585113 # DTB accesses
-system.cpu0.numCycles 5743564684 # number of cpu cycles simulated
+system.cpu0.itb.accesses 121581252 # DTB accesses
+system.cpu0.numCycles 5743612462 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 1899 # number of quiesce instructions executed
-system.cpu0.committedInsts 117764996 # Number of instructions committed
-system.cpu0.committedOps 142323546 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 125936873 # Number of integer alu accesses
+system.cpu0.kern.inst.quiesce 1891 # number of quiesce instructions executed
+system.cpu0.committedInsts 117761026 # Number of instructions committed
+system.cpu0.committedOps 142319020 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 125932364 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 11483 # Number of float alu accesses
-system.cpu0.num_func_calls 12772448 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 16008688 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 125936873 # number of integer instructions
+system.cpu0.num_func_calls 12772321 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 16008283 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 125932364 # number of integer instructions
system.cpu0.num_fp_insts 11483 # number of float instructions
-system.cpu0.num_int_register_reads 231719006 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 87450436 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 231711074 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 87448067 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 8771 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 2716 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 515468589 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 53496392 # number of times the CC registers were written
-system.cpu0.num_mem_refs 46152180 # number of memory refs
-system.cpu0.num_load_insts 26006060 # Number of load instructions
-system.cpu0.num_store_insts 20146120 # Number of store instructions
-system.cpu0.num_idle_cycles 5455990176.452100 # Number of idle cycles
-system.cpu0.num_busy_cycles 287574507.547900 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.050069 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.949931 # Percentage of idle cycles
-system.cpu0.Branches 29546529 # Number of branches fetched
+system.cpu0.num_cc_register_reads 515452324 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 53494266 # number of times the CC registers were written
+system.cpu0.num_mem_refs 46150372 # number of memory refs
+system.cpu0.num_load_insts 26005626 # Number of load instructions
+system.cpu0.num_store_insts 20144746 # Number of store instructions
+system.cpu0.num_idle_cycles 5456042423.958100 # Number of idle cycles
+system.cpu0.num_busy_cycles 287570038.041900 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.050068 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.949932 # Percentage of idle cycles
+system.cpu0.Branches 29545974 # Number of branches fetched
system.cpu0.op_class::No_OpClass 2315 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 99842345 68.33% 68.33% # Class of executed instruction
-system.cpu0.op_class::IntMult 112141 0.08% 68.41% # Class of executed instruction
+system.cpu0.op_class::IntAlu 99839256 68.33% 68.33% # Class of executed instruction
+system.cpu0.op_class::IntMult 112113 0.08% 68.41% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 68.41% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 68.41% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 8311 0.01% 68.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 8315 0.01% 68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.41% # Class of executed instruction
-system.cpu0.op_class::MemRead 26006060 17.80% 86.21% # Class of executed instruction
-system.cpu0.op_class::MemWrite 20146120 13.79% 100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead 26005626 17.80% 86.21% # Class of executed instruction
+system.cpu0.op_class::MemWrite 20144746 13.79% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 146117292 # Class of executed instruction
-system.cpu0.dcache.tags.replacements 732778 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 487.345221 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 44083181 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 733290 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 60.116981 # Average number of references to valid blocks.
+system.cpu0.op_class::total 146112371 # Class of executed instruction
+system.cpu0.dcache.tags.replacements 733230 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 488.702331 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 44081285 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 733742 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 60.077364 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 1836359000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 487.345221 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.951846 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.951846 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 488.702331 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.954497 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.954497 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 90667478 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 90667478 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 24441740 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 24441740 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 18494582 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 18494582 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 326232 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 326232 # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374079 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 374079 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 371656 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 371656 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 42936322 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 42936322 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 43262554 # number of overall hits
-system.cpu0.dcache.overall_hits::total 43262554 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 418013 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 418013 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 337667 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 337667 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 133440 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 133440 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22337 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 22337 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19808 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 19808 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 755680 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 755680 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 889120 # number of overall misses
-system.cpu0.dcache.overall_misses::total 889120 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5665137000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 5665137000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6926542000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 6926542000 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 343483500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 343483500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 502731000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 502731000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1840500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1840500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 12591679000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 12591679000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 12591679000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 12591679000 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 24859753 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 24859753 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 18832249 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 18832249 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 459672 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 459672 # number of SoftPFReq accesses(hits+misses)
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-system.cpu0.dcache.LoadLockedReq_accesses::total 396416 # number of LoadLockedReq accesses(hits+misses)
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-system.cpu0.dcache.StoreCondReq_accesses::total 391464 # number of StoreCondReq accesses(hits+misses)
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-system.cpu0.dcache.overall_accesses::total 44151674 # number of overall (read+write) accesses
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-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.290294 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056347 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056347 # miss rate for LoadLockedReq accesses
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-system.cpu0.dcache.demand_miss_rate::total 0.017296 # miss rate for demand accesses
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-system.cpu0.dcache.overall_miss_rate::total 0.020138 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13552.537840 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13552.537840 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20512.937302 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 20512.937302 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15377.333572 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15377.333572 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25380.199919 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25380.199919 # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses 90665231 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 90665231 # Number of data accesses
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+system.cpu0.dcache.SoftPFReq_hits::total 326163 # number of SoftPFReq hits
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+system.cpu0.dcache.ReadReq_misses::total 418663 # number of ReadReq misses
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+system.cpu0.dcache.WriteReq_misses::total 337563 # number of WriteReq misses
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+system.cpu0.dcache.SoftPFReq_misses::total 133473 # number of SoftPFReq misses
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+system.cpu0.dcache.LoadLockedReq_misses::total 22401 # number of LoadLockedReq misses
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+system.cpu0.dcache.StoreCondReq_misses::total 19896 # number of StoreCondReq misses
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+system.cpu0.dcache.demand_misses::total 756226 # number of demand (read+write) misses
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+system.cpu0.dcache.ReadReq_miss_latency::total 5670544000 # number of ReadReq miss cycles
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+system.cpu0.dcache.LoadLockedReq_miss_latency::total 345375500 # number of LoadLockedReq miss cycles
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+system.cpu0.dcache.StoreCondReq_miss_latency::total 506120500 # number of StoreCondReq miss cycles
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+system.cpu0.dcache.overall_accesses::total 44150273 # number of overall (read+write) accesses
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+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13544.411615 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13544.411615 # average ReadReq miss latency
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system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16662.713053 # average overall miss latency
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+system.cpu0.dcache.demand_avg_miss_latency::total 16651.932756 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14153.803140 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 14153.803140 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 732778 # number of writebacks
-system.cpu0.dcache.writebacks::total 732778 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25286 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 25286 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15664 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15664 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 25288 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 25288 # number of demand (read+write) MSHR hits
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-system.cpu0.dcache.overall_mshr_hits::total 25288 # number of overall MSHR hits
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-system.cpu0.dcache.overall_mshr_misses::total 836730 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31820 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31820 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.writebacks::writebacks 733230 # number of writebacks
+system.cpu0.dcache.writebacks::total 733230 # number of writebacks
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+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits
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+system.cpu0.dcache.overall_mshr_hits::total 25286 # number of overall MSHR hits
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+system.cpu0.dcache.ReadReq_mshr_misses::total 393378 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337562 # number of WriteReq MSHR misses
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system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102846500 # number of LoadLockedReq MSHR miss cycles
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-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1793500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1793500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11432271500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 11432271500 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12029928000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015798 # mshr miss rate for ReadReq accesses
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016833 # mshr miss rate for LoadLockedReq accesses
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-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12332.859722 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12332.859722 # average ReadReq mshr miss latency
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-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16335.693731 # average SoftPFReq mshr miss latency
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-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15412.333283 # average LoadLockedReq mshr miss latency
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-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24382.572698 # average StoreCondReq mshr miss latency
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+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628843000 # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16344.342772 # average SoftPFReq mshr miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15507.679690 # average LoadLockedReq mshr miss latency
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system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
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-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15652.240851 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15652.240851 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15739.099232 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15739.099232 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208329.666876 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208329.666876 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189511.140742 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189511.140742 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199438.452229 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199438.452229 # average overall mshr uncacheable latency
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-system.cpu0.icache.tags.total_refs 120433653 # Total number of references to valid blocks.
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system.cpu0.icache.tags.warmup_cycle 14862010000 # Cycle when the warmup percentage was hit.
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system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency
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+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36920.891101 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77179.151703 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63704.390920 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200316.687618 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185110.633661 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182006.877434 # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182006.877434 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200329.807964 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185119.738485 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182008.368715 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182008.368715 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191665.826688 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183834.996611 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191673.022084 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183840.916958 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests 3905249 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1969182 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28911 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 320342 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 316677 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3665 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq 63843 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 1765873 # Transaction distribution
+system.cpu0.toL2Bus.snoop_filter.tot_requests 3905427 # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1969134 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28903 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops 319838 # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 316964 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2874 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq 63699 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 1766064 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 28499 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 28499 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty 732965 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean 1379104 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict 189043 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 312150 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 85708 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41941 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 112560 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 301555 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 298207 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1147786 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 575214 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 3299 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3460881 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2681738 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11926 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27058 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 6181603 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 146919352 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 101652834 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 19592 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 44412 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 248636190 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 986669 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 2981108 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.123159 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.332339 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::WritebackDirty 734457 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean 1378164 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict 189732 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 311664 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 85807 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41981 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 112714 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 301438 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 298033 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1147547 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq 575765 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq 3263 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3460164 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2683424 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12059 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27146 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 6182793 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 146888760 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 101708758 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 20124 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 45328 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 248662970 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 986506 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 2981817 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 0.122538 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.330833 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 2617624 87.81% 87.81% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 359819 12.07% 99.88% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 3665 0.12% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 2619305 87.84% 87.84% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 359638 12.06% 99.90% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 2874 0.10% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 2981108 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 3885976496 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 2981817 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 3886437494 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 115188451 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 115091926 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 1730701000 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 1730342500 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 1266054481 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 1266858980 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 7028000 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 15961487 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 15821984 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 2346 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 2346 # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 473 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1873 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 2346 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 2346 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 2346 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 1700 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 11761.764706 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 11073.675458 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 5957.546231 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-16383 1554 91.41% 91.41% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-32767 135 7.94% 99.35% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-49151 5 0.29% 99.65% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-65535 5 0.29% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.06% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 1700 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks 2347 # Table walker walks requested
+system.cpu1.dtb.walker.walksShort 2347 # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 475 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1872 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples 2347 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 2347 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 2347 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 1701 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 11647.854203 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 11021.395784 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 4763.004778 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-4095 3 0.18% 0.18% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::4096-8191 360 21.16% 21.34% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-12287 989 58.14% 79.48% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::12288-16383 206 12.11% 91.59% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-20479 34 2.00% 93.59% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::20480-24575 60 3.53% 97.12% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-28671 28 1.65% 98.77% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::28672-32767 11 0.65% 99.41% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-36863 1 0.06% 99.47% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::36864-40959 2 0.12% 99.59% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.18% 99.76% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-53247 3 0.18% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.06% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 1701 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples -1207257828 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 -1207257828 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total -1207257828 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 1227 72.18% 72.18% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 473 27.82% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 1700 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2346 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K 1226 72.08% 72.08% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M 475 27.92% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 1701 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2347 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2346 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1700 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2347 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1701 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1700 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 4046 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1701 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 4048 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 3334779 # DTB read hits
-system.cpu1.dtb.read_misses 1954 # DTB read misses
-system.cpu1.dtb.write_hits 2915242 # DTB write hits
-system.cpu1.dtb.write_misses 392 # DTB write misses
+system.cpu1.dtb.read_hits 3334777 # DTB read hits
+system.cpu1.dtb.read_misses 1951 # DTB read misses
+system.cpu1.dtb.write_hits 2915290 # DTB write hits
+system.cpu1.dtb.write_misses 396 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 1652 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 260 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 124 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 3336733 # DTB read accesses
-system.cpu1.dtb.write_accesses 2915634 # DTB write accesses
+system.cpu1.dtb.read_accesses 3336728 # DTB read accesses
+system.cpu1.dtb.write_accesses 2915686 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 6250021 # DTB hits
-system.cpu1.dtb.misses 2346 # DTB misses
-system.cpu1.dtb.accesses 6252367 # DTB accesses
+system.cpu1.dtb.hits 6250067 # DTB hits
+system.cpu1.dtb.misses 2347 # DTB misses
+system.cpu1.dtb.accesses 6252414 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkWaitTime::total 1376 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 819 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 11933.455433 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 11288.127256 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 5150.797327 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191 116 14.16% 14.16% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287 577 70.45% 84.62% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383 76 9.28% 93.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479 8 0.98% 94.87% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.24% 95.12% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671 22 2.69% 97.80% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.98% 98.78% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 98.90% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.61% 99.51% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11302.540712 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 5121.103483 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191 113 13.80% 13.80% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287 572 69.84% 83.64% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383 87 10.62% 94.26% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479 7 0.85% 95.12% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.12% 95.24% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671 23 2.81% 98.05% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.98% 99.02% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959 4 0.49% 99.51% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.24% 99.76% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.24% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.12% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.12% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 819 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples -1208095828 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 -1208095828 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 819 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 819 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 2195 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 13920333 # ITB inst hits
+system.cpu1.itb.inst_hits 13921759 # ITB inst hits
system.cpu1.itb.inst_misses 1376 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 13921709 # ITB inst accesses
-system.cpu1.itb.hits 13920333 # DTB hits
+system.cpu1.itb.inst_accesses 13923135 # ITB inst accesses
+system.cpu1.itb.hits 13921759 # DTB hits
system.cpu1.itb.misses 1376 # DTB misses
-system.cpu1.itb.accesses 13921709 # DTB accesses
-system.cpu1.numCycles 5742623362 # number of cpu cycles simulated
+system.cpu1.itb.accesses 13923135 # DTB accesses
+system.cpu1.numCycles 5742672703 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2722 # number of quiesce instructions executed
-system.cpu1.committedInsts 13721353 # Number of instructions committed
-system.cpu1.committedOps 16716448 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 15155011 # Number of integer alu accesses
+system.cpu1.kern.inst.quiesce 2702 # number of quiesce instructions executed
+system.cpu1.committedInsts 13722686 # Number of instructions committed
+system.cpu1.committedOps 16717642 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 15156242 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu1.num_func_calls 915079 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 1497955 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 15155011 # number of integer instructions
+system.cpu1.num_func_calls 915130 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 1497977 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 15156242 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 27537464 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 10698089 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 27539507 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 10698774 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 61338598 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 5194112 # number of times the CC registers were written
-system.cpu1.num_mem_refs 6464162 # number of memory refs
-system.cpu1.num_load_insts 3439477 # Number of load instructions
-system.cpu1.num_store_insts 3024685 # Number of store instructions
-system.cpu1.num_idle_cycles 5696031009.438875 # Number of idle cycles
-system.cpu1.num_busy_cycles 46592352.561125 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.008113 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.991887 # Percentage of idle cycles
-system.cpu1.Branches 2464329 # Number of branches fetched
+system.cpu1.num_cc_register_reads 61342237 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 5194989 # number of times the CC registers were written
+system.cpu1.num_mem_refs 6464220 # number of memory refs
+system.cpu1.num_load_insts 3439445 # Number of load instructions
+system.cpu1.num_store_insts 3024775 # Number of store instructions
+system.cpu1.num_idle_cycles 5696078911.641530 # Number of idle cycles
+system.cpu1.num_busy_cycles 46593791.358469 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.008114 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.991886 # Percentage of idle cycles
+system.cpu1.Branches 2464409 # Number of branches fetched
system.cpu1.op_class::No_OpClass 24 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 10543721 61.89% 61.89% # Class of executed instruction
-system.cpu1.op_class::IntMult 24250 0.14% 62.04% # Class of executed instruction
+system.cpu1.op_class::IntAlu 10544854 61.90% 61.90% # Class of executed instruction
+system.cpu1.op_class::IntMult 24300 0.14% 62.04% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 62.04% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 62.04% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 62.04% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.04% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.04% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.04% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 3188 0.02% 62.05% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 62.05% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.05% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.05% # Class of executed instruction
-system.cpu1.op_class::MemRead 3439477 20.19% 82.24% # Class of executed instruction
-system.cpu1.op_class::MemWrite 3024685 17.76% 100.00% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 3186 0.02% 62.06% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 62.06% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.06% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.06% # Class of executed instruction
+system.cpu1.op_class::MemRead 3439445 20.19% 82.25% # Class of executed instruction
+system.cpu1.op_class::MemWrite 3024775 17.75% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 17035345 # Class of executed instruction
-system.cpu1.dcache.tags.replacements 148314 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 469.091453 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 6019898 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 148666 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 40.492769 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 106291978000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.091453 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916194 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.916194 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 352 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 33 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 12680697 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 12680697 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 3066133 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 3066133 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 2748576 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 2748576 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41842 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 41842 # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69851 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 69851 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61610 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 61610 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 5814709 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 5814709 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 5856551 # number of overall hits
-system.cpu1.dcache.overall_hits::total 5856551 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 112800 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 112800 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 79377 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 79377 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24461 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 24461 # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16636 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 16636 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23088 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 23088 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 192177 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 192177 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 216638 # number of overall misses
-system.cpu1.dcache.overall_misses::total 216638 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1758096000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 1758096000 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2710284000 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 2710284000 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320294000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 320294000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 628163500 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 628163500 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3848000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3848000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 4468380000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 4468380000 # number of demand (read+write) miss cycles
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-system.cpu1.dcache.overall_miss_latency::total 4468380000 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 3178933 # number of ReadReq accesses(hits+misses)
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-system.cpu1.dcache.WriteReq_accesses::cpu1.data 2827953 # number of WriteReq accesses(hits+misses)
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-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66303 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 66303 # number of SoftPFReq accesses(hits+misses)
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-system.cpu1.dcache.LoadLockedReq_accesses::total 86487 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84698 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 84698 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 6006886 # number of demand (read+write) accesses
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-system.cpu1.dcache.overall_accesses::total 6073189 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035484 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.035484 # miss rate for ReadReq accesses
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-system.cpu1.dcache.WriteReq_miss_rate::total 0.028069 # miss rate for WriteReq accesses
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-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.368927 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.192353 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.192353 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.272592 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.272592 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031993 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.031993 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035671 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.035671 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15585.957447 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15585.957447 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34144.449904 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 34144.449904 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19253.065641 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19253.065641 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27207.358801 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27207.358801 # average StoreCondReq miss latency
+system.cpu1.op_class::total 17036584 # Class of executed instruction
+system.cpu1.dcache.tags.replacements 148452 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 468.602887 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 6022671 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 148794 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 40.476572 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 106290860000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.602887 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.915240 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.915240 # Average percentage of cache occupancy
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+system.cpu1.dcache.tags.age_task_id_blocks_1024::3 36 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.667969 # Percentage of cache occupancy per task id
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+system.cpu1.dcache.tags.data_accesses 12680857 # Number of data accesses
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+system.cpu1.dcache.StoreCondReq_hits::total 61599 # number of StoreCondReq hits
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+system.cpu1.dcache.overall_hits::total 5856474 # number of overall hits
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+system.cpu1.dcache.ReadReq_miss_latency::total 1761858500 # number of ReadReq miss cycles
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+system.cpu1.dcache.LoadLockedReq_miss_latency::total 321180000 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 626224500 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total 626224500 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5032000 # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5032000 # number of StoreCondFailReq miss cycles
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+system.cpu1.dcache.overall_miss_latency::total 4468930500 # number of overall miss cycles
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+system.cpu1.dcache.WriteReq_accesses::total 2828006 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66287 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total 66287 # number of SoftPFReq accesses(hits+misses)
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+system.cpu1.dcache.StoreCondReq_accesses::total 84696 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 6006956 # number of demand (read+write) accesses
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+system.cpu1.dcache.overall_accesses::total 6073243 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035517 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.035517 # miss rate for ReadReq accesses
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+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.367930 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.191941 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.191941 # miss rate for LoadLockedReq accesses
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+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.272705 # miss rate for StoreCondReq accesses
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+system.cpu1.dcache.demand_miss_rate::total 0.032026 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035692 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.035692 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15604.372587 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15604.372587 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34063.217234 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 34063.217234 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19348.192771 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19348.192771 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27112.806858 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27112.806858 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23251.377636 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 23251.377636 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20626.021289 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 20626.021289 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23229.704231 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 23229.704231 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20616.095936 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 20616.095936 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 148314 # number of writebacks
-system.cpu1.dcache.writebacks::total 148314 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 199 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 199 # number of ReadReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11732 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11732 # number of LoadLockedReq MSHR hits
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-system.cpu1.dcache.demand_mshr_hits::total 199 # number of demand (read+write) MSHR hits
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-system.cpu1.dcache.overall_mshr_hits::total 199 # number of overall MSHR hits
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-system.cpu1.dcache.ReadReq_mshr_misses::total 112601 # number of ReadReq MSHR misses
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-system.cpu1.dcache.WriteReq_mshr_misses::total 79377 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 24003 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 24003 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4904 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4904 # number of LoadLockedReq MSHR misses
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-system.cpu1.dcache.StoreCondReq_mshr_misses::total 23088 # number of StoreCondReq MSHR misses
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-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3083 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3083 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2425 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2425 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5508 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5508 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1635811500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1635811500 # number of ReadReq MSHR miss cycles
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89921000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89921000 # number of LoadLockedReq MSHR miss cycles
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-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 605110500 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3813000 # number of StoreCondFailReq MSHR miss cycles
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-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035421 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035421 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028069 # mshr miss rate for WriteReq accesses
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-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.362020 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056702 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056702 # mshr miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035563 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.035563 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14527.504196 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14527.504196 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33144.449904 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33144.449904 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17979.940007 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17979.940007 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18336.256117 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18336.256117 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26208.874740 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26208.874740 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 148452 # number of writebacks
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+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035447 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035447 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028102 # mshr miss rate for WriteReq accesses
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+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.360930 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056993 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056993 # mshr miss rate for LoadLockedReq accesses
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+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.272705 # mshr miss rate for StoreCondReq accesses
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+system.cpu1.dcache.demand_mshr_miss_rate::total 0.031989 # mshr miss rate for demand accesses
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+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14508.829924 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14508.829924 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33063.217234 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33063.217234 # average WriteReq mshr miss latency
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+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18282.194357 # average SoftPFReq mshr miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18586.021505 # average LoadLockedReq mshr miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22225.038807 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22225.038807 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21753.260703 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21753.260703 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142569.412910 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142569.412910 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125058.969072 # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125058.969072 # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134860.112564 # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134860.112564 # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22182.525227 # average overall mshr miss latency
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+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21750.673355 # average overall mshr miss latency
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+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.124642 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.166480 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.140986 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.637826 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.637826 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019198 # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.019198 # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.451423 # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451423 # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.124153 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.169109 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.019198 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.500380 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159871 # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.124153 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.169109 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.019198 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.500380 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.635821 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.635821 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018914 # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018914 # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.451105 # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451105 # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.124642 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.166480 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018914 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.499625 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159462 # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.124642 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.166480 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018914 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.499625 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191827 # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14162.808642 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44272.218526 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44272.218526 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19901.166603 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19901.166603 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18706.436523 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18706.436523 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 3550000 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 3550000 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44810.382905 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44810.382905 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 53553.834063 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 53553.834063 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16480.612085 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16480.612085 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 53553.834063 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25964.974122 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28219.919685 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 53553.834063 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25964.974122 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44272.218526 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30894.056879 # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191241 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14073.275862 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14013.931889 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44184.581154 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44184.581154 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19905.624978 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19905.624978 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18619.565217 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18619.565217 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 926400 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 926400 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44732.064878 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44732.064878 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54263.616682 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54263.616682 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16588.591834 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16588.591834 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14073.275862 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54263.616682 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25996.256868 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28277.957107 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14073.275862 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54263.616682 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25996.256868 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44184.581154 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30921.170050 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134456.373662 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133971.779141 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117555.463918 # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117555.463918 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134498.053212 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134011.046333 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117604.416013 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117604.416013 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127015.432099 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126969.217238 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127062.397820 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127014.695530 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests 1324645 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 668824 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10099 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 169409 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 166956 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2453 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq 10097 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 652790 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 2425 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 2425 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty 119017 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean 519745 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict 86537 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 25449 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 70337 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40896 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 84740 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 57665 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 55147 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 463944 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 215084 # Transaction distribution
+system.cpu1.toL2Bus.snoop_filter.tot_requests 1324952 # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests 669028 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10089 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops 168501 # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 166697 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1804 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq 10096 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 652859 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 2423 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 2423 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty 119114 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean 519969 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict 86535 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 25223 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 70168 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40922 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 84814 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 57641 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 55180 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq 463996 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq 214635 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 32 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1391674 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 722021 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4392 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7022 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 2125109 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 59352772 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24485096 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7096 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11212 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 83856176 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 356096 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 999531 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.187033 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.396182 # Request fanout histogram
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1391830 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 722434 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4408 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7011 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 2125683 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 59359428 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24498524 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7160 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11168 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 83876280 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 355270 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 998881 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 0.185518 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.393336 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 815039 81.54% 81.54% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 182039 18.21% 99.75% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 2453 0.25% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 815375 81.63% 81.63% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 181702 18.19% 99.82% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 1804 0.18% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 999531 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 1279051999 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 998881 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 1279425500 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 79434008 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 79453408 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 696093000 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 696171000 # Layer occupancy (ticks)
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-system.l2c.overall_mshr_miss_rate::total 0.567233 # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72729.970168 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72293.908404 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72645.681135 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74539.182283 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73949.923547 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74132.453826 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135769.705956 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120850.135785 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 129627.654333 # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 125400 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 171000 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121526.656134 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126244.086300 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 136500 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 122783.415359 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130687.195274 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133669.083481 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125400 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 171000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121526.656134 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131540.121161 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 136500 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122783.415359 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121771.822748 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 133263.982012 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125400 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 171000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121526.656134 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131540.121161 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 136500 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122783.415359 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121771.822748 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 133263.982012 # average overall mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.224375 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.533969 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.252741 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.224278 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.576698 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.383350 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.729691 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.849223 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.774186 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.065217 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.028571 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.382564 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.158077 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740224 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.268345 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.135328 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.622618 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total 0.552352 # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.065217 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.028571 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.382564 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.280813 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740224 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.268345 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.568439 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.622618 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.568622 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.065217 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.028571 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.382564 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.280813 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740224 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.268345 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.568439 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.622618 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.568622 # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72734.033433 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72331.696429 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72656.152783 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74575.082508 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73932.527301 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74138.771186 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135700.046305 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121478.197794 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 129892.979915 # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 124916.666667 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121559.878933 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126142.550983 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135080.747196 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123628.455626 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 140210.435930 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145140.941337 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133411.035014 # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 124916.666667 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121559.878933 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131475.089851 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135080.747196 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123628.455626 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123232.210446 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145140.941337 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 133059.737740 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 124916.666667 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121559.878933 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131475.089851 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135080.747196 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123628.455626 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123232.210446 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145140.941337 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 133059.737740 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182316.341923 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182329.650847 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116572.727273 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163341.515681 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165006.368645 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100538.350928 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159950.911945 # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116613.998376 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163353.770314 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165007.403804 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100578.208832 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159958.831932 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174137.875296 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174144.978148 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109509.446140 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 161943.930541 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109552.072156 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 161954.377048 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 44099 # Transaction distribution
-system.membus.trans_dist::ReadResp 213926 # Transaction distribution
-system.membus.trans_dist::WriteReq 30924 # Transaction distribution
-system.membus.trans_dist::WriteResp 30924 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 133193 # Transaction distribution
-system.membus.trans_dist::CleanEvict 14771 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 73670 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 39871 # Transaction distribution
+system.membus.trans_dist::ReadReq 44095 # Transaction distribution
+system.membus.trans_dist::ReadResp 214453 # Transaction distribution
+system.membus.trans_dist::WriteReq 30922 # Transaction distribution
+system.membus.trans_dist::WriteResp 30922 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 133378 # Transaction distribution
+system.membus.trans_dist::CleanEvict 14958 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 73332 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 39852 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
-system.membus.trans_dist::ReadExReq 39385 # Transaction distribution
-system.membus.trans_dist::ReadExResp 18791 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 169827 # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
+system.membus.trans_dist::ReadExReq 39426 # Transaction distribution
+system.membus.trans_dist::ReadExResp 18801 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 170358 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13776 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 650336 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 772080 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13764 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 651465 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 773197 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72955 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72955 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 845035 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 846152 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27552 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18297804 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 18488238 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18344268 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 18534678 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 20806382 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 121083 # Total snoops (count)
-system.membus.snoop_fanout::samples 581994 # Request fanout histogram
+system.membus.pkt_size::total 20852822 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 120859 # Total snoops (count)
+system.membus.snoop_fanout::samples 582572 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 581994 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 582572 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 581994 # Request fanout histogram
-system.membus.reqLayer0.occupancy 88286500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 582572 # Request fanout histogram
+system.membus.reqLayer0.occupancy 88269500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 11391000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 11360500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 968108262 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 969988933 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1106274782 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1109172490 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 1388877 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 1385877 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 960339 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 518534 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 139328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 20435 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 19626 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 809 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 44102 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 468032 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 30924 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 30924 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 390589 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 105128 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 107757 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 42814 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 150571 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 82 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 50426 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 50426 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 423945 # Transaction distribution
+system.toL2Bus.snoop_filter.tot_requests 961097 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 519247 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 138785 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 20683 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 19864 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 819 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq 44098 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 467805 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 30922 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 30922 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 391320 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 106223 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 107477 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 42889 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 150366 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 104 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 50473 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 50473 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 423722 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1240075 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 253445 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1493520 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34222158 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3776032 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 37998190 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 438746 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 896439 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.337268 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.474682 # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1241271 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 253131 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1494402 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34264962 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3773844 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 38038806 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 438960 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 896783 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.336520 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.474448 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 594908 66.36% 66.36% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 300722 33.55% 99.91% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 809 0.09% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 595817 66.44% 66.44% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 300147 33.47% 99.91% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 819 0.09% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 896439 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 863728414 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 896783 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 864823852 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 360123 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 645946273 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 645977888 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 202615858 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 202227821 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff