[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

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+Date: Wed, 18 Mar 2020 20:51:20 +0000
+X-Bugzilla-Reason: CC
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Specification
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: mtnolan2640@gmail.com
+X-Bugzilla-Status: CONFIRMED
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+X-Bugzilla-Assigned-To: lkcl@lkcl.net
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+Message-ID: <bug-186-13-9qRKWt4hxm@http.bugs.libre-riscv.org/>
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+Subject: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and
+ RISC-V
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