Fixed bug in memory_share for memory ports with different ABITS

diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index f298169dec3b1c6067a6ec6e53972eb33942d86d..bcb7433a27ea758f8d28065c7ffe190e27ac71c5 100644 (file)
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -619,6 +619,12 @@ struct MemoryShareWorker
 
                        RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
 
+                       if (GetSize(last_addr) < GetSize(this_addr))
+                               last_addr.extend_u0(GetSize(this_addr));
+                       else
+                               this_addr.extend_u0(GetSize(last_addr));
+
+                       wr_ports[i]->setParam("\\ABITS", GetSize(this_addr));
                        wr_ports[i]->setPort("\\ADDR", module->Mux(NEW_ID, last_addr, this_addr, this_en_active));
                        wr_ports[i]->setPort("\\DATA", module->Mux(NEW_ID, last_data, this_data, this_en_active));