Added initial version of "synth_gowin"

diff --git a/techlibs/gowin/Makefile.inc b/techlibs/gowin/Makefile.inc
new file mode 100644 (file)
index 0000000..679d7ef
--- /dev/null
+++ b/techlibs/gowin/Makefile.inc
@@ -0,0 +1,6 @@
+
+OBJS += techlibs/gowin/synth_gowin.o
+
+$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v))
+$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v))
+

diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v
new file mode 100644 (file)
index 0000000..e1f85ef
--- /dev/null
+++ b/techlibs/gowin/cells_map.v
@@ -0,0 +1,31 @@
+module  \$_DFF_N_ (input D, C, output Q); DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
+module  \$_DFF_P_ (input D, C, output Q); DFF  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
+
+module \$lut (A, Y);
+  parameter WIDTH = 0;
+  parameter LUT = 0;
+
+  input [WIDTH-1:0] A;
+  output Y;
+
+  generate
+    if (WIDTH == 1) begin
+      LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
+        .I0(A[0]));
+    end else
+    if (WIDTH == 2) begin
+      LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
+        .I0(A[0]), .I1(A[1]));
+    end else
+    if (WIDTH == 3) begin
+      LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
+        .I0(A[0]), .I1(A[1]), .I2(A[2]));
+    end else
+    if (WIDTH == 4) begin
+      LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
+        .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
+    end else begin
+      wire _TECHMAP_FAIL_ = 1;
+    end
+  endgenerate
+endmodule

diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
new file mode 100644 (file)
index 0000000..3a09c15
--- /dev/null
+++ b/techlibs/gowin/cells_sim.v
@@ -0,0 +1,51 @@
+module LUT1(output F, input I0);
+  parameter [1:0] INIT = 0;
+  assign F = I0 ? INIT[1] : INIT[0];
+endmodule
+
+module LUT2(output F, input I0, I1);
+  parameter [3:0] INIT = 0;
+  wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
+  assign F = I0 ? s1[1] : s1[0];
+endmodule
+
+module LUT3(output F, input I0, I1, I2);
+  parameter [7:0] INIT = 0;
+  wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
+  wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
+  assign F = I0 ? s1[1] : s1[0];
+endmodule
+
+module LUT4(output F, input I0, I1, I2, I3);
+  parameter [15:0] INIT = 0;
+  wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
+  wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
+  wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
+  assign F = I0 ? s1[1] : s1[0];
+endmodule
+
+module DFF (output reg Q, input CLK, D);
+       always @(posedge C)
+               Q <= D;
+endmodule
+
+module DFFN (output reg Q, input CLK, D);
+       always @(negedge C)
+               Q <= D;
+endmodule
+
+module VCC(output V);
+  assign V = 1;
+endmodule
+
+module GND(output G);
+  assign G = 0;
+endmodule
+
+module IBUF(output O, input I);
+  assign O = I;
+endmodule
+
+module OBUF(output O, input I);
+  assign O = I;
+endmodule

diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
new file mode 100644 (file)
index 0000000..129ab83
--- /dev/null
+++ b/techlibs/gowin/synth_gowin.cc
@@ -0,0 +1,178 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SynthGowinPass : public ScriptPass
+{
+       SynthGowinPass() : ScriptPass("synth_gowin", "synthesis for Gowin FPGAs") { }
+
+       virtual void help() YS_OVERRIDE
+       {
+               //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+               log("\n");
+               log("    synth_gowin [options]\n");
+               log("\n");
+               log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n");
+               log("\n");
+               log("    -top <module>\n");
+               log("        use the specified module as top module (default='top')\n");
+               log("\n");
+               log("    -vout <file>\n");
+               log("        write the design to the specified Verilog netlist file. writing of an\n");
+               log("        output file is omitted if this parameter is not specified.\n");
+               log("\n");
+               log("    -run <from_label>:<to_label>\n");
+               log("        only run the commands between the labels (see below). an empty\n");
+               log("        from label is synonymous to 'begin', and empty to label is\n");
+               log("        synonymous to the end of the command list.\n");
+               log("\n");
+               log("    -retime\n");
+               log("        run 'abc' with -dff option\n");
+               log("\n");
+               log("\n");
+               log("The following commands are executed by this synthesis command:\n");
+               help_script();
+               log("\n");
+       }
+
+       string top_opt, vout_file;
+       bool retime;
+
+       virtual void clear_flags() YS_OVERRIDE
+       {
+               top_opt = "-auto-top";
+               vout_file = "";
+               retime = false;
+       }
+
+       virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+       {
+               string run_from, run_to;
+               clear_flags();
+
+               size_t argidx;
+               for (argidx = 1; argidx < args.size(); argidx++)
+               {
+                       if (args[argidx] == "-top" && argidx+1 < args.size()) {
+                               top_opt = "-top " + args[++argidx];
+                               continue;
+                       }
+                       if (args[argidx] == "-vout" && argidx+1 < args.size()) {
+                               vout_file = args[++argidx];
+                               continue;
+                       }
+                       if (args[argidx] == "-run" && argidx+1 < args.size()) {
+                               size_t pos = args[argidx+1].find(':');
+                               if (pos == std::string::npos)
+                                       break;
+                               run_from = args[++argidx].substr(0, pos);
+                               run_to = args[argidx].substr(pos+1);
+                               continue;
+                       }
+                       if (args[argidx] == "-retime") {
+                               retime = true;
+                               continue;
+                       }
+                       break;
+               }
+               extra_args(args, argidx, design);
+
+               if (!design->full_selection())
+                       log_cmd_error("This comannd only operates on fully selected designs!\n");
+
+               log_header(design, "Executing SYNTH_GOWIN pass.\n");
+               log_push();
+
+               run_script(design, run_from, run_to);
+
+               log_pop();
+       }
+
+       virtual void script() YS_OVERRIDE
+       {
+               if (check_label("begin"))
+               {
+                       run("read_verilog -lib +/gowin/cells_sim.v");
+                       run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
+               }
+
+               if (check_label("flatten"))
+               {
+                       run("proc");
+                       run("flatten");
+                       run("tribuf -logic");
+                       run("deminout");
+               }
+
+               if (check_label("coarse"))
+               {
+                       run("synth -run coarse");
+               }
+
+               if (check_label("fine"))
+               {
+                       run("opt -fast -mux_undef -undriven -fine");
+                       run("memory_map");
+                       run("opt -undriven -fine");
+                       run("techmap");
+                       run("clean -purge");
+                       run("splitnets -ports");
+                       run("setundef -undriven -zero");
+                       if (retime || help_mode)
+                               run("abc -dff", "(only if -retime)");
+               }
+
+               if (check_label("map_luts"))
+               {
+                       run("abc -lut 4");
+                       run("clean");
+               }
+
+               if (check_label("map_cells"))
+               {
+                       run("techmap -map +/gowin/cells_map.v");
+                       run("hilomap -hicell VCC V -locell GND G");
+                       run("iopadmap -inpad IBUF O:I -outpad OBUF I:O");
+                       run("clean -purge");
+               }
+
+               if (check_label("check"))
+               {
+                       run("hierarchy -check");
+                       run("stat");
+                       run("check -noinit");
+               }
+
+               if (check_label("vout"))
+               {
+                       if (!vout_file.empty() || help_mode)
+                               run(stringf("write_verilog -attr2comment -defparam -renameprefix gen %s",
+                                               help_mode ? "<file-name>" : vout_file.c_str()));
+               }
+       }
+} SynthGowinPass;
+
+PRIVATE_NAMESPACE_END