MIPS/opcodes: Add MFCR and MTCR data dependencies

	* mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and
	"mtcr".

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 1b3f05d2762037d9f62dae401ecdb4b9e4232d98..230ed3bae4eedafd9b51a1fbbd91b04fda8b9535 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2013-11-15  Maciej W. Rozycki  <macro@codesourcery.com>
+
+       * mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and
+       "mtcr".
+
 2013-11-11  Catherine Moore  <clm@codesourcery.com>
 
        * mips-dis.c (print_insn_mips): Use

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 43fab35d50dd8f544ba45e676062eec3040f798e..9fb2d9530870a7a487a46a76c289b2a8476fd36d 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -1317,7 +1317,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mflo",               "d,9",          0x00000012, 0xff9f07ff, WR_1|RD_LO,             0,              0,              D32,    0 },
 {"mflo1",              "d",            0x70000012, 0xffff07ff, WR_1|RD_LO,             0,              EE,             0,      0 },
 {"mflhxu",             "d",            0x00000052, 0xffff07ff, WR_1|MOD_HILO,          0,              0,              SMT,    0 },
-{"mfcr",               "t,s",          0x70000018, 0xfc00ffff, WR_1,                   0,              XLR,            0,      0 },
+{"mfcr",               "t,s",          0x70000018, 0xfc00ffff, WR_1|RD_2,              0,              XLR,            0,      0 },
 {"mfsa",               "d",            0x00000028, 0xffff07ff, WR_1,                   0,              EE,             0,      0 },
 {"min.ob",             "X,Y,Q",        0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"min.ob",             "D,S,Q",        0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
@@ -1410,7 +1410,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtlo",               "s,7",          0x00000013, 0xfc1fe7ff, RD_1|WR_LO,             0,              0,              D32,    0 },
 {"mtlo1",              "s",            0x70000013, 0xfc1fffff, RD_1|WR_LO,             0,              EE,             0,      0 },
 {"mtlhx",              "s",            0x00000053, 0xfc1fffff, RD_1|MOD_HILO,          0,              0,              SMT,    0 },
-{"mtcr",               "t,s",          0x70000019, 0xfc00ffff, RD_1,                   0,              XLR,            0,      0 },
+{"mtcr",               "t,s",          0x70000019, 0xfc00ffff, RD_1|RD_2,              0,              XLR,            0,      0 },
 {"mtm0",               "s",            0x70000008, 0xfc1fffff, RD_1,                   0,              IOCT,           0,      0 },
 {"mtm1",               "s",            0x7000000c, 0xfc1fffff, RD_1,                   0,              IOCT,           0,      0 },
 {"mtm2",               "s",            0x7000000d, 0xfc1fffff, RD_1,                   0,              IOCT,           0,      0 },