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diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 1e293462e0af1fcc5db578ffbf1e82435e372524..232f1d40582e3d58c1251010a08505505d36131e 100644 (file)
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -161,6 +161,8 @@ there is no separate Vector register file*: it's all the same instruction,
 on the standard register file, just with a loop.  Scalar happens to set
 that loop size to one.
 
+Also, it is important to note from the above that, strictly speaking, Simple-V is not really a Vectorisation scheme at all: it is more of a hardware instruction "Compression scheme", allowing as it does for what would normally require multiple sequential instructions to be replaced with one (and aome tags).  This is where the rule that Program Order must be preserved in Sub-OC execution derives from.  However in other ways, which will emerge below, the "tagging" concept presents an opportunity to include features definitely not common outside of Vector ISAs, and in that regard it's definitely a xlass of Vectorisation.
+
 ## Register "tagging"
 
 As an aside: in [[sv/svp64]] the encoding which allows SV to both extend the range beyond r0-r31 and to determine whether it is a scalar or vector is encoded in two to three bits, depending on the instruction.