i965/vs: Fix texelFetchOffset() on pre-Gen7.

Commit 4650aea7a536ddce120576fadb91845076e8e37a fixed texelFetchOffset()
on Ivybridge, but didn't update the Ironlake/Sandybridge code.

+18 piglits on Sandybridge.

NOTE: This and 4650aea7a536ddce are both candidates for stable branches.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index c2b103331aa5f04e61a92e52228a9d40c9f37ff8..cfffef44605fe74fc214144e13b7d35d3ff14870 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -1838,7 +1838,7 @@ vec4_visitor::visit(ir_texture *ir)
    inst->dst = dst_reg(this, ir->type);
    inst->shadow_compare = ir->shadow_comparitor != NULL;
 
-   if (ir->offset != NULL && !(intel->gen >= 7 && ir->op == ir_txf))
+   if (ir->offset != NULL && ir->op != ir_txf)
       inst->texture_offset = brw_texture_offset(ir->offset->as_constant());
 
    /* MRF for the first parameter */
@@ -1859,7 +1859,7 @@ vec4_visitor::visit(ir_texture *ir)
         zero_mask |= (1 << i);
 
       ir->coordinate->accept(this);
-      if (ir->offset && intel->gen >= 7 && ir->op == ir_txf) {
+      if (ir->offset && ir->op == ir_txf) {
         /* It appears that the ld instruction used for txf does its
          * address bounds check before adding in the offset.  To work
          * around this, just add the integer offset to the integer