(no commit message)

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 7582962632d936912ca8c8eb7af2d295217458be..6c0646eb11221dcf1a4b912c9d5d8c915783598c 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -208,6 +208,7 @@ Standard PowerISA floating-point and VSX registers are aliased to some of the SV
 When vectorized, the CR inputs/outputs are read/written to 4-bit CR fields
 starting from CR6 and incrementing from there. If CR63 is reached, the next CR
 field used wraps around to CR0, then incrementing from there.
+(see [[discussion]].  an alternative scheme is described there)
 
 CR6 was chosen to balance avoiding needing to save CR2-CR4 (which are
 callee-saved) just to use SV vectors with VL <= 61 as well as having the first