add yosys-nowidelut command-option

diff --git a/README.txt b/README.txt
index 56adddf762d1ef5673a41e3fca87acd9263c9a34..3d008ebf7092cfa3d0f73115338064932c0df034 100644 (file)
--- a/README.txt
+++ b/README.txt
@@ -11,5 +11,5 @@ terminal 2: openocd -f openocd.cfg -c init -c 'svf idcode_test2.svf'
 
 same thing: first build libresoc.v and copy it to the libresoc/ directory
 
-./versa_ecp5.py --sys-clk-freq=55e6 --build
+./versa_ecp5.py --sys-clk-freq=55e6 --build --yosys-nowidelut
 ./versa_ecp5.py --sys-clk-freq=55e6 --load

diff --git a/versa_ecp5.py b/versa_ecp5.py
index 638f5640b41e77940df96031512dedcbb3923273..e960d9689eb94a55ce6b3896f85e731d3d98b0a6 100755 (executable)
--- a/versa_ecp5.py
+++ b/versa_ecp5.py
@@ -6,6 +6,7 @@ import sys
 
 import litex_boards.targets.versa_ecp5 as versa_ecp5
 import litex_boards.targets.ulx3s as ulx3s
+from litex.build.lattice.trellis import trellis_args, trellis_argdict
 
 from litex.soc.integration.soc_sdram import (soc_sdram_args,
                                              soc_sdram_argdict)
@@ -122,8 +123,10 @@ def main():
     parser.add_argument("--fpga", default="versa_ecp5", help="FPGA target " \
                         "to build for/load to")
     parser.add_argument("--load-from", default=None, help="svf to load, disables build")
+    parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
 
     builder_args(parser)
+    trellis_args(parser)
     soc_sdram_args(parser)
     args = parser.parse_args()
 
@@ -141,6 +144,8 @@ def main():
 
     if args.load_from == None:
         builder = Builder(soc, **builder_argdict(args))
+        builder_kargs = trellis_argdict(args) \
+                if args.toolchain == "trellis" else {}
         builder.build(run=args.build)
 
         if args.load: