Add counter-enable registers

diff --git a/riscv/encoding.h b/riscv/encoding.h
index 112723429eb6fc892fa14067faeab52cef9b2cff..9189fde43d36ce94bef3201f4a629c43a82c536d 100644 (file)
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -647,6 +647,9 @@
 #define CSR_SIP 0x144
 #define CSR_SPTBR 0x180
 #define CSR_SASID 0x181
+#define CSR_SCYCLE 0xd00
+#define CSR_STIME 0xd01
+#define CSR_SINSTRET 0xd02
 #define CSR_MSTATUS 0x300
 #define CSR_MEDELEG 0x302
 #define CSR_MIDELEG 0x303
@@ -659,6 +662,14 @@
 #define CSR_MBADADDR 0x343
 #define CSR_MIP 0x344
 #define CSR_MIPI 0x345
+#define CSR_MUCOUNTEREN 0x310
+#define CSR_MSCOUNTEREN 0x311
+#define CSR_MUCYCLE_DELTA 0x700
+#define CSR_MUTIME_DELTA 0x701
+#define CSR_MUINSTRET_DELTA 0x702
+#define CSR_MSCYCLE_DELTA 0x704
+#define CSR_MSTIME_DELTA 0x705
+#define CSR_MSINSTRET_DELTA 0x706
 #define CSR_MCYCLE 0xf00
 #define CSR_MTIME 0xf01
 #define CSR_MINSTRET 0xf02
@@ -675,6 +686,12 @@
 #define CSR_TIMEH 0xc81
 #define CSR_INSTRETH 0xc82
 #define CSR_MTIMECMPH 0x361
+#define CSR_MUCYCLE_DELTAH 0x780
+#define CSR_MUTIME_DELTAH 0x781
+#define CSR_MUINSTRET_DELTAH 0x782
+#define CSR_MSCYCLE_DELTAH 0x784
+#define CSR_MSTIME_DELTAH 0x785
+#define CSR_MSINSTRET_DELTAH 0x786
 #define CSR_MCYCLEH 0xf80
 #define CSR_MTIMEH 0xf81
 #define CSR_MINSTRETH 0xf82
@@ -952,6 +969,9 @@ DECLARE_CSR(sbadaddr, CSR_SBADADDR)
 DECLARE_CSR(sip, CSR_SIP)
 DECLARE_CSR(sptbr, CSR_SPTBR)
 DECLARE_CSR(sasid, CSR_SASID)
+DECLARE_CSR(scycle, CSR_SCYCLE)
+DECLARE_CSR(stime, CSR_STIME)
+DECLARE_CSR(sinstret, CSR_SINSTRET)
 DECLARE_CSR(mstatus, CSR_MSTATUS)
 DECLARE_CSR(medeleg, CSR_MEDELEG)
 DECLARE_CSR(mideleg, CSR_MIDELEG)
@@ -964,6 +984,14 @@ DECLARE_CSR(mcause, CSR_MCAUSE)
 DECLARE_CSR(mbadaddr, CSR_MBADADDR)
 DECLARE_CSR(mip, CSR_MIP)
 DECLARE_CSR(mipi, CSR_MIPI)
+DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
+DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
+DECLARE_CSR(mucycle_delta, CSR_MUCYCLE_DELTA)
+DECLARE_CSR(mutime_delta, CSR_MUTIME_DELTA)
+DECLARE_CSR(muinstret_delta, CSR_MUINSTRET_DELTA)
+DECLARE_CSR(mscycle_delta, CSR_MSCYCLE_DELTA)
+DECLARE_CSR(mstime_delta, CSR_MSTIME_DELTA)
+DECLARE_CSR(msinstret_delta, CSR_MSINSTRET_DELTA)
 DECLARE_CSR(mcycle, CSR_MCYCLE)
 DECLARE_CSR(mtime, CSR_MTIME)
 DECLARE_CSR(minstret, CSR_MINSTRET)
@@ -980,6 +1008,12 @@ DECLARE_CSR(cycleh, CSR_CYCLEH)
 DECLARE_CSR(timeh, CSR_TIMEH)
 DECLARE_CSR(instreth, CSR_INSTRETH)
 DECLARE_CSR(mtimecmph, CSR_MTIMECMPH)
+DECLARE_CSR(mucycle_deltah, CSR_MUCYCLE_DELTAH)
+DECLARE_CSR(mutime_deltah, CSR_MUTIME_DELTAH)
+DECLARE_CSR(muinstret_deltah, CSR_MUINSTRET_DELTAH)
+DECLARE_CSR(mscycle_deltah, CSR_MSCYCLE_DELTAH)
+DECLARE_CSR(mstime_deltah, CSR_MSTIME_DELTAH)
+DECLARE_CSR(msinstret_deltah, CSR_MSINSTRET_DELTAH)
 DECLARE_CSR(mcycleh, CSR_MCYCLEH)
 DECLARE_CSR(mtimeh, CSR_MTIMEH)
 DECLARE_CSR(minstreth, CSR_MINSTRETH)

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 34735f95fce0dc838d95b9ec6018248815473943..ed7c02ffc710b1e4b3c5643081180f440b11ca0e 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -332,6 +332,12 @@ void processor_t::set_csr(int which, reg_t val)
       state.medeleg = (state.medeleg & ~mask) | (val & mask);
       break;
     }
+    case CSR_MUCOUNTEREN:
+      state.mucounteren = val & 7;
+      break;
+    case CSR_MSCOUNTEREN:
+      state.mscounteren = val & 7;
+      break;
     case CSR_SSTATUS: {
       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
                  | SSTATUS_XS | SSTATUS_PUM;
@@ -392,6 +398,32 @@ reg_t processor_t::get_csr(int which)
       if (!supports_extension('F'))
         break;
       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
+    case CSR_TIME:
+    case CSR_INSTRET:
+    case CSR_CYCLE:
+      if ((state.mucounteren >> (which & (xlen-1))) & 1)
+        return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
+      break;
+    case CSR_STIME:
+    case CSR_SINSTRET:
+    case CSR_SCYCLE:
+      if ((state.mscounteren >> (which & (xlen-1))) & 1)
+        return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
+      break;
+    case CSR_MUCOUNTEREN: return state.mucounteren;
+    case CSR_MSCOUNTEREN: return state.mscounteren;
+    case CSR_MUCYCLE_DELTA: return 0;
+    case CSR_MUTIME_DELTA: return 0;
+    case CSR_MUINSTRET_DELTA: return 0;
+    case CSR_MSCYCLE_DELTA: return 0;
+    case CSR_MSTIME_DELTA: return 0;
+    case CSR_MSINSTRET_DELTA: return 0;
+    case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
+    case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
+    case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
+    case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
+    case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
+    case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
     case CSR_MTIME: return sim->rtc;
     case CSR_MCYCLE: return state.minstret;
     case CSR_MINSTRET: return state.minstret;

diff --git a/riscv/processor.h b/riscv/processor.h
index 7d71b315f042472c3b1ca4b52e711ad2ed0aa574..e342ab07170d4c09398180c9af174ba9b8e67104 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -53,6 +53,8 @@ struct state_t
   reg_t mip;
   reg_t medeleg;
   reg_t mideleg;
+  reg_t mucounteren;
+  reg_t mscounteren;
   reg_t sepc;
   reg_t sbadaddr;
   reg_t sscratch;