synth_gatemate Revert cascade A/B port mixup

diff --git a/techlibs/gatemate/brams_map.v b/techlibs/gatemate/brams_map.v
index 2e5e1a5ccf43252f88b18f7f708bf87a511d03a4..f36f05212d3f0b3425283241311794d1ffd4b6f1 100644 (file)
--- a/techlibs/gatemate/brams_map.v
+++ b/techlibs/gatemate/brams_map.v
@@ -450,7 +450,7 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
                        `undef INIT_UPPER\r
                        .LOC("UNPLACED"),\r
                        .CAS("UPPER"),\r
-                       .A_RD_WIDTH(CFG_DBITS), .B_RD_WIDTH(0),\r
+                       .A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),\r
                        .A_WR_WIDTH(CFG_DBITS), .B_WR_WIDTH(0),\r
                        .RAM_MODE("TDP"),\r
                        .A_WR_MODE("NO_CHANGE"), .B_WR_MODE("NO_CHANGE"),\r
@@ -462,8 +462,8 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
                ) upper_cell (\r
                        .A_CI(A_CAS),\r
                        .B_CI(B_CAS),\r
-                       .A_DO(B1DATA),\r
-                       .B_DO(A_UP_DO),\r
+                       .A_DO(A_UP_DO),\r
+                       .B_DO(B1DATA),\r
                        .A_ECC_1B_ERR(A_ECC_1B_ERR),\r
                        .B_ECC_1B_ERR(B_ECC_1B_ERR),\r
                        .A_ECC_2B_ERR(A_ECC_2B_ERR),\r
@@ -488,7 +488,7 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
                        `undef INIT_LOWER\r
                        .LOC("UNPLACED"),\r
                        .CAS("LOWER"),\r
-                       .A_RD_WIDTH(CFG_DBITS), .B_RD_WIDTH(0),\r
+                       .A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),\r
                        .A_WR_WIDTH(CFG_DBITS), .B_WR_WIDTH(0),\r
                        .RAM_MODE("TDP"),\r
                        .A_WR_MODE("NO_CHANGE"), .B_WR_MODE("NO_CHANGE"),\r

diff --git a/techlibs/gatemate/cells_sim.v b/techlibs/gatemate/cells_sim.v
index 1c7e40680abeb24625d0aa06dc212a085af3fd0b..1de3d1c7a6d454d16a8048c07c4e29bd637337df 100644 (file)
--- a/techlibs/gatemate/cells_sim.v
+++ b/techlibs/gatemate/cells_sim.v
@@ -1035,14 +1035,6 @@ module CC_BRAM_40K (
                        $display("ERROR: Port B width of 80 bits is only supported in SDP mode.");\r
                        $finish();\r
                end\r
-               if (((CAS == "UPPER") || (CAS == "LOWER")) && (WIDTH_MODE_A > 1)) begin\r
-                       $display("ERROR: Port A cascade mode only supported in 1 bit mode.");\r
-                       $finish();\r
-               end\r
-               if (((CAS == "UPPER") || (CAS == "LOWER")) && (WIDTH_MODE_B > 1)) begin\r
-                       $display("ERROR: Port B cascade mode only supported in 1 bit mode.");\r
-                       $finish();\r
-               end\r
                if ((WIDTH_MODE_A != 80) && (WIDTH_MODE_A != 40) && (WIDTH_MODE_A != 20) && (WIDTH_MODE_A != 10) &&\r
                        (WIDTH_MODE_A != 5)  && (WIDTH_MODE_A != 2)  && (WIDTH_MODE_A != 1) && (WIDTH_MODE_A != 0)) begin\r
                        $display("ERROR: Illegal %s Port A width configuration %d.", RAM_MODE, WIDTH_MODE_A);\r