re PR target/83467 (ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find...
authorUros Bizjak <uros@gcc.gnu.org>
Thu, 21 Dec 2017 19:00:28 +0000 (20:00 +0100)
committerUros Bizjak <uros@gcc.gnu.org>
Thu, 21 Dec 2017 19:00:28 +0000 (20:00 +0100)
PR target/83467
* config/i386/i386.md (*ashl<mode>3_mask): Add operand
constraints to operand 2.
(*ashl<mode>3_mask_1): Ditto.
(*<shift_insn><mode>3_mask): Ditto.
(*<shift_insn><mode>3_mask_1): Ditto.
(*<rotate_insn><mode>3_mask): Ditto.
(*<rotate_insn><mode>3_mask_1): Ditto.

testsuite/ChangeLog:

PR target/83467
* gcc.target/i386/pr83467-1.c: New test.
* gcc.target/i386/pr83467-2.c: Ditto.

From-SVN: r255949

gcc/ChangeLog
gcc/config/i386/i386.md
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/i386/pr83467-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/i386/pr83467-2.c [new file with mode: 0644]

index 7200561a332072525c3815c426b773985044365b..7f9d16c08d35a27ceefabcbcf81bfa47aa9d84be 100644 (file)
@@ -1,9 +1,19 @@
-2017-12-21  Alexandre Oliva <aoliva@redhat.com>
+2017-12-21  Uros Bizjak  <ubizjak@gmail.com>
 
-       * reorg.c (make_return_insns): Reemit each insn with its own
-       location.
+       PR target/83467
+       * config/i386/i386.md (*ashl<mode>3_mask): Add operand
+       constraints to operand 2.
+       (*ashl<mode>3_mask_1): Ditto.
+       (*<shift_insn><mode>3_mask): Ditto.
+       (*<shift_insn><mode>3_mask_1): Ditto.
+       (*<rotate_insn><mode>3_mask): Ditto.
+       (*<rotate_insn><mode>3_mask_1): Ditto.
 
-2017-12-21  Alexandre Oliva <aoliva@redhat.com>
+2017-12-21  Alexandre Oliva  <aoliva@redhat.com>
+
+       * reorg.c (make_return_insns): Reemit each insn with its own location.
+
+2017-12-21  Alexandre Oliva  <aoliva@redhat.com>
 
        PR debug/83419
        * c-family/c-semantics.c (pop_stmt_list): Propagate side
        (expand_builtin_strcmp): Call maybe_warn_nonstring_arg.
        (expand_builtin_strncmp): Same.
 
-2017-12-20  Alexandre Oliva <aoliva@redhat.com>
+2017-12-20  Alexandre Oliva  <aoliva@redhat.com>
 
        PR bootstrap/83396
        * cfgexpand.c (label_rtx_for_bb): Revert SFN changes that
        poly_int64.  Use strip_offset_and_add to handle (plus X (const)).
 
 2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
-            Alan Hayward  <alan.hayward@arm.com>
+           Alan Hayward  <alan.hayward@arm.com>
            David Sherwood  <david.sherwood@arm.com>
 
        * rtl.h (reg_attrs::offset): Change from HOST_WIDE_INT to poly_int64.
        of a PARALLEL.
 
 2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
-            Alan Hayward  <alan.hayward@arm.com>
+           Alan Hayward  <alan.hayward@arm.com>
            David Sherwood  <david.sherwood@arm.com>
 
        * target.def (truly_noop_truncation): Take poly_uint64s instead of
 2017-12-20  Tom de Vries  <tom@codesourcery.com>
 
        PR middle-end/83423
-       * config/i386/i386.c (ix86_static_chain): Move DECL_STATIC_CHAIN test ...
+       * config/i386/i386.c (ix86_static_chain): Move
+       DECL_STATIC_CHAIN test ...
        * calls.c (rtx_for_static_chain): ... here.  New function.
        * calls.h (rtx_for_static_chain): Declare.
        * builtins.c (expand_builtin_setjmp_receiver): Use rtx_for_static_chain
        character load case, if get_stridx on MEM_REF's operand doesn't
        look usable, retry with get_addr_stridx.
 
-2017-12-19  Alexandre Oliva <aoliva@redhat.com>
+2017-12-19  Alexandre Oliva  <aoliva@redhat.com>
 
        PR debug/83422
        * var-tracking.c (vt_debug_insns_local): Do not drop markers.
        * sched-rgn.c (sched_rgn_init): Likewise.
        * diagnostic-show-locus.c (layout::show_ruler): Likewise.
        * combine.c (find_split_point, simplify_if_then_else, force_to_mode,
-       if_then_else_cond, simplify_shift_const_1, simplify_comparison): Likewise.
+       if_then_else_cond, simplify_shift_const_1, simplify_comparison):
+       Likewise.
        * explow.c (eliminate_constant_term): Likewise.
        * final.c (leaf_renumber_regs_insn): Likewise.
        * cfgrtl.c (print_rtl_with_bb): Likewise.
 
        PR c++/83489
        * config/i386/i386.c (init_cumulative_args): Don't check TYPE_EMPTY_P
-       on an error node.                                                    
+       on an error node.
 
 2017-12-19  Claudiu Zissulescu  <claziss@synopsys.com>
 
        * doc/extend.texi (x86 Function Attributes): Reformat nocf_check
        example to avoid overfull hbox.
        * doc/invoke.texi (Option Summary): Add missing @gol.
-       (C++ Dialect Options): Reformat -Wnoexcept-type example to avoid 
+       (C++ Dialect Options): Reformat -Wnoexcept-type example to avoid
        overfull hbox.
-       
+
 2017-12-17  Sandra Loosemore  <sandra@codesourcery.com>
            Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
        optimizing for size.  Don't pessimize blocks which will be
        copied, but all the statements will be dead.
 
-2017-12-15  Alexandre Oliva <aoliva@redhat.com>
+2017-12-15  Alexandre Oliva  <aoliva@redhat.com>
 
        PR tree-optimization/81165
        * tree-ssa-threadupdate.c (uses_in_bb): New.
        (estimate_threading_killed_stmts): New.
        * tree-ssa-threadupdate.h (estimate_threading_killed_stmts): Prototype.
-       * tree-ssa-threadedge.c 
+       * tree-ssa-threadedge.c
        (record_temporary_equivalences_from_stmts_at_dest): Expand limit
        when its hit.
 
 2017-12-15  Julia Koval  <julia.koval@intel.com>
 
        * config/i386/i386-builtin.def (__builtin_ia32_vaesenclast_v16qi,
-       __builtin_ia32_vaesenclast_v32qi, __builtin_ia32_vaesenclast_v64qi): New.
+       __builtin_ia32_vaesenclast_v32qi, __builtin_ia32_vaesenclast_v64qi):
+       New.
        * config/i386/sse.md (vaesenclast_<mode>): New pattern.
        * config/i386/vaesintrin.h (_mm256_aesenclast_epi128,
        _mm512_aesenclast_epi128, _mm_aesenclast_epi128): New intrinsics.
 2017-12-15  Julia Koval  <julia.koval@intel.com>
 
        * config/i386/i386-builtin.def (__builtin_ia32_vaesdeclast_v16qi,
-       __builtin_ia32_vaesdeclast_v32qi, __builtin_ia32_vaesdeclast_v64qi): New.
+       __builtin_ia32_vaesdeclast_v32qi, __builtin_ia32_vaesdeclast_v64qi):
+       New.
        * config/i386/sse.md (vaesdeclast_<mode>): New pattern.
        * config/i386/vaesintrin.h (_mm256_aesdeclast_epi128,
        _mm512_aesdeclast_epi128, _mm_aesdeclast_epi128): New intrinsics.
        PR bootstrap/83396
        * reload1.c (emit_input_reload_insns): Skip debug markers.
 
-2017-12-14  Alexandre Oliva <aoliva@redhat.com>
+2017-12-14  Alexandre Oliva  <aoliva@redhat.com>
 
        * config/i386/i386.c (rest_of_insert_endbranch): Use call loc
        for its nop_endbr.
 
        PR tree-optimization/83418
        * vr-values.c (vr_values::extract_range_for_var_from_comparison_expr):
-       Instead of asserting we don't get unfolded comparisons deal with
-       them.
+       Instead of asserting we don't get unfolded comparisons deal with them.
 
 2017-12-14  Jakub Jelinek  <jakub@redhat.com>
 
        (ASSERT_MAYBE_NE_AT): New macros.
 
 2017-12-13  Eric Botcazou  <ebotcazou@adacore.com>
-            Dominik Vogt  <vogt@linux.vnet.ibm.com>
+           Dominik Vogt  <vogt@linux.vnet.ibm.com>
 
        PR middle-end/78468
        * emit-rtl.c (init_emit): Remove ??? comment.
        * config/rs6000/ppc-auxv.h (PPC_FEATURE2_HTM_NO_SUSPEND): New define.
        * config/rs6000/rs6000.c (cpu_supports_info): Use it.
 
-2017-12-13  Alexandre Oliva <aoliva@redhat.com>
+2017-12-13  Alexandre Oliva  <aoliva@redhat.com>
 
        PR bootstrap/83396
        * reload1.c (eliminate_regs_in_insn): Skip debug markers.
index c6ab79a42acf792023a5dfdcf24d8c41c43ecc5c..59d9245234fd4cf0d79fab2edbe98d035cdd0b38 100644 (file)
          (match_operand:SWI48 1 "nonimmediate_operand")
          (subreg:QI
            (and:SI
-             (match_operand:SI 2 "register_operand")
+             (match_operand:SI 2 "register_operand" "c,r")
              (match_operand:SI 3 "const_int_operand")) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands)
           (ashift:SWI48 (match_dup 1)
                         (match_dup 2)))
       (clobber (reg:CC FLAGS_REG))])]
-  "operands[2] = gen_lowpart (QImode, operands[2]);")
+  "operands[2] = gen_lowpart (QImode, operands[2]);"
+  [(set_attr "isa" "*,bmi2")])
 
 (define_insn_and_split "*ashl<mode>3_mask_1"
   [(set (match_operand:SWI48 0 "nonimmediate_operand")
        (ashift:SWI48
          (match_operand:SWI48 1 "nonimmediate_operand")
          (and:QI
-           (match_operand:QI 2 "register_operand")
+           (match_operand:QI 2 "register_operand" "c,r")
            (match_operand:QI 3 "const_int_operand"))))
    (clobber (reg:CC FLAGS_REG))]
   "ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands)
      [(set (match_dup 0)
           (ashift:SWI48 (match_dup 1)
                         (match_dup 2)))
-      (clobber (reg:CC FLAGS_REG))])])
+      (clobber (reg:CC FLAGS_REG))])]
+  ""
+  [(set_attr "isa" "*,bmi2")])
 
 (define_insn "*bmi2_ashl<mode>3_1"
   [(set (match_operand:SWI48 0 "register_operand" "=r")
          (match_operand:SWI48 1 "nonimmediate_operand")
          (subreg:QI
            (and:SI
-             (match_operand:SI 2 "register_operand")
+             (match_operand:SI 2 "register_operand" "c,r")
              (match_operand:SI 3 "const_int_operand")) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
           (any_shiftrt:SWI48 (match_dup 1)
                              (match_dup 2)))
       (clobber (reg:CC FLAGS_REG))])]
-  "operands[2] = gen_lowpart (QImode, operands[2]);")
+  "operands[2] = gen_lowpart (QImode, operands[2]);"
+  [(set_attr "isa" "*,bmi2")])
 
 (define_insn_and_split "*<shift_insn><mode>3_mask_1"
   [(set (match_operand:SWI48 0 "nonimmediate_operand")
        (any_shiftrt:SWI48
          (match_operand:SWI48 1 "nonimmediate_operand")
          (and:QI
-           (match_operand:QI 2 "register_operand")
+           (match_operand:QI 2 "register_operand" "c,r")
            (match_operand:QI 3 "const_int_operand"))))
    (clobber (reg:CC FLAGS_REG))]
   "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
      [(set (match_dup 0)
           (any_shiftrt:SWI48 (match_dup 1)
                              (match_dup 2)))
-      (clobber (reg:CC FLAGS_REG))])])
+      (clobber (reg:CC FLAGS_REG))])]
+  ""
+  [(set_attr "isa" "*,bmi2")])
 
 (define_insn_and_split "*<shift_insn><mode>3_doubleword"
   [(set (match_operand:DWI 0 "register_operand" "=&r")
          (match_operand:SWI48 1 "nonimmediate_operand")
          (subreg:QI
            (and:SI
-             (match_operand:SI 2 "register_operand")
+             (match_operand:SI 2 "register_operand" "c")
              (match_operand:SI 3 "const_int_operand")) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
        (any_rotate:SWI48
          (match_operand:SWI48 1 "nonimmediate_operand")
          (and:QI
-           (match_operand:QI 2 "register_operand")
+           (match_operand:QI 2 "register_operand" "c")
            (match_operand:QI 3 "const_int_operand"))))
    (clobber (reg:CC FLAGS_REG))]
   "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
index 8cc163adac0e0fb3c358eaa5421b9c93e6a91443..2696f5e86555bdcf897559f66bd7b51e09ad191b 100644 (file)
@@ -1,4 +1,10 @@
-2017-12-21  Alexandre Oliva <aoliva@redhat.com>
+2017-12-21  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/83467
+       * gcc.target/i386/pr83467-1.c: New test.
+       * gcc.target/i386/pr83467-2.c: Ditto.
+
+2017-12-21  Alexandre Oliva  <aoliva@redhat.com>
 
        PR debug/83419
        * gcc.dg/pr83419.c: New.
        * gcc.dg/Wstringop-overflow.c: New test.
        * gcc/testsuite/c-c++-common/Warray-bounds-3.c: Adjust.
 
-2017-12-19  Alexandre Oliva <aoliva@redhat.com>
+2017-12-19  Alexandre Oliva  <aoliva@redhat.com>
 
        PR debug/83422
        * gcc.dg/pr83422.c: New.
diff --git a/gcc/testsuite/gcc.target/i386/pr83467-1.c b/gcc/testsuite/gcc.target/i386/pr83467-1.c
new file mode 100644 (file)
index 0000000..b5cf17e
--- /dev/null
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -flive-range-shrinkage -m8bit-idiv" } */
+/* { dg-require-effective-target int128 } */
+
+unsigned a;
+
+__int128
+b (unsigned c, short d, int e, long f, unsigned __int128 g, char h,
+   int i, __int128 j)
+{
+  j %= 5;
+  c *= i;
+  e = e >> (g & 31);
+  h &= e /= d;
+  g <<= 0 <= 0;
+  g &= h < j;
+  return c + d + f + g + h + i + a + j;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr83467-2.c b/gcc/testsuite/gcc.target/i386/pr83467-2.c
new file mode 100644 (file)
index 0000000..1b424fe
--- /dev/null
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -flive-range-shrinkage" } */
+/* { dg-require-effective-target int128 } */
+
+int
+a (int b, short c, int d, long e, __int128 f, short g, long h, __int128 i)
+{
+  d <<= f & 31;
+  f >>= 127;
+  g *= d > c;
+  f >>= g;
+  return b + e + f + h + i;
+}