targets: add Lattice ECP3 versa

diff --git a/targets/versa.py b/targets/versa.py
new file mode 100644 (file)
index 0000000..c0fe471
--- /dev/null
+++ b/targets/versa.py
@@ -0,0 +1,17 @@
+from migen.fhdl.std import *
+from migen.bus import wishbone
+from migen.genlib.io import CRG
+
+from misoclib.soc import SoC
+
+class BaseSoC(SoC):
+       default_platform = "versa"
+       def __init__(self, platform, **kwargs):
+               SoC.__init__(self, platform,
+                       clk_freq=100*1000000,
+                       with_rom=True,
+                       **kwargs)
+               self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("rst_n"))
+               self.comb += platform.request("user_led", 0).eq(ResetSignal())
+
+default_subtarget = BaseSoC