12 + /* flush_vgt_streamout */
6 + /* set_streamout_enable */
util_bitcount(buffer_en) * 7 + /* SET_CONTEXT_REG */
+ (ctx->chip_class == R700 ? util_bitcount(buffer_en) * 5 : 0) + /* STRMOUT_BASE_UPDATE */
util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 + /* STRMOUT_BUFFER_UPDATE */
util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 + /* STRMOUT_BUFFER_UPDATE */
(ctx->family > CHIP_R600 && ctx->family < CHIP_RV770 ? 2 : 0) + /* SURFACE_BASE_UPDATE */
r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer),
RADEON_USAGE_WRITE);
+ /* R7xx requires this packet after updating BUFFER_BASE.
+ * Without this, R7xx locks up. */
+ if (ctx->chip_class == R700) {
+ cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0);
+ cs->buf[cs->cdw++] = i;
+ cs->buf[cs->cdw++] = va >> 8;
+
+ cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
+ cs->buf[cs->cdw++] =
+ r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer),
+ RADEON_USAGE_WRITE);
+ }
+
if (ctx->streamout_append_bitmask & (1 << i)) {
va = r600_resource_va(&ctx->screen->screen,
(void*)t[i]->filled_size);
#define PKT3_SET_RESOURCE 0x6D
#define PKT3_SET_SAMPLER 0x6E
#define PKT3_SET_CTL_CONST 0x6F
+#define PKT3_STRMOUT_BASE_UPDATE 0x72
#define PKT3_SURFACE_BASE_UPDATE 0x73
#define SURFACE_BASE_UPDATE_DEPTH (1 << 0)
#define SURFACE_BASE_UPDATE_COLOR(x) (2 << (x))