platforms: add -w option to bitgen_opt

diff --git a/mibuild/platforms/lx9_microboard.py b/mibuild/platforms/lx9_microboard.py
index e259e4eb3c8d88410092be6df3e752865b25ef49..08d61249e47d2a1c67ed75155eead1f6f80efbaf 100644 (file)
--- a/mibuild/platforms/lx9_microboard.py
+++ b/mibuild/platforms/lx9_microboard.py
@@ -103,7 +103,7 @@ _io = [
 
 
 class Platform(XilinxISEPlatform):
-       bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -g SPI_buswidth:4"
+       bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
        ise_commands = """
 promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit
 """

diff --git a/mibuild/platforms/usrp_b100.py b/mibuild/platforms/usrp_b100.py
index 977025559d4ee7f0d09b597b9f86e0ac924655bc..720bed43855552ca0c0a0c0107b7651fc1283200 100644 (file)
--- a/mibuild/platforms/usrp_b100.py
+++ b/mibuild/platforms/usrp_b100.py
@@ -114,7 +114,7 @@ _io = [
 
 
 class Platform(XilinxISEPlatform):
-       bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -g UnusedPin:PullUp"
+       bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"
        def __init__(self):
                XilinxISEPlatform.__init__(self, "xc3s1400a-ft256-4", _io,
                        lambda p: CRG_DS(p, "clk64", "reset_n", rst_invert=True))