migen/test: start unittests

diff --git a/migen/test/__init__.py b/migen/test/__init__.py
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/migen/test/support.py b/migen/test/support.py
new file mode 100644 (file)
index 0000000..016373d
--- /dev/null
+++ b/migen/test/support.py
@@ -0,0 +1,24 @@
+import unittest
+from migen.fhdl.std import *
+from migen.sim.generic import Simulator
+from migen.fhdl import verilog
+
+class SimBench(Module):
+       callback = None
+       def do_simulation(self, s):
+               if self.callback is not None:
+                       return self.callback(self, s)
+
+class SimCase(unittest.TestCase):
+       TestBench = SimBench
+
+       def setUp(self):
+               self.tb = self.TestBench()
+
+       def test_to_verilog(self):
+               verilog.convert(self.tb)
+
+       def run_with(self, cb, cycles=-1):
+               self.tb.callback = cb
+               with Simulator(self.tb) as s:
+                       s.run(cycles)

diff --git a/setup.py b/setup.py
index 61121f1abb79b89e827657122e24918b29da3260..3c6713fdea963ef6fc9780b2d32929a876b8f44b 100755 (executable)
--- a/setup.py
+++ b/setup.py
@@ -22,6 +22,7 @@ setup(
        url="http://www.milkymist.org",
        download_url="https://github.com/milkymist/migen",
        packages=find_packages(here),
+       test_suite="migen.test",
        license="BSD",
        platforms=["Any"],
        keywords="HDL ASIC FPGA hardware design",