--- /dev/null
+# Links
+
+* <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001498.html>>
+* [[svp64/discussion]]
+* <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001650.html>
+* <https://bugs.libre-soc.org/show_bug.cgi?id=550>
+
+# Rewrite of SVP64 for OpenPower ISA v3.1
+
+This document focuses on the encoding of SV. It it best read in conjunction with the [[sv/overview]] which explains the background.
+
+The plan is to create an encoding for SVP64, then to create an encoding
+for SVP48, then to reorganize them both to improve field overlap,
+reducing the amount of decoder hardware necessary.
+
+All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB
+and counting up as you move to the LSB end). All bit ranges are inclusive
+(so `4:6` means bits 4, 5, and 6).
+
+64-bit instructions are split into two 32-bit words, the prefix and the
+suffix. The prefix always comes before the suffix in PC order.
+
+| 0:5 | 6:31 | 0:31 |
+|--------|--------------|--------------|
+| EXT01 | v3.1B Prefix | v3.1B Suffix |
+
+svp64 fits into the "reserved" portions of the v3.1B prefix, making it possible for svp64, v3.0B (or v3.1B including 64 bit prefixed) instructions to co-exist in the same binary without conflict.
+
+# Definition of Reserved in this spec.
+
+For the new fields added in SVP64, instructions that have any of their
+fields set to a reserved value must cause an illegal instruction trap,
+to allow emulation of future instruction sets.
+
+This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero.
+
+# Identity Behaviour
+
+SVP64 is designed so that when the prefix is all zeros, and
+ VL=1, no effect or
+influence occurs (no augmentation) such that all standard OpenPOWER
+v3.0/1B instructions covered by the prefix are "unaltered". This is termed `scalar identity behaviour` (based on the mathematical definition for "identity", as in, "identity matrix" or better "identity transformation").
+
+Note that this is completely different from when VL=0. VL=0 turns all operations under its influence into `nops` (regardless of the prefix)
+ whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction (an "identity operation").
+
+# Register Naming and size
+
+SV Registers are simply the INT, FP and CR register files extended
+linearly to larger sizes; SV Vectorisation iterates sequentially through these registers.
+
+Where the integer regfile in standard scalar
+OpenPOWER v3.0B/v3.1B is r0 to r31, SV extends this as r0 to r127.
+Likewise FP registers are extended to 128 (fp0 to fp127), and CRs are
+extended to 64 entries, CR0 thru CR63.
+
+The names of the registers therefore reflects a simple linear extension
+of the OpenPOWER v3.0B / v3.1B register naming, and in hardware this
+would be reflected by a linear increase in the size of the underlying
+SRAM used for the regfiles.
+
+Note: when an EXTRA field (defined below) is zero, SV is deliberately designed
+so that the register fields are identical to as if SV was not in effect
+i.e. under these circumstances (EXTRA=0) the register field names RA,
+RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers. This is part of
+`scalar identity behaviour` described above.
+
+## Future expansion.
+
+With the way that EXTRA fields are defined and applied to register fields,
+future versions of SV may involve 256 or greater registers. To accommodate 256 registers, numbering of Vectors will simply shift up by one bit, without
+requiring additional prefix bits. Backwards binary compatibility may be achieved with a PCR bit (Program Compatibility Register). Beyond this, further discussion is out of scope for this version of svp64.
+
+# Remapped Encoding (`RM[0:23]`)
+
+To allow relatively easy remapping of which portions of the Prefix Opcode
+Map are used for SVP64 without needing to rewrite a large portion of the
+SVP64 spec, a mapping is defined from the OpenPower v3.1 prefix bits to
+a new 24-bit Remapped Encoding denoted `RM[0]` at the MSB to `RM[23]`
+at the LSB.
+
+The mapping from the OpenPower v3.1 prefix bits to the Remapped Encoding
+is defined in the Prefix Fields section.
+
+## Prefix Opcode Map (64-bit instruction encoding)
+
+In the original table in the v3.1B OpenPOWER ISA Spec on p1350, Table 12, prefix bits 6:11 are shown, with their allocations to different v3.1B pregix "modes".
+
+The table below hows both PowerISA v3.1 instructions as well as new SVP instructions fit;
+empty spaces are yet-to-be-allocated Illegal Instructions.
+
+| 6:11 | ---000 | ---001 | ---010 | ---011 | ---100 | ---101 | ---110 | ---111 |
+|------|--------|--------|--------|--------|--------|--------|--------|--------|
+|000---| 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS |
+|001---| | | | | | | | |
+|010---| 8RR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
+|011---| | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
+|100---| MLS | MLS | MLS | MLS | MLS | MLS | MLS | MLS |
+|101---| | | | | | | | |
+|110---| MRR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
+|111---| | MMIRR | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
+
+Note that by taking up a block of 16, where in every case bits 7 and 9 are set, this allows svp64 to utilise four bits of the v3.1B Prefix space and "allocate" them to svp64's Remapped Encoding field, instead.
+
+## Prefix Fields
+
+To "activate" svp64 (in a way that does not conflict with v3.1B 64 bit Pregix mode), fields within the v3.1B Prefix Opcode Map are set
+(see Prefix Opcode Map, above), leaving 24 bits "free" for use by SV.
+This is achieved by setting bits 7 and 9 to 1:
+
+| Name | Bits | Value | Description |
+|------------|---------|-------|--------------------------------|
+| EXT01 | `0:5` | `1` | Indicates Prefixed 64-bit |
+| `RM[0]` | `6` | | Bit 0 of Remapped Encoding |
+| SVP64_7 | `7` | `1` | Indicates this is SVP64 |
+| `RM[1]` | `8` | | Bit 1 of Remapped Encoding |
+| SVP64_9 | `9` | `1` | Indicates this is SVP64 |
+| `RM[2:23]` | `10:31` | | Bits 2-23 of Remapped Encoding |
+
+Laid out bitwise, this is as follows, showing how the 32-bits of the prefix
+are constructed:
+
+| 0:5 | 6 | 7 | 8 | 9 | 10:31 |
+|--------|-------|---|-------|---|----------|
+| EXT01 | RM | 1 | RM | 1 | RM |
+| 000001 | RM[0] | 1 | RM[1] | 1 | RM]2:23] |
+
+Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1B
+instruction. That instruction becomes "prefixed" with the SVP context: the
+Remapped Encoding field (RM).
+
+# Remapped Encoding Fields
+
+Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction
+variants. There are two categories: Single and Twin Predication.
+Due to space considerations further subdivision of Single Predication
+is based on whether the number of src operands is 2 or 3.
+
+* `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
+* `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
+* `RM-2P-1S1D` Twin Predication (src=1, dest=1)
+* `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
+* `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
+
+## Common RM fields
+
+The following fields are common to all Remapped Encodings:
+
+
+| Field Name | Field bits | Description |
+|------------|------------|----------------------------------------|
+| MASK\_KIND | `0` | Execution (predication) Mask Kind |
+| MASK | `1:3` | Execution Mask |
+| ELWIDTH | `4:5` | Element Width |
+| SUBVL | `6:7` | Sub-vector length |
+| MODE | `19:23` | changes Vector behaviour |
+
+Bits 9 to 18 are further decoded depending on RM category for the instruction.
+
+## RM-1P-3S1D
+
+| Field Name | Field bits | Description |
+|------------|------------|----------------------------------------|
+| Rdest\_EXTRA2 | `8:9` | extends Rdest (R\*\_EXTRA2 Encoding) |
+| Rsrc1\_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
+| Rsrc2\_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
+| Rsrc3\_EXTRA2 | `14:15` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
+| reserved | `16` | reserved |
+
+## RM-1P-2S1D
+
+| Field Name | Field bits | Description |
+|------------|------------|-------------------------------------------|
+| Rdest\_EXTRA3 | `8:10` | extends Rdest |
+| Rsrc1\_EXTRA3 | `11:13` | extends Rsrc1 |
+| Rsrc2\_EXTRA3 | `14:16` | extends Rsrc3 |
+| ELWIDTH_SRC | `17:18` | Element Width for Source |
+
+These are for 2 operand 1 dest instructions, such as `add RT, RA,
+RB`. However also included are unusual instructions with an implicit dest
+that is identical to its src reg, such as `rlwinmi`.
+
+Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bit fields to allow
+an alternative destination. With SV however this becomes possible.
+Therefore, the fact that the dest is implicitly also a src should not
+mislead: due to the *prefix* they are different SV regs.
+
+* `rlwimi RA, RS, ...`
+* Rsrc1_EXTRA3 applies to RS as the first src
+* Rsrc2_EXTRA3 applies to RA as the secomd src
+* Rdest_EXTRA3 applies to RA to create an **independent** dest.
+
+With the addition of the EXTRA bits, the three registers
+each may be *independently* made vector or scalar, and be independently
+augmented to 7 bits in length.
+
+Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
+
+## RM-2P-1S1D/2S
+
+| Field Name | Field bits | Description |
+|------------|------------|----------------------------|
+| Rdest_EXTRA3 | `8:10` | extends Rdest |
+| Rsrc1_EXTRA3 | `11:13` | extends Rsrc1 |
+| MASK_SRC | `14:16` | Execution Mask for Source |
+| ELWIDTH_SRC | `17:18` | Element Width for Source |
+
+Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
+
+`RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
+
+## RM-2P-2S1D/1S2D/3S
+
+The primary purpose for this encoding is for Twin Predication on LOAD
+and STORE operations. see [[sv/ldst]] for detailed anslysis.
+
+RM-2P-2S1D:
+
+| Field Name | Field bits | Description |
+|------------|------------|----------------------------|
+| Rdest_EXTRA2 | `8:9` | extends Rdest (R\*\_EXTRA2 Encoding) |
+| Rsrc1_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
+| Rsrc2_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
+| MASK_SRC | `14:16` | Execution Mask for Source |
+| ELWIDTH_SRC | `17:18` | Element Width for Source |
+
+Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2
+is in bits 8:9, Rdest1_EXTRA2 in 10:11)
+
+Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src: Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
+
+Note also that LD with update indexed, which takes 2 src and 2 dest
+(e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also
+Twin Predication. therefore these are treated as RM-2P-2S1D and the
+src spec for RA is also used for the same RA as a dest.
+
+Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
+
+# Mode
+
+Mode is an augmentation of SV behaviour. Some of these alterations are element-based (saturation), others involve post-analysis (predicate result) and others are Vector-based (mapreduce, fail-on-first).
+
+These are the modes:
+
+* **normal** mode is straight vectorisation. no augmentations: the vector comprises an array of independently created results.
+* **ffirst** or data-dependent fail-on-first: see separate section. the vector may be truncated depending on certain criteria.
+ *VL is altered as a result*.
+* **sat mode** or saturation: clamps each elemrnt result to a min/max rather than overflows / wraps. allows signed and unsigned clamping.
+* **reduce mode**. a mapreduce is performed. the result is a scalar. a result vector however is required, as the upper elements may be used to store intermediary computations. the result of the mapreduce is in the first element with a nonzero predicate bit. see separate section below.
+ note that there are comprehensive caveats when using this mode.
+* **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero. When Rc=1 the CR element however is still stored in the CR regfile, even if the test failed. This scheme does not apply to crops (crand, cror). See appendix for details.
+
+Note that ffirst and reduce modes are not anticipated to be high-performance in some implementations. ffirst due to interactions with VL, and reduce due to it requiring additional operations to produce a result. normal, saturate and pred-result are however independent and may easily be parallelised to give high performance, regardless of the value of VL.
+
+The Mode table is laid out as follows:
+
+| 0-1 | 2 | 3 4 | description |
+| --- | --- |---------|-------------------------- |
+| 00 | 0 | sz dz | normal mode |
+| 00 | 1 | sz CRM | reduce mode (mapreduce), SUBVL=1 |
+| 00 | 1 | SVM CRM | subvector reduce mode, SUBVL>1 |
+| 01 | inv | CR-bit | Rc=1: ffirst CR sel |
+| 01 | inv | sz dz | Rc=0: ffirst z/nonz |
+| 10 | N | sz dz | sat mode: N=0/1 u/s |
+| 11 | inv | CR-bit | Rc=1: pred-result CR sel |
+| 11 | inv | sz dz | Rc=0: pred-result z/nonz |
+
+Fields:
+
+* **sz / dz** if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero. otherwise the element is ignored or skipped, depending on context.
+* **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1)
+* **CRM** affects the CR on reduce mode when Rc=1
+* **SVM** sets "subvector" reduce mode
+* **N** sets signed/unsigned saturation.
+
+# R\*\_EXTRA2 and R\*\_EXTRA3 Encoding
+
+EXTRA is the means by which two things are achieved:
+
+1. Registers are marked as either Vector *or Scalar*
+2. Register field numbers (limited typically to 5 bit)
+ are extended in range, both for Scalar and Vector.
+
+In the following tables register numbers are constructed from the
+standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
+or EXTRA3 field from the SV Prefix. The prefixing is arranged so that
+interoperability between prefixing and nonprefixing of scalar registers
+is direct and convenient (when the EXTRA field is all zeros).
+
+A pseudocode algorithm explains the relationship, for INT/FP (see separate section for CRs)
+
+ if extra3_mode:
+ spec = EXTRA3
+ else:
+ spec = EXTRA2 << 1 # same as EXTRA3, shifted
+ if spec[2]: # vector
+ return (RA << 2) | spec[0:1]
+ else: # scalar
+ return (spec[0:1] << 5) | RA
+
+## INT/FP EXTRA3
+
+alternative which is understandable and, if EXTRA3 is zero, maps to
+"no effect" (scalar OpenPOWER ISA field naming). also, these are the
+encodings used in the original SV Prefix scheme. the reason why they
+were chosen is so that scalar registers in v3.0B and prefixed scalar
+registers have access to the same 32 registers.
+
+| R\*\_EXTRA3 | Mode | Range | MSB downto LSB |
+|-----------|-------|---------------|---------------------|
+| 000 | Scalar | `r0-r31` | `0b00 RA` |
+| 001 | Scalar | `r32-r63` | `0b01 RA` |
+| 010 | Scalar | `r64-r95` | `0b10 RA` |
+| 011 | Scalar | `r96-r127` | `0b11 RA` |
+| 100 | Vector | `r0-r124` | `RA 0b00` |
+| 101 | Vector | `r1-r125` | `RA 0b01` |
+| 110 | Vector | `r2-r126` | `RA 0b10` |
+| 111 | Vector | `r3-r127` | `RA 0b11` |
+
+## INT/FP EXTRA2
+
+alternative which is understandable and, if EXTRA2 is zero will map to
+"no effect" i.e Scalar OpenPOWER register naming:
+
+| R\*\_EXTRA2 | Mode | Range | MSB down to LSB |
+|-----------|-------|---------------|---------------------|
+| 00 | Scalar | `r0-r31` | `0b00 RA` |
+| 01 | Scalar | `r32-r63` | `0b01 RA` |
+| 10 | Vector | `r0-r124` | `RA 0b00` |
+| 11 | Vector | `r2-r126` | `RA 0b10` |
+
+## CR EXTRA3
+
+CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
+
+ Encoding shown MSB down to LSB
+
+| R\*\_EXTRA3 | Mode | 7..5 | 4..2 | 1..0 |
+|-------------|------|---------| --------|---------|
+| 000 | Scalar | 0b000 | BA[4:2] | BA[1:0] |
+| 001 | Scalar | 0b001 | BA[4:2] | BA[1:0] |
+| 010 | Scalar | 0b010 | BA[4:2] | BA[1:0] |
+| 011 | Scalar | 0b011 | BA[4:2] | BA[1:0] |
+| 100 | Vector | BA[4:2] | 0b000 | BA[1:0] |
+| 101 | Vector | BA[4:2] | 0b010 | BA[1:0] |
+| 110 | Vector | BA[4:2] | 0b100 | BA[1:0] |
+| 111 | Vector | BA[4:2] | 0b110 | BA[1:0] |
+
+## CR EXTRA2
+
+CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
+
+Encoding shown MSB down to LSB
+
+| R\*\_EXTRA2 | Mode | 7..5 | 4..2 | 1..0 |
+|-------------|--------|---------|---------|---------|
+| 00 | Scalar | 0b000 | BA[4:2] | BA[1:0] |
+| 01 | Scalar | 0b001 | BA[4:2] | BA[1:0] |
+| 10 | Vector | BA[4:2] | 0b000 | BA[1:0] |
+| 11 | Vector | BA[4:2] | 0b100 | BA[1:0] |
+
+# ELWIDTH Encoding
+
+Default behaviour is set to 0b00 so that zeros follow the convention of
+"npt doing anything". In this case it means that elwidth overrides
+are not applicable. Thus if a 32 bit instruction operates on 32 bit,
+`elwidth=0b00` specifies that this behaviour is unmodified. Likewise
+when a processor is switched from 64 bit to 32 bit mode, `elwidth=0b00`
+states that, again, the behaviour is not to be modified.
+
+Only when elwidth is nonzero is the element width overridden to the
+explicitly required value.
+
+## Elwidth for Integers:
+
+| Value | Mnemonic | Description |
+|-------|----------------|------------------------------------|
+| 00 | DEFAULT | default behaviour for operation |
+| 01 | `ELWIDTH=b` | Byte: 8-bit integer |
+| 10 | `ELWIDTH=h` | Halfword: 16-bit integer |
+| 11 | `ELWIDTH=w` | Word: 32-bit integer |
+
+## Elwidth for FP Registers:
+
+| Value | Mnemonic | Description |
+|-------|----------------|------------------------------------|
+| 00 | DEFAULT | default behaviour for FP operation |
+| 01 | `ELWIDTH=bf16` | Reserved for `bf16` |
+| 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point |
+| 11 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
+
+Note:
+[`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
+is reserved for a future implementation of SV
+
+## Elwidth for CRs:
+
+TODO, important, particularly for crops, mfcr and mtcr, what elwidth
+even means. instead it may be possible to use the bits as extra indices
+(EXTRA6) to access the full 64 CRs. TBD, several ideas
+
+The actual width of the CRs cannot be altered: they are 4 bit. Also,
+for Rc=1 operations that produce a result (in RT or FRT) and corresponding CR, it is
+the INT/FP result to which the elwidth override applies, *not* the CR.
+This therefore inherently places Rc=1 operations firmly out of scope as far as a "meaning" for elwidth on CRs is concerned.
+
+As mentioned TBD, this leaves crops etc. to have a meaning defined for
+elwidth, because these ops are pure explicit CR based.
+
+Examples: mfxm may take the extra bits and use them as extra mask bits.
+
+# SUBVL Encoding
+
+the default for SUBVL is 1 and its encoding is 0b00 to indicate that
+SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
+lines up in combination with all other "default is all zeros" behaviour.
+
+| Value | Mnemonic | Subvec | Description |
+|-------|-----------|---------|------------------------|
+| 00 | `SUBVL=1` | single | Sub-vector length of 1 |
+| 01 | `SUBVL=2` | vec2 | Sub-vector length of 2 |
+| 10 | `SUBVL=3` | vec3 | Sub-vector length of 3 |
+| 11 | `SUBVL=4` | vec4 | Sub-vector length of 4 |
+
+The SUBVL encoding value may be thought of as an inclusive range of a
+sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore
+this may be considered to be elements 0b00 to 0b01 inclusive.
+
+# MASK/MASK_SRC & MASK_KIND Encoding
+
+One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two
+types may not be mixed.
+
+Special note: to get default behaviour (SV disabled) this field must
+be set to zero in combination with Integer Predication also being set
+to 0b000. this has the effect of enabling "all 1s" in the predicate
+mask, which is equivalent to "not having any predication at all"
+and consequently, in combination with all other default zeros, fully
+disables SV.
+
+| Value | Description |
+|-------|------------------------------------------------------|
+| 0 | MASK/MASK_SRC are encoded using Integer Predication |
+| 1 | MASK/MASK_SRC are encoded using CR-based Predication |
+
+Integer Twin predication has a second set of 3 bits that uses the same
+encoding thus allowing either the same register (r3 or r10) to be used
+for both src and dest, or different regs (one for src, one for dest).
+
+Likewise CR based twin predication has a second set of 3 bits, allowing
+a different test to be applied.
+
+## Integer Predication (MASK_KIND=0)
+
+When the predicate mode bit is zero the 3 bits are interpreted as below.
+Twin predication has an identical 3 bit field similarly encoded.
+
+| Value | Mnemonic | Element `i` enabled if: |
+|-------|----------|------------------------------|
+| 000 | ALWAYS | predicate effectively all 1s |
+| 001 | 1 << R3 | `i == R3` |
+| 010 | R3 | `R3 & (1 << i)` is non-zero |
+| 011 | ~R3 | `R3 & (1 << i)` is zero |
+| 100 | R10 | `R10 & (1 << i)` is non-zero |
+| 101 | ~R10 | `R10 & (1 << i)` is zero |
+| 110 | R30 | `R30 & (1 << i)` is non-zero |
+| 111 | ~R30 | `R30 & (1 << i)` is zero |
+
+## CR-based Predication (MASK_KIND=1)
+
+When the predicate mode bit is one the 3 bits are interpreted as below.
+Twin predication has an identical 3 bit field similarly encoded
+
+| Value | Mnemonic | Element `i` is enabled if |
+|-------|----------|--------------------------|
+| 000 | lt | `CR[offs+i].LT` is set |
+| 001 | nl/ge | `CR[offs+i].LT` is clear |
+| 010 | gt | `CR[offs+i].GT` is set |
+| 011 | ng/le | `CR[offs+i].GT` is clear |
+| 100 | eq | `CR[offs+i].EQ` is set |
+| 101 | ne | `CR[offs+i].EQ` is clear |
+| 110 | so/un | `CR[offs+i].FU` is set |
+| 111 | ns/nu | `CR[offs+i].FU` is clear |
+
+CR based predication. TODO: select alternate CR for twin predication? see
+[[discussion]] Overlap of the two CR based predicates must be taken
+into account, so the starting point for one of them must be suitably
+high, or accept that for twin predication VL must not exceed the range
+where overlap will occur, *or* that they use the same starting point
+but select different *bits* of the same CRs
+
+`offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
+
+# Appendix
+
+## XER, SO and other global flags
+
+Vector systems are expected to be high performance. This is achieved
+through parallelism, which requires that elements in the vector be
+independent. XER SO and other global "accumulation" flags (CR.OV) cause
+Read-Write Hazards on single-bit global resources, having a significant
+detrimental effect.
+
+Consequently in SV, XER.SO and CR.OV behaviour is disregarded (including in cmp ibstructions) . XER is
+simply neither read nor written. This includes when `scalar identity behaviour` occurs. If precise OpenPOWER v3.0/1 scalar behaviour is desired then OpenPOWER v3.0/1 instructions should be used without an SV Prefix.
+
+An interesting side-effect of this decision is that the OE flag is now free for other uses when SV Prefixing is used.
+
+Regarding XER.CA: this does not fit either: it was designed for a scalar ISA. Instead, both carry-in and carry-out go into the CR.so bit of a given Vector element. This provides a means to perform large parallel batches of Vectorised carry-capable additions. crweird instructions can be used to transfer the CRs in and out of an integer, where bitmanipulation may be performed to analyse the carry bits (including carry lookahead propagation) before continuing with further parallel additions.
+
+## v3.0B/v3.1B relevant instructions
+
+SV is primarily designed for use as an efficient hybrid 3D GPU / VPU / CPU ISA.
+
+As mentioned above, OE=1 is not applicable in SV, freeing this bit for alternative uses. Additionally, Vectorisation of the VSX SIMD system likewise makes no sense whatsoever. SV *replaces* VSX and provides, at the very minimum, predication (which VSX was designed without). Thus all VSX Major Opcodes - all of them - are "unused" and must raise illegal instruction exceptions in SV Prefix Mode.
+
+Likewise, `lq` (Load Quad), and Load/Store Multiple make no sense to have because they are not only provided by SV, the SV alternatives may be predicated as well, making them far better suited to use in function calls and context-switching.
+
+Additionally, some v3.0/1 instructions simply make no sense at all in a Vector context: `twi` and `tdi` fall into this category, as do branch operations as well as `sc` and `scv`. Here there is simply no point trying to Vectorise them: the standard OpenPOWER v3.0/1 instructions should be called instead.
+
+Fortuitously this leaves several Major Opcodes free for use by SV to fit alternative future instructions. In a 3D context this means Vector Product, Vector Normalise, [[sv/mv.swizzle]], Texture LD/ST operations, and others critical to an efficient, effective 3D GPU and VPU ISA. With such instructions being included as standard in other commercially-successful GPU ISAs it is likewise critical that a 3D GPU/VPU based on svp64 also have such instructions.
+
+Note however that svp64 is stand-alone and is in no way critically dependent on the existence or provision of 3D GPU or VPU instructions. These should be considered extensions, and their discussion and specification is out of scope for this document.
+
+Note, again: this is *only* under svp64 prefixing. Standard v3.0B / v3.1B is *not* altered by svp64 in any way.
+
+### Major opcode map (v3.0B)
+
+This table is taken from v3.0B.
+Table 9: Primary Opcode Map (opcode bits 0:5)
+
+ | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
+ 000 | | | tdi | twi | EXT04 | | | mulli | 000
+ 001 | subfic | | cmpli | cmpi | addic | addic. | addi | addis | 001
+ 010 | bc/l/a | EXT17 | b/l/a | EXT19 | rlwimi| rlwinm | | rlwnm | 010
+ 011 | ori | oris | xori | xoris | andi. | andis. | EXT30 | EXT31 | 011
+ 100 | lwz | lwzu | lbz | lbzu | stw | stwu | stb | stbu | 100
+ 101 | lhz | lhzu | lha | lhau | sth | sthu | lmw | stmw | 101
+ 110 | lfs | lfsu | lfd | lfdu | stfs | stfsu | stfd | stfdu | 110
+ 111 | lq | EXT57 | EXT58 | EXT59 | EXT60 | EXT61 | EXT62 | EXT63 | 111
+ | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
+
+### Suitable for svp64
+
+This is the same table containing v3.0B Primary Opcodes except those that make mo sense in a Vectorisation Context have been removed. These removed POs can, *in the SV Vector Context only*, be assigned to alternative (Vectorised-only) instructions, including future extensions.
+
+Note, again, to emphasise: outside of svp64 these opcodes **do not** change. When not prefixed with svp64 these opcodes **specifically** retain their v3.0B / v3.1B OpenPOWER Standard compliant meaning.
+
+ | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
+ 000 | | | | | | | | mulli | 000
+ 001 | subfic | | cmpli | cmpi | addic | addic. | addi | addis | 001
+ 010 | | | | EXT19 | rlwimi| rlwinm | | rlwnm | 010
+ 011 | ori | oris | xori | xoris | andi. | andis. | EXT30 | EXT31 | 011
+ 100 | lwz | lwzu | lbz | lbzu | stw | stwu | stb | stbu | 100
+ 101 | lhz | lhzu | lha | lhau | sth | sthu | | | 101
+ 110 | lfs | lfsu | lfd | lfdu | stfs | stfsu | stfd | stfdu | 110
+ 111 | | | EXT58 | EXT59 | | EXT61 | | EXT63 | 111
+ | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
+
+## Twin Predication
+
+This is a novel concept that allows predication to be applied to a single
+source and a single dest register. The following types of traditional
+Vector operations may be encoded with it, *without requiring explicit
+opcodes to do so*
+
+* VSPLAT (a single scalar distributed across a vector)
+* VEXTRACT (like LLVM IR [`extractelement`](https://releases.llvm.org/11.0.0/docs/LangRef.html#extractelement-instruction))
+* VINSERT (like LLVM IR [`insertelement`](https://releases.llvm.org/11.0.0/docs/LangRef.html#insertelement-instruction))
+* VCOMPRESS (like LLVM IR [`llvm.masked.compressstore.*`](https://releases.llvm.org/11.0.0/docs/LangRef.html#llvm-masked-compressstore-intrinsics))
+* VEXPAND (like LLVM IR [`llvm.masked.expandload.*`](https://releases.llvm.org/11.0.0/docs/LangRef.html#llvm-masked-expandload-intrinsics))
+
+Those patterns (and more) may be applied to:
+
+* mv (the usual way that V\* ISA operations are created)
+* exts\* sign-extension
+* rwlinm and other RS-RA shift operations (**note**: excluding
+ those that take RA as both a src and dest. These are not
+ 1-src 1-dest, they are 2-src, 1-dest)
+* LD and ST (treating AGEN as one source)
+* FP fclass, fsgn, fneg, fabs, fcvt, frecip, fsqrt etc.
+* Condition Register ops mfcr, mtcr and other similar
+
+This is a huge list that creates extremely powerful combinations,
+particularly given that one of the predicate options is `(1<<r3)`
+
+Additional unusual capabilities of Twin Predication include a back-to-back
+version of VCOMPRESS-VEXPAND which is effectively the ability to do
+sequentially ordered multiple VINSERTs. The source predicate selects a
+sequentially ordered subset of elements to be inserted; the destination predicate specifies the sequentially ordered recipient locations.
+This is equivalent to
+`llvm.masked.compressstore.*`
+followed by
+`llvm.masked.expandload.*`
+
+## Rounding, clamp and saturate
+
+see [[av_opcodes]].
+
+To help ensure that audio quality is not compromised by overflow,
+"saturation" is provided, as well as a way to detect when saturation
+occurred if desired (Rc=1). When Rc=1 there will be a *vector* of CRs, one CR per
+element in the result (Note: this is different from VSX which has a
+single CR per block).
+
+When N=0 the result is saturated to within the maximum range of an
+unsigned value. For integer ops this will be 0 to 2^elwidth-1. Similar
+logic applies to FP operations, with the result being saturated to
+maximum rather than returning INF, and the minimum to +0.0
+
+When N=1 the same occurs except that the result is saturated to the min
+or max of a signed result, and for FP to the min and max value rather than returning +/- INF.
+
+When Rc=1, the CR "overflow" bit is set on the CR associated with the
+element, to indicate whether saturation occurred. Note that due to
+the hugely detrimental effect it has on parallel processing, XER.SO is
+**ignored** completely and is **not** brought into play here. The CR
+overflow bit is therefore simply set to zero if saturation did not occur,
+and to one if it did.
+
+Note also that saturate on operations that produce a carry output are prohibited due to the conflicting use of the CR.so bit for storing if saturation occurred.
+
+Post-analysis of the Vector of CRs to find out if any given element hit
+saturation may be done using a mapreduced CR op (cror), or by using the
+new crweird instruction, transferring the relevant CR bits to a scalar
+integer and testing it for nonzero. see [[sv/cr_int_predication]]
+
+Note that the operation takes place at the maximum bitwidth (max of src and dest elwidth) and that truncation occurs to the range of the dest elwidth.
+
+## Reduce mode
+
+1. limited to single predicated dual src operations (add RT, RA, RB).
+ triple source operations are prohibited (fma).
+2. limited to operations that make sense. divide is excluded, as is
+ subtract (X - Y - Z produces different answers depending on the order)
+ and asymmetric CRops (crandc, crorc). sane operations:
+ multiply, min/max, add, logical bitwise OR, most other CR ops.
+ operations that do have the same source and dest register type are
+ also excluded (isel, cmp). operations involving carry or overflow
+ (XER.CA / OV) are also prohibited.
+3. the destination is a vector but the result is stored, ultimately,
+ in the first nonzero predicated element. all other nonzero predicated
+ elements are undefined. *this includes the CR vector* when Rc=1
+4. implementations may use any ordering and any algorithm to reduce
+ down to a single result. However it must be equivalent to a straight
+ application of mapreduce. The destination vector (except masked out
+ elements) may be used for storing any intermediate results. these may
+ be left in the vector (undefined).
+5. CRM applies when Rc=1. When CRM is zero, the CR associated with
+ the result is regarded as a "some results met standard CR result
+ criteria". When CRM is one, this changes to "all results met standard
+ CR criteria".
+6. implementations MAY use destoffs as well as srcoffs (see [[sv/sprs]])
+ in order to store sufficient state to resume operation should an
+ interrupt occur. this is also why implementations are permitted to use
+ the destination vector to store intermediary computations
+7. *Predication may be applied*. zeroing mode is not an option. masked-out
+ inputs are ignored; masked-out elements in the destination vector are
+ unaltered (not used for the purposes of intermediary storage); the
+ scalar result is placed in the first available unmasked element.
+
+Pseudocode for the case where RA==RB:
+
+ result = op(iregs[RA], iregs[RA+1])
+ CR = analyse(result)
+ for i in range(2, VL):
+ result = op(result, iregs[RA+i])
+ CRnew = analyse(result)
+ if Rc=1
+ if CRM:
+ CR = CR bitwise or CRnew
+ else:
+ CR = CR bitwise AND CRnew
+
+TODO: case where RA!=RB which involves first a vector of 2-operand
+results followed by a mapreduce on the intermediates.
+
+Note that when SVM is clear and SUBVL!=1 the sub-elements are *independent*, i.e. they
+are mapreduced per *sub-element* as a result. illustration with a vec2:
+
+ result.x = op(iregs[RA].x, iregs[RA+1].x)
+ result.y = op(iregs[RA].y, iregs[RA+1].y)
+ for i in range(2, VL):
+ result.x = op(result.x, iregs[RA+i].x)
+ result.y = op(result.y, iregs[RA+i].y)
+
+Note here that Rc=1 does not make sense when SVM is clear and SUBVL!=1.
+
+
+When SVM is set and SUBVL!=1, another variant is enabled: horizontal subvector mode. Example for a vec3:
+
+ for i in range(VL):
+ result = op(iregs[RA+i].x, iregs[RA+i].x)
+ result = op(result, iregs[RA+i].y)
+ result = op(result, iregs[RA+i].z)
+ iregs[RT+i] = result
+
+In this mode, when Rc=1 the Vector of CRs is as normal: each result element creates a corresponding CR element.
+
+## Fail-on-first
+
+Data-dependent fail-on-first has two distinct variants: one for LD/ST,
+the other for arithmetic operations (actually, CR-driven). Note in each
+case the assumption is that vector elements are required appear to be
+executed in sequential Program Order, element 0 being the first.
+
+* LD/ST ffirst treats the first LD/ST in a vector (element 0) as an
+ ordinary one. Exceptions occur "as normal". However for elements 1
+ and above, if an exception would occur, then VL is **truncated** to the
+ previous element.
+* Data-driven (CR-driven) fail-on-first activates when Rc=1 or other
+ CR-creating operation produces a result (including cmp). Similar to
+ branch, an analysis of the CR is performed and if the test fails, the
+ vector operation terminates and discards all element operations at and
+ above the current one, and VL is truncated to the *previous* element.
+ Thus the new VL comprises a contiguous vector of results, all of which
+ pass the testing criteria (equal to zero, less than zero).
+
+The CR-based data-driven fail-on-first is new and not found in ARM SVE
+or RVV. It is extremely useful for reducing instruction count, however
+requires speculative execution involving modifications of VL to get high
+performance implementations.
+
+In CR-based data-driven fail-on-first there is only the option to select
+and test one bit of each CR (just as with branch BO). For more complex
+tests this may be insufficient. If that is the case, a vectorised crops
+(crand, cror) may be used, and ffirst applied to the crop instead of to
+the arithmetic vector.
+
+One extremely important aspect of ffirst is:
+
+* LDST ffirst may never set VL equal to zero. This because on the first
+ element an exception must be raised "as normal".
+* CR-based data-dependent ffirst on the other hand **can** set VL equal
+ to zero. This is the only means in the entirety of SV that VL may be set
+ to zero (with the exception of via the SV.STATE SPR). When VL is set
+ zero due to the first element failing the CR bit-test, all subsequent
+ vectorised operations are effectively `nops` which is
+ *precisely the desired and intended behaviour*.
+
+Another aspect is that for ffirst LD/STs, VL may be truncated arbitrarily to a nonzero value for any implementation-specific reason. For example: it is perfectly reasonable for implementations to alter VL when ffirst LD or ST operations are initiated on a nonaligned boundary, such that within a loop the subsequent iteration of that loop begins subsequent ffirst LD/ST operations on an aligned boundary. Likewise, to reduce workloads or balance resources.
+
+CR-based data-dependent first on the other hand MUST not truncate VL arbitrarily. This because it is a precise test on which algorithms will rely.
+
+## pred-result mode
+
+This mode merges common CR testing with predication, saving on instruction count. Below is the pseudocode excluding predicate zeroing and elwidth overrides.
+
+ for i in range(VL):
+ # predication test, skip all masked out elements.
+ if predicate_masked_out(i):
+ continue
+ result = op(iregs[RA+i], iregs[RB+i])
+ CRnew = analyse(result) # calculates eq/lt/gt
+ # Rc=1 always stores the CR
+ if Rc=1:
+ crregs[offs+i] = CRnew
+ # now test CR, similar to branch
+ if CRnew[BO[0:1]] != BO[2]:
+ continue # test failed: cancel store
+ # result optionally stored but CR always is
+ iregs[RT+i] = result
+
+The reason for allowing the CR element to be stored is so that post-analysis
+of the CR Vector may be carried out. For example: Saturation may have occurred (and been prevented from updating, by the test) but it is desirable to know *which* elements fail saturation.
+
+Note that predication is still respected: predicate zeroing is slightly different: elements that fail the CR test *or* are masked out are zero'd.
+
+## CR Operations
+
+CRs are slightly more involved than INT or FP registers due to the
+possibility for indexing individual bits (crops BA/BB/BT). Again however
+the access pattern needs to be understandable in relation to v3.0B / v3.1B
+numbering, with a clear linear relationship and mapping existing when
+SV is applied.
+
+### CR EXTRA mapping table and algorithm
+
+Numbering relationships for CR fields are already complex due to being
+in BE format (*the relationship is not clearly explained in the v3.0B
+or v3.1B specification*). However with some care and consideration
+the exact same mapping used for INT and FP regfiles may be applied,
+just to the upper bits, as explained below.
+
+In OpenPOWER v3.0/1, BF/BT/BA/BB are all 5 bits. The top 3 bits (2:4)
+select one of the 8 CRs; the bottom 2 bits (0:1) select one of 4 bits
+*in* that CR. The numbering was determined (after 4 months of
+analysis and research) to be as follows:
+
+ CR_index = 7-(BA>>2) # top 3 bits but BE
+ bit_index = 3-(BA & 0b11) # low 2 bits but BE
+ CR_reg = CR[CR_index] # get the CR
+ # finally get the bit from the CR.
+ CR_bit = (CR_reg & (1<<bit_index)) != 0
+
+When it comes to applying SV, it is the CR\_reg number to which SV EXTRA2/3
+applies, **not** the CR\_bit portion (bits 0:1):
+
+ if extra3_mode:
+ spec = EXTRA3
+ else:
+ spec = EXTRA2<<1 | 0b0
+ if spec[2]:
+ # vector constructs "BA[2:4] spec[0:1] 0 BA[0:1]"
+ return ((BA >> 2)<<5) | # hi 3 bits shifted up
+ (spec[0:1]<<3) | # to make room for these
+ (BA & 0b11) # CR_bit on the end
+ else:
+ # scalar constructs "0 spec[0:1] BA[0:4]"
+ return (spec[0:1] << 5) | BA
+
+Thus, for example, to access a given bit for a CR in SV mode, the v3.0B
+algorithm to determin CR\_reg is modified to as follows:
+
+ CR_index = 7-(BA>>2) # top 3 bits but BE
+ if spec[2]:
+ # vector mode
+ CR_index = (CR_index<<3) | (spec[0:1] << 1)
+ else:
+ # scalar mode
+ CR_index = (spec[0:1]<<3) | CR_index
+ # same as for v3.0/v3.1 from this point onwards
+ bit_index = 3-(BA & 0b11) # low 2 bits but BE
+ CR_reg = CR[CR_index] # get the CR
+ # finally get the bit from the CR.
+ CR_bit = (CR_reg & (1<<bit_index)) != 0
+
+Note here that the decoding pattern to determine CR\_bit does not change.
+
+Note: high-performance implementations may read/write Vectors of CRs in
+batches of aligned 32-bit chunks (CR0-7, CR7-15). This is to greatly
+simplify internal design. If instructions are issued where CR Vectors
+do not start on a 32-bit aligned boundary, performance may be affected.
+
+### CR fields as inputs/outputs of vector operations
+
+CRs (or, the arithmetic operations associated with them)
+may be marked as Vectorised or Scalar. When Rc=1 in arithmetic operations that have no explicit EXTRA to cover the CR, the CR is Vectorised if the destination is Vectorised. Likewise if the destination is scalar then so is the CR.
+
+When vectorized, the CR inputs/outputs are sequentially read/written
+to 4-bit CR fields. Vectorised Integer results, when Rc=1, will begin
+writing to CR8 (TBD evaluate) and increase sequentially from there.
+This is so that:
+
+* implementations may rely on the Vector CRs being aligned to 8. This
+ means that CRs may be read or written in aligned batches of 32 bits
+ (8 CRs per batch), for high performance implementations.
+* scalar Rc=1 operation (CR0, CR1) and callee-saved CRs (CR2-4) are not
+ overwritten by vector Rc=1 operations except for very large VL
+* CR-based predication, from CR32, is also not interfered with
+ (except by large VL).
+
+However when the SV result (destination) is marked as a scalar by the
+EXTRA field the *standard* v3.0B behaviour applies: the accompanying
+CR when Rc=1 is written to. This is CR0 for integer operations and CR1
+for FP operations.
+
+Note that yes, the CRs are genuinely Vectorised. Unlike in SIMD VSX which
+has a single CR (CR6) for a given SIMD result, SV Vectorised OpenPOWER
+v3.0B scalar operations produce a **tuple** of element results: the
+result of the operation as one part of that element *and a corresponding
+CR element*. Greatly simplified pseudocode:
+
+ for i in range(VL):
+ # calculate the vector result of an add
+ iregs[RT+i] = iregs[RA+i] + iregs[RB+i]
+ # now calculate CR bits
+ CRs[8+i].eq = iregs[RT+i] == 0
+ CRs[8+i].gt = iregs[RT+i] > 0
+ ... etc
+
+If a "cumulated" CR based analysis of results is desired (a la VSX CR6)
+then a followup instruction must be performed, setting "reduce" mode on
+the Vector of CRs, using cr ops (crand, crnor)to do so. This provides far
+more flexibility in analysing vectors than standard Vector ISAs. Normal
+Vector ISAs are typically restricted to "were all results nonzero" and
+"were some results nonzero". The application of mapreduce to Vectorised
+cr operations allows far more sophisticated analysis, particularly in
+conjunction with the new crweird operations see [[sv/cr_int_predication]].
+
+Note in particular that the use of a separate instruction in this way
+ensures that high performance multi-issue OoO inplementations do not
+have the computation of the cumulative analysis CR as a bottleneck and
+hindrance, regardless of the length of VL.
+
+(see [[discussion]]. some alternative schemes are described there)
+
+### Rc=1 when SUBVL!=1
+
+sub-vectors are effectively a form of SIMD (length 2 to 4). Only 1 bit of predicate is allocated per subvector; likewise only one CR is allocated
+per subvector.
+
+This leaves a conundrum as to how to apply CR computation per subvector, when normally Rc=1 is exclusively applied to scalar elements. A solution is to perform a bitwise OR or AND of the subvector tests. Given that OE is ignored, rhis field may (when available) be used to select OR or AND behavior.
+
+### Table of CR fields
+
+CR[i] is the notation used by the OpenPower spec to refer to CR field #i,
+so FP instructions with Rc=1 write to CR[1] aka SVCR1_000.
+
+CRs are not stored in SPRs: they are registers in their own right.
+Therefore context-switching the full set of CRs involves a Vectorised
+mfcr or mtcr, using VL=64, elwidth=8 to do so. This is exactly as how scalar OpenPOWER context-switches CRs: it is just that there are now more of them.
+
+The 64 SV CRs are arranged similarly to the way the 128 integer registers
+are arranged. TODO a python program that auto-generates a CSV file
+which can be included in a table, which is in a new page (so as not to
+overwhelm this one). [[svp64/cr_names]]
+
+## Register Profiles
+
+**NOTE THIS TABLE SHOULD NO LONGER BE HAND EDITED** see
+<https://bugs.libre-soc.org/show_bug.cgi?id=548> for details.
+
+Instructions are broken down by Register Profiles as listed in the
+following auto-generated page: [[opcode_regs_deduped]]. "Non-SV"
+indicates that the operations with this Register Profile cannot be
+Vectorised (mtspr, bc, dcbz, twi)
+
+TODO generate table which will be here [[svp64/reg_profiles]]
+
+## SV pseudocode illilustration
+
+### Single-predicated Instruction
+
+illustration of normal mode add operation: zeroing not included, elwidth overrides not included. if there is no predicate, it is set to all 1s
+
+ function op_add(rd, rs1, rs2) # add not VADD!
+ int i, id=0, irs1=0, irs2=0;
+ predval = get_pred_val(FALSE, rd);
+ for (i = 0; i < VL; i++)
+ STATE.srcoffs = i # save context
+ if (predval & 1<<i) # predication uses intregs
+ ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
+ if (!int_vec[rd ].isvec) break;
+ if (rd.isvec) { id += 1; }
+ if (rs1.isvec) { irs1 += 1; }
+ if (rs2.isvec) { irs2 += 1; }
+ if (id == VL or irs1 == VL or irs2 == VL) {
+ # end VL hardware loop
+ STATE.srcoffs = 0; # reset
+ return;
+ }
+
+This has several modes:
+
+* RT.v = RA.v RB.v
+* RT.v = RA.v RB.s (and RA.s RB.v)
+* RT.v = RA.s RB.s
+* RT.s = RA.v RB.v
+* RT.s = RA.v RB.s (and RA.s RB.v)
+* RT.s = RA.s RB.s
+
+All of these may be predicated. Vector-Vector is straightfoward. When one of source is a Vector and the other a Scalar, it is clear that each element of the Vector source should be added to the Scalar source, each result placed into the Vector (or, if the destination is a scalar, only the first nonpredicated result).
+
+The one that is not obvious is RT=vector but both RA/RB=scalar. Here this acts as a "splat scalar result", copying the same result into all nonpredicated result elements. If a fixed destination scalar was intended, then an all-Scalar operation should be used.
+
+See <https://bugs.libre-soc.org/show_bug.cgi?id=552>
+
+## Assembly Annotation
+
+Assembly code annotation is required for SV to be able to successfully
+mark instructions as "prefixed".
+
+A reasonable (prototype) starting point:
+
+ svp64 [field=value]*
+
+Fields:
+
+* ew=8/16/32 - element width
+* sew=8/16/32 - source element width
+* vec=2/3/4 - SUBVL
+* mode=reduce/satu/sats/crpred
+* pred=1\<\<3/r3/~r3/r10/~r10/r30/~r30/lt/gt/le/ge/eq/ne
+* spred={reg spec}
+
+similar to x86 "rex" prefix.
--- /dev/null
+# CR names
+
+TODO autogenerate CSV file to be included here
--- /dev/null
+
+# Note about naming
+
+the original assessment for SVP from 18 months ago concluded that it should be easy for scalar (non SV) instructions to get at the exact same scalar registers when in SVP mode. otherwise scalar v3.0B code needs to restrict itself to a massively truncated subset of the scalar registers numbered 0-31 (only r0, r4, r8...) which hugely interferes with ABIs to such an extent that it would compromise SV.
+
+question: has anything changed about the assessment that was done, which concluded that for scalar SVP regs they should overlap completely with scalar ISA regs?
+
+
+# Notes on requirements for bit allocations
+
+do not try to jam VL or MAXVL in. go with the flow of 24 bits spare.
+
+* 2: SUBVL
+* 2: elwidth
+* 2: twin-predication (src, dest) elwidth
+* 1: select INT or CR predication
+* 3: predicate selection and inversion (QTY 2 for tpred)
+* 4x2 or 3x3: src1/2/3/dest Vector/Scalar reg
+* 5: mode
+
+totals: 24 bits (dest elwidth shared)
+
+http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001434.html
+
+## All zeros indicates "disable SVP"
+
+The defaults for all capabilities of SVP should be zero to indicate "no action". SUBVL=1 encoded as 0b00. register name prefixes, scalar=0b0, elwidth overrides DEFAULT=0b00, predication off=0b000 etc.
+
+this way SV may be entirely disabled, leaving an "all zeros" to indicate to v3.1B 64bit prefixing that the standard OpenPOWER v3.1B encodings are in full effect (and that SV is not). As all zeros meshes with current "reserved" encodings this should work well.
+
+
+## twin predication
+
+twin predication and twin elwidth overrides is extremely important to have to be able to override both the src and dest elwidth yet keep the underlying scalar operation intact. examples include mr with an elwidth=8, VL=8 on the src will take a byte at a time from one 64 bit reg and place it into 8x 64-bit regs, zero-extended. more complex operations involve SUBVL and Audio/Video DSP operations, see [[av_opcodes]]
+
+something like:
+
+| 0 1 | 2 3 | 4 5 | 6 | 7 9 | 10 12 | 13 18 | 19 23 |
+|-------|-----|-----|------|------|-------|-------|-------|
+| subvl | sew | dew | ptyp | psrc | pdst | vspec | mode |
+
+table:
+
+* subvl - 1 to 4 scalar / vec2 / vec3 / vec4
+* sew / dew - DEFAULT / 8 / 16 /32 element width
+* ptyp - predication INT / CR
+* psrc / pdst - predicate mask selector and inversion
+* vspec - 3 bit src / dest scalar-vector extension
+* mode: 5 bits
+
+## twin predication, CR based.
+
+separate src and dest predicates are a critical part of SV for provision of VEXPAND, VCOMPRESS, VSPLAT, VINSERT and many more operations.
+
+Twin CR predication could be done in two ways:
+
+* start from different CRs for the src and dest
+* start from the same CR.
+
+With different bits being selectable (CR[0..3]) starting from the same CR makes some sense.
+
+# standard arith ops (single predication)
+
+these are of the form res = op(src1, src2, ...)
+
+| 0 1 | 2 3 | 4 5 | 6 | 7 9 | 10 18 | 19 23 |
+|-------|-----|-----|------|------|-------|--------|
+| subvl | sew | dew | ptyp | pred | vspec | mode |
+
+table:
+
+* subvl - 1 to 4 scalar / vec2 / vec3 / vec4
+* sew / dew - DEFAULT / 8 / 16 /32 element width
+* ptyp - predication INT / CR
+* pred - predicate mask selector and inversion
+* vspec - 2/3 bit src / dest scalar-vector extension
+* mode - 5 bit
+
+For 2 op (dest/src1/src2) the tag may be 3 bits: total 9 bits. for 3 op (dest/src1/2/3) the vspec may be 2 bits per reg: total 8 bits.
+
+Note:
+
+* the operation should always be done at max(srcwidth, dstwidth), unless it can
+ be proven using the lower will lead to the same result
+* saturation is done on the result at the **dest** elwidth
+
+Some examples on different operation widths:
+
+ u16 / u16 = u8
+ 256 / 2 = 128 # if we used the smaller width, we'd get 0. Wrong
+
+ u8 * u8 = u16
+ 255 * 2 = 510 # if we used the smaller width, we'd get 254. Wrong
+
+ u16 + u16 = u8
+ 256 + 2 = 2 # this is correct whether we use the larger or smaller width
+ # aka hw can optimize narrowing addition
+
+
+# Notes about Swizzle
+
+Basically, there isn't enough room to try to fit two src src1/2 swizzle, and SV, even into 64 bit (actually 24) without severely compromising on the number of bits allocated to either swizzle, or SV, or both.
+
+therefore the strategy proposed is:
+
+* design 16bit scalar ops
+* use the 11 bit old SV prefix to create 32bit insns
+* when those are embedded into v3.1B 64 prefix, the 24 bits are entirely allocated to swizzle.
+
+with 2x12 this would mean no need to have complex encoding of swizzle.
+
+if we really do need 2 bits spare then the complex encoder of swizzle could be deployed. (*an analysis shows this to be very unlikely. 7^4 is around 2400 which still requires 12 bits to encode* (that's miscalculated, see Single Swizzle section below.) it isn't because you missed out predicate mask skip as thr 7th option.)
+
+## Single Swizzle
+
+I expect swizzle to not be common enough to warrant 2 swizzles in a single instruction, therefor the above swizzle strategy is probably unnecessary.
+
+Also, if a swizzle supports up to subvl=4, then 11 bits is sufficient since each swizzle element needs to be able to select 1 of 6 different values: 0, 1, x, y, z, w. 6^4 = 1296 which easily fits in 11 bits (only by dropping "predicate mask" from the list of options, which makes 7 options not 6. see [[mv.swizzle]])
+
+What about subvl=4 that skips one element? src vec is 4 but one of the elements is to be left alone? This is not 6 options, it is 7 options (including "skip" i.e combining with a predicate mask in effect). note that this is not the same as a vec3-with-a-skip
+
+What could hypothetically be done is: when SUBVL=3 a different encoding is used, one that allows the "skip" to be specified. X Y skip W for example. this would then be interpreted, "actually the vector is vec4 but one rlement is skipped"
+
+the problem with that is that now SUBVL has become critically dependent on the swizzle, worse than that the swizzle is embedded in the instruction, even worse than that it's encoded in a complex multi-gate fashion.
+
+all of which screams, "this is going in completely the wrong direction". keep it simple. 7 options, 3 bits, 4x3, 12 bits for swizzle, ignore some if SUBVL is 1 2 or 3.
+
+# note about INT predicate
+
+001 ALWAYS (implicit) Operation is not masked
+
+this means by default that 001 will always be in nonpredicated ops, which seems anomalous. would 000 be better to indicate "no predication"?
+
+000 would indicate "the predicate is an immediate of all 1s" i.e. "no operation is masked out"
+
+programmerjake:
+I picked 0001 to indicate ALWAYS since that matches with the other semantics: the LSB bit is invert-the-mask, and you can think about the table as-if it is really:
+
+this is the opposite of what feels natural. inversion should switch *off* something. also 000 is the canonical "this feature is off by default" number.
+
+the constant should be an immediate of all 1s (not r0), which is the natural way to think of "predication is off".
+
+i get the idea "r0 to be used therefore it is all zeros" but that makes 001 the "default", not 000.
+
+| Value | Mnemonic |
+|-------|-------------|
+| 000 | R0 (zero) set to all 1s, naturally means "no predication" |
+| 001 | ~R0 (~zero) |
+| 010 | R3 |
+| 011 | ~R3 |
+| 100 | R10 |
+| 101 | ~R10 |
+| 110 | R30 |
+| 111 | ~R30 |
+
+
+# CR Vectorisation
+
+Some thoughts on this: the sensible (sane) number of CRs to have is 64. A case could be made for having 128 but it is an awful lot. 64 CRs also has the advantage that it is only 4x 64 bit registers on a context-switch (programmerjake: yeah, but we already have 256 64-bit registers, a few more won't change much).
+
+A practical issue stems from the fact that accessing the CR regfile on a non-aligned 8-CR boundary during Vector operations would significantly increase internal routing. By aligning Vector Reads/Writes to 8 CRs this requires only 32 bit aligned read/writes. (programmerjake: simple solution -- rename them internally such that CR6 is the first one)
+
+How to number them as vectors gets particularly interesting. A case could be made for treating the 64 CRs as a square, and using CR numbering (CR0-7) to begin VL for-loop incrementing first by row and when rolling over to increment the column. CR6 CR14 ... CR62 then CR7 CR15 ...
+
+When the SV prefix marks them with 2 bits, one of those could be used to indicate scalar, and the other to indicate whether the 3 bit CR number is to be treated as a horizontal vector (CR incrementing straight by 1) or a vertical vector (incrementing by 8)
+
+When there are 3 bits it would be possible to indicate whether to begin from a position offset by 4 (middle of matrix, edge of matrix).
+
+Note: considerable care needs to be taken when putting these horiz/vertical CRs through the Dependency Matrices
+
+Indexing algorithm illustrating how the H/V modes would work. Note that BA is the 3 bit CR register field that normsll, in scalar ISA, would reference only CR0-7 as CR[BA].
+
+ for i in range(VL)
+ y = i % 8
+ x = i // 8
+ if verticalmode:
+ CRINDEX = BA + y*8 + x
+ else:
+ CRINDEX = BA*8 + i
+ CR[CRINDEX] = ...
+
+# Should twin-predication (src=1, dest=1) have DEST SUBVL?
+
+this is tricky: there isn't really enough space unless the reg scalar-vector extension (currently 3 bits per reg) is compacted to only 2 bits each, which would provide 2 extra bits.
+
+so before adding this, an evaluation is needed: *is it necessary*?
+
+what actual operations out of this list need - and work - with a separate SRC and DEST SUBVL?
+
+* mv (the usual way that V* operations are created)
+* exts* sign-extension
+* rwlinm and other RS-RA shift operations
+* LD and ST (treating AGEN as one source)
+* FP fclass, fsgn, fneg, fabs, fcvt, frecip, fsqrt etc.
+* Condition Register ops mfcr, mtcr and other similar
+
+Evaluation:
+
+* mv: yes. these may need merge/split
+* exts: no. no transformation.
+* rwlinm shift operations: no
+* LD and ST: no
+* FP ops: no
+* CR ops: maybe on mvs, not on arithmetic.
+
+therefore it makes no sense to have DEST SUBVL, and instead to have special mv operations. see [[mv.vec]]
--- /dev/null
+# table to be autogenerated
+
+## LDST-1R-1W-imm
+
+`RM-2P-1S1D`
+
+LD immediate
+
+## LDST-1R-2W-imm
+
+LD immediate with update
+
+## LDST-2R-imm
+
+ST immediate
+
+## LDST-2R-1W
+
+`RM-2P-2S1D`
+
+LD Indexed with update
+
+## LDST-2R-1W-imm
+
+ST Indexed with update
+
+## LDST-2R-2W
+
+LD Indexed with update
+
+## LDST-3R
+
+ST Indexed
+
+## LDST-3R-CRo
+
+ST Indexed cache
+
+## LDST-3R-1W
+
+ST Indexed with update
+
+## CRio
+TBD
+## CR=2R1W
+
+Remapped Encoding Fields: `RM-1P-2S1D`
+
+
+## 1W-CRi
+
+Remapped Encoding Fields: `RM-2P-1S1D`
+
+
+
+## 1R-CRo
+
+Remapped Encoding Fields: `RM-2P-1S1D`
+
+
+## 1R-CRio
+
+Remapped Encoding Fields: `RM-2P-1S1D`
+
+
+
+## 1R-1W
+
+Remapped Encoding Fields: `RM-2P-1S1D`
+
+
+## 1R-1W-imm
+
+Remapped Encoding Fields: `RM-2P-1S1D`
+
+
+
+## 1R-1W-CRo
+
+Remapped Encoding Fields: `RM-2P-1S1D`
+
+
+
+## 1R-1W-CRio
+
+Remapped Encoding Fields: `RM-2P-1S1D`
+
+
+
+## 2R-CRo
+
+Remapped Encoding Fields: `RM-1P-2S1D`
+# table to be autogenerated
+
+
+## 2R-CRio
+
+Remapped Encoding Fields: `RM-1P-2S1D`
+
+
+
+## 2R-1W
+
+Remapped Encoding Fields: `RM-1P-2S1D`
+
+
+
+## 2R-1W-CRo
+
+Remapped Encoding Fields: `RM-1P-2S1D`
+
+*Note that analysis of `rl(w|d)imi` shows that these are correctly identified as 2S1D. The pseudocode in [[isa/fixedshift]] although RA is used as both a src and a dest the EXTRA3 extension of each of these gives different meanings to the src RA and dest RA.*
+
+
+## 2R-1W-CRi
+TBD
+
+## 2R-1W-CRio
+
+Remapped Encoding Fields: `RM-1P-2S1D`
+
+
+
+## 3R-1W-CRio
+
+Remapped Encoding Fields: `RM-1P-3S1D`
+
+++ /dev/null
-# Links
-
-* <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001498.html>>
-* [[svp64/discussion]]
-* <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001650.html>
-* <https://bugs.libre-soc.org/show_bug.cgi?id=550>
-
-# Rewrite of SVP64 for OpenPower ISA v3.1
-
-This document focuses on the encoding of SV. It it best read in conjunction with the [[sv/overview]] which explains the background.
-
-The plan is to create an encoding for SVP64, then to create an encoding
-for SVP48, then to reorganize them both to improve field overlap,
-reducing the amount of decoder hardware necessary.
-
-All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB
-and counting up as you move to the LSB end). All bit ranges are inclusive
-(so `4:6` means bits 4, 5, and 6).
-
-64-bit instructions are split into two 32-bit words, the prefix and the
-suffix. The prefix always comes before the suffix in PC order.
-
-| 0:5 | 6:31 | 0:31 |
-|--------|--------------|--------------|
-| EXT01 | v3.1B Prefix | v3.1B Suffix |
-
-svp64 fits into the "reserved" portions of the v3.1B prefix, making it possible for svp64, v3.0B (or v3.1B including 64 bit prefixed) instructions to co-exist in the same binary without conflict.
-
-# Definition of Reserved in this spec.
-
-For the new fields added in SVP64, instructions that have any of their
-fields set to a reserved value must cause an illegal instruction trap,
-to allow emulation of future instruction sets.
-
-This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero.
-
-# Identity Behaviour
-
-SVP64 is designed so that when the prefix is all zeros, and
- VL=1, no effect or
-influence occurs (no augmentation) such that all standard OpenPOWER
-v3.0/1B instructions covered by the prefix are "unaltered". This is termed `scalar identity behaviour` (based on the mathematical definition for "identity", as in, "identity matrix" or better "identity transformation").
-
-Note that this is completely different from when VL=0. VL=0 turns all operations under its influence into `nops` (regardless of the prefix)
- whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction (an "identity operation").
-
-# Register Naming and size
-
-SV Registers are simply the INT, FP and CR register files extended
-linearly to larger sizes; SV Vectorisation iterates sequentially through these registers.
-
-Where the integer regfile in standard scalar
-OpenPOWER v3.0B/v3.1B is r0 to r31, SV extends this as r0 to r127.
-Likewise FP registers are extended to 128 (fp0 to fp127), and CRs are
-extended to 64 entries, CR0 thru CR63.
-
-The names of the registers therefore reflects a simple linear extension
-of the OpenPOWER v3.0B / v3.1B register naming, and in hardware this
-would be reflected by a linear increase in the size of the underlying
-SRAM used for the regfiles.
-
-Note: when an EXTRA field (defined below) is zero, SV is deliberately designed
-so that the register fields are identical to as if SV was not in effect
-i.e. under these circumstances (EXTRA=0) the register field names RA,
-RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers. This is part of
-`scalar identity behaviour` described above.
-
-## Future expansion.
-
-With the way that EXTRA fields are defined and applied to register fields,
-future versions of SV may involve 256 or greater registers. To accommodate 256 registers, numbering of Vectors will simply shift up by one bit, without
-requiring additional prefix bits. Backwards binary compatibility may be achieved with a PCR bit (Program Compatibility Register). Beyond this, further discussion is out of scope for this version of svp64.
-
-# Remapped Encoding (`RM[0:23]`)
-
-To allow relatively easy remapping of which portions of the Prefix Opcode
-Map are used for SVP64 without needing to rewrite a large portion of the
-SVP64 spec, a mapping is defined from the OpenPower v3.1 prefix bits to
-a new 24-bit Remapped Encoding denoted `RM[0]` at the MSB to `RM[23]`
-at the LSB.
-
-The mapping from the OpenPower v3.1 prefix bits to the Remapped Encoding
-is defined in the Prefix Fields section.
-
-## Prefix Opcode Map (64-bit instruction encoding)
-
-In the original table in the v3.1B OpenPOWER ISA Spec on p1350, Table 12, prefix bits 6:11 are shown, with their allocations to different v3.1B pregix "modes".
-
-The table below hows both PowerISA v3.1 instructions as well as new SVP instructions fit;
-empty spaces are yet-to-be-allocated Illegal Instructions.
-
-| 6:11 | ---000 | ---001 | ---010 | ---011 | ---100 | ---101 | ---110 | ---111 |
-|------|--------|--------|--------|--------|--------|--------|--------|--------|
-|000---| 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS |
-|001---| | | | | | | | |
-|010---| 8RR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
-|011---| | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
-|100---| MLS | MLS | MLS | MLS | MLS | MLS | MLS | MLS |
-|101---| | | | | | | | |
-|110---| MRR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
-|111---| | MMIRR | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
-
-Note that by taking up a block of 16, where in every case bits 7 and 9 are set, this allows svp64 to utilise four bits of the v3.1B Prefix space and "allocate" them to svp64's Remapped Encoding field, instead.
-
-## Prefix Fields
-
-To "activate" svp64 (in a way that does not conflict with v3.1B 64 bit Pregix mode), fields within the v3.1B Prefix Opcode Map are set
-(see Prefix Opcode Map, above), leaving 24 bits "free" for use by SV.
-This is achieved by setting bits 7 and 9 to 1:
-
-| Name | Bits | Value | Description |
-|------------|---------|-------|--------------------------------|
-| EXT01 | `0:5` | `1` | Indicates Prefixed 64-bit |
-| `RM[0]` | `6` | | Bit 0 of Remapped Encoding |
-| SVP64_7 | `7` | `1` | Indicates this is SVP64 |
-| `RM[1]` | `8` | | Bit 1 of Remapped Encoding |
-| SVP64_9 | `9` | `1` | Indicates this is SVP64 |
-| `RM[2:23]` | `10:31` | | Bits 2-23 of Remapped Encoding |
-
-Laid out bitwise, this is as follows, showing how the 32-bits of the prefix
-are constructed:
-
-| 0:5 | 6 | 7 | 8 | 9 | 10:31 |
-|--------|-------|---|-------|---|----------|
-| EXT01 | RM | 1 | RM | 1 | RM |
-| 000001 | RM[0] | 1 | RM[1] | 1 | RM]2:23] |
-
-Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1B
-instruction. That instruction becomes "prefixed" with the SVP context: the
-Remapped Encoding field (RM).
-
-# Remapped Encoding Fields
-
-Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction
-variants. There are two categories: Single and Twin Predication.
-Due to space considerations further subdivision of Single Predication
-is based on whether the number of src operands is 2 or 3.
-
-* `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
-* `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
-* `RM-2P-1S1D` Twin Predication (src=1, dest=1)
-* `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
-* `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
-
-## Common RM fields
-
-The following fields are common to all Remapped Encodings:
-
-
-| Field Name | Field bits | Description |
-|------------|------------|----------------------------------------|
-| MASK\_KIND | `0` | Execution (predication) Mask Kind |
-| MASK | `1:3` | Execution Mask |
-| ELWIDTH | `4:5` | Element Width |
-| SUBVL | `6:7` | Sub-vector length |
-| MODE | `19:23` | changes Vector behaviour |
-
-Bits 9 to 18 are further decoded depending on RM category for the instruction.
-
-## RM-1P-3S1D
-
-| Field Name | Field bits | Description |
-|------------|------------|----------------------------------------|
-| Rdest\_EXTRA2 | `8:9` | extends Rdest (R\*\_EXTRA2 Encoding) |
-| Rsrc1\_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
-| Rsrc2\_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
-| Rsrc3\_EXTRA2 | `14:15` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
-| reserved | `16` | reserved |
-
-## RM-1P-2S1D
-
-| Field Name | Field bits | Description |
-|------------|------------|-------------------------------------------|
-| Rdest\_EXTRA3 | `8:10` | extends Rdest |
-| Rsrc1\_EXTRA3 | `11:13` | extends Rsrc1 |
-| Rsrc2\_EXTRA3 | `14:16` | extends Rsrc3 |
-| ELWIDTH_SRC | `17:18` | Element Width for Source |
-
-These are for 2 operand 1 dest instructions, such as `add RT, RA,
-RB`. However also included are unusual instructions with an implicit dest
-that is identical to its src reg, such as `rlwinmi`.
-
-Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bit fields to allow
-an alternative destination. With SV however this becomes possible.
-Therefore, the fact that the dest is implicitly also a src should not
-mislead: due to the *prefix* they are different SV regs.
-
-* `rlwimi RA, RS, ...`
-* Rsrc1_EXTRA3 applies to RS as the first src
-* Rsrc2_EXTRA3 applies to RA as the secomd src
-* Rdest_EXTRA3 applies to RA to create an **independent** dest.
-
-With the addition of the EXTRA bits, the three registers
-each may be *independently* made vector or scalar, and be independently
-augmented to 7 bits in length.
-
-Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
-
-## RM-2P-1S1D/2S
-
-| Field Name | Field bits | Description |
-|------------|------------|----------------------------|
-| Rdest_EXTRA3 | `8:10` | extends Rdest |
-| Rsrc1_EXTRA3 | `11:13` | extends Rsrc1 |
-| MASK_SRC | `14:16` | Execution Mask for Source |
-| ELWIDTH_SRC | `17:18` | Element Width for Source |
-
-Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
-
-`RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
-
-## RM-2P-2S1D/1S2D/3S
-
-The primary purpose for this encoding is for Twin Predication on LOAD
-and STORE operations. see [[sv/ldst]] for detailed anslysis.
-
-RM-2P-2S1D:
-
-| Field Name | Field bits | Description |
-|------------|------------|----------------------------|
-| Rdest_EXTRA2 | `8:9` | extends Rdest (R\*\_EXTRA2 Encoding) |
-| Rsrc1_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
-| Rsrc2_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
-| MASK_SRC | `14:16` | Execution Mask for Source |
-| ELWIDTH_SRC | `17:18` | Element Width for Source |
-
-Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2
-is in bits 8:9, Rdest1_EXTRA2 in 10:11)
-
-Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src: Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
-
-Note also that LD with update indexed, which takes 2 src and 2 dest
-(e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also
-Twin Predication. therefore these are treated as RM-2P-2S1D and the
-src spec for RA is also used for the same RA as a dest.
-
-Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
-
-# Mode
-
-Mode is an augmentation of SV behaviour. Some of these alterations are element-based (saturation), others involve post-analysis (predicate result) and others are Vector-based (mapreduce, fail-on-first).
-
-These are the modes:
-
-* **normal** mode is straight vectorisation. no augmentations: the vector comprises an array of independently created results.
-* **ffirst** or data-dependent fail-on-first: see separate section. the vector may be truncated depending on certain criteria.
- *VL is altered as a result*.
-* **sat mode** or saturation: clamps each elemrnt result to a min/max rather than overflows / wraps. allows signed and unsigned clamping.
-* **reduce mode**. a mapreduce is performed. the result is a scalar. a result vector however is required, as the upper elements may be used to store intermediary computations. the result of the mapreduce is in the first element with a nonzero predicate bit. see separate section below.
- note that there are comprehensive caveats when using this mode.
-* **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero. When Rc=1 the CR element however is still stored in the CR regfile, even if the test failed. This scheme does not apply to crops (crand, cror). See appendix for details.
-
-Note that ffirst and reduce modes are not anticipated to be high-performance in some implementations. ffirst due to interactions with VL, and reduce due to it requiring additional operations to produce a result. normal, saturate and pred-result are however independent and may easily be parallelised to give high performance, regardless of the value of VL.
-
-The Mode table is laid out as follows:
-
-| 0-1 | 2 | 3 4 | description |
-| --- | --- |---------|-------------------------- |
-| 00 | 0 | sz dz | normal mode |
-| 00 | 1 | sz CRM | reduce mode (mapreduce), SUBVL=1 |
-| 00 | 1 | SVM CRM | subvector reduce mode, SUBVL>1 |
-| 01 | inv | CR-bit | Rc=1: ffirst CR sel |
-| 01 | inv | sz dz | Rc=0: ffirst z/nonz |
-| 10 | N | sz dz | sat mode: N=0/1 u/s |
-| 11 | inv | CR-bit | Rc=1: pred-result CR sel |
-| 11 | inv | sz dz | Rc=0: pred-result z/nonz |
-
-Fields:
-
-* **sz / dz** if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero. otherwise the element is ignored or skipped, depending on context.
-* **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1)
-* **CRM** affects the CR on reduce mode when Rc=1
-* **SVM** sets "subvector" reduce mode
-* **N** sets signed/unsigned saturation.
-
-# R\*\_EXTRA2 and R\*\_EXTRA3 Encoding
-
-EXTRA is the means by which two things are achieved:
-
-1. Registers are marked as either Vector *or Scalar*
-2. Register field numbers (limited typically to 5 bit)
- are extended in range, both for Scalar and Vector.
-
-In the following tables register numbers are constructed from the
-standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
-or EXTRA3 field from the SV Prefix. The prefixing is arranged so that
-interoperability between prefixing and nonprefixing of scalar registers
-is direct and convenient (when the EXTRA field is all zeros).
-
-A pseudocode algorithm explains the relationship, for INT/FP (see separate section for CRs)
-
- if extra3_mode:
- spec = EXTRA3
- else:
- spec = EXTRA2 << 1 # same as EXTRA3, shifted
- if spec[2]: # vector
- return (RA << 2) | spec[0:1]
- else: # scalar
- return (spec[0:1] << 5) | RA
-
-## INT/FP EXTRA3
-
-alternative which is understandable and, if EXTRA3 is zero, maps to
-"no effect" (scalar OpenPOWER ISA field naming). also, these are the
-encodings used in the original SV Prefix scheme. the reason why they
-were chosen is so that scalar registers in v3.0B and prefixed scalar
-registers have access to the same 32 registers.
-
-| R\*\_EXTRA3 | Mode | Range | MSB downto LSB |
-|-----------|-------|---------------|---------------------|
-| 000 | Scalar | `r0-r31` | `0b00 RA` |
-| 001 | Scalar | `r32-r63` | `0b01 RA` |
-| 010 | Scalar | `r64-r95` | `0b10 RA` |
-| 011 | Scalar | `r96-r127` | `0b11 RA` |
-| 100 | Vector | `r0-r124` | `RA 0b00` |
-| 101 | Vector | `r1-r125` | `RA 0b01` |
-| 110 | Vector | `r2-r126` | `RA 0b10` |
-| 111 | Vector | `r3-r127` | `RA 0b11` |
-
-## INT/FP EXTRA2
-
-alternative which is understandable and, if EXTRA2 is zero will map to
-"no effect" i.e Scalar OpenPOWER register naming:
-
-| R\*\_EXTRA2 | Mode | Range | MSB down to LSB |
-|-----------|-------|---------------|---------------------|
-| 00 | Scalar | `r0-r31` | `0b00 RA` |
-| 01 | Scalar | `r32-r63` | `0b01 RA` |
-| 10 | Vector | `r0-r124` | `RA 0b00` |
-| 11 | Vector | `r2-r126` | `RA 0b10` |
-
-## CR EXTRA3
-
-CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
-
- Encoding shown MSB down to LSB
-
-| R\*\_EXTRA3 | Mode | 7..5 | 4..2 | 1..0 |
-|-------------|------|---------| --------|---------|
-| 000 | Scalar | 0b000 | BA[4:2] | BA[1:0] |
-| 001 | Scalar | 0b001 | BA[4:2] | BA[1:0] |
-| 010 | Scalar | 0b010 | BA[4:2] | BA[1:0] |
-| 011 | Scalar | 0b011 | BA[4:2] | BA[1:0] |
-| 100 | Vector | BA[4:2] | 0b000 | BA[1:0] |
-| 101 | Vector | BA[4:2] | 0b010 | BA[1:0] |
-| 110 | Vector | BA[4:2] | 0b100 | BA[1:0] |
-| 111 | Vector | BA[4:2] | 0b110 | BA[1:0] |
-
-## CR EXTRA2
-
-CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
-
-Encoding shown MSB down to LSB
-
-| R\*\_EXTRA2 | Mode | 7..5 | 4..2 | 1..0 |
-|-------------|--------|---------|---------|---------|
-| 00 | Scalar | 0b000 | BA[4:2] | BA[1:0] |
-| 01 | Scalar | 0b001 | BA[4:2] | BA[1:0] |
-| 10 | Vector | BA[4:2] | 0b000 | BA[1:0] |
-| 11 | Vector | BA[4:2] | 0b100 | BA[1:0] |
-
-# ELWIDTH Encoding
-
-Default behaviour is set to 0b00 so that zeros follow the convention of
-"npt doing anything". In this case it means that elwidth overrides
-are not applicable. Thus if a 32 bit instruction operates on 32 bit,
-`elwidth=0b00` specifies that this behaviour is unmodified. Likewise
-when a processor is switched from 64 bit to 32 bit mode, `elwidth=0b00`
-states that, again, the behaviour is not to be modified.
-
-Only when elwidth is nonzero is the element width overridden to the
-explicitly required value.
-
-## Elwidth for Integers:
-
-| Value | Mnemonic | Description |
-|-------|----------------|------------------------------------|
-| 00 | DEFAULT | default behaviour for operation |
-| 01 | `ELWIDTH=b` | Byte: 8-bit integer |
-| 10 | `ELWIDTH=h` | Halfword: 16-bit integer |
-| 11 | `ELWIDTH=w` | Word: 32-bit integer |
-
-## Elwidth for FP Registers:
-
-| Value | Mnemonic | Description |
-|-------|----------------|------------------------------------|
-| 00 | DEFAULT | default behaviour for FP operation |
-| 01 | `ELWIDTH=bf16` | Reserved for `bf16` |
-| 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point |
-| 11 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
-
-Note:
-[`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
-is reserved for a future implementation of SV
-
-## Elwidth for CRs:
-
-TODO, important, particularly for crops, mfcr and mtcr, what elwidth
-even means. instead it may be possible to use the bits as extra indices
-(EXTRA6) to access the full 64 CRs. TBD, several ideas
-
-The actual width of the CRs cannot be altered: they are 4 bit. Also,
-for Rc=1 operations that produce a result (in RT or FRT) and corresponding CR, it is
-the INT/FP result to which the elwidth override applies, *not* the CR.
-This therefore inherently places Rc=1 operations firmly out of scope as far as a "meaning" for elwidth on CRs is concerned.
-
-As mentioned TBD, this leaves crops etc. to have a meaning defined for
-elwidth, because these ops are pure explicit CR based.
-
-Examples: mfxm may take the extra bits and use them as extra mask bits.
-
-# SUBVL Encoding
-
-the default for SUBVL is 1 and its encoding is 0b00 to indicate that
-SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
-lines up in combination with all other "default is all zeros" behaviour.
-
-| Value | Mnemonic | Subvec | Description |
-|-------|-----------|---------|------------------------|
-| 00 | `SUBVL=1` | single | Sub-vector length of 1 |
-| 01 | `SUBVL=2` | vec2 | Sub-vector length of 2 |
-| 10 | `SUBVL=3` | vec3 | Sub-vector length of 3 |
-| 11 | `SUBVL=4` | vec4 | Sub-vector length of 4 |
-
-The SUBVL encoding value may be thought of as an inclusive range of a
-sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore
-this may be considered to be elements 0b00 to 0b01 inclusive.
-
-# MASK/MASK_SRC & MASK_KIND Encoding
-
-One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two
-types may not be mixed.
-
-Special note: to get default behaviour (SV disabled) this field must
-be set to zero in combination with Integer Predication also being set
-to 0b000. this has the effect of enabling "all 1s" in the predicate
-mask, which is equivalent to "not having any predication at all"
-and consequently, in combination with all other default zeros, fully
-disables SV.
-
-| Value | Description |
-|-------|------------------------------------------------------|
-| 0 | MASK/MASK_SRC are encoded using Integer Predication |
-| 1 | MASK/MASK_SRC are encoded using CR-based Predication |
-
-Integer Twin predication has a second set of 3 bits that uses the same
-encoding thus allowing either the same register (r3 or r10) to be used
-for both src and dest, or different regs (one for src, one for dest).
-
-Likewise CR based twin predication has a second set of 3 bits, allowing
-a different test to be applied.
-
-## Integer Predication (MASK_KIND=0)
-
-When the predicate mode bit is zero the 3 bits are interpreted as below.
-Twin predication has an identical 3 bit field similarly encoded.
-
-| Value | Mnemonic | Element `i` enabled if: |
-|-------|----------|------------------------------|
-| 000 | ALWAYS | predicate effectively all 1s |
-| 001 | 1 << R3 | `i == R3` |
-| 010 | R3 | `R3 & (1 << i)` is non-zero |
-| 011 | ~R3 | `R3 & (1 << i)` is zero |
-| 100 | R10 | `R10 & (1 << i)` is non-zero |
-| 101 | ~R10 | `R10 & (1 << i)` is zero |
-| 110 | R30 | `R30 & (1 << i)` is non-zero |
-| 111 | ~R30 | `R30 & (1 << i)` is zero |
-
-## CR-based Predication (MASK_KIND=1)
-
-When the predicate mode bit is one the 3 bits are interpreted as below.
-Twin predication has an identical 3 bit field similarly encoded
-
-| Value | Mnemonic | Element `i` is enabled if |
-|-------|----------|--------------------------|
-| 000 | lt | `CR[offs+i].LT` is set |
-| 001 | nl/ge | `CR[offs+i].LT` is clear |
-| 010 | gt | `CR[offs+i].GT` is set |
-| 011 | ng/le | `CR[offs+i].GT` is clear |
-| 100 | eq | `CR[offs+i].EQ` is set |
-| 101 | ne | `CR[offs+i].EQ` is clear |
-| 110 | so/un | `CR[offs+i].FU` is set |
-| 111 | ns/nu | `CR[offs+i].FU` is clear |
-
-CR based predication. TODO: select alternate CR for twin predication? see
-[[discussion]] Overlap of the two CR based predicates must be taken
-into account, so the starting point for one of them must be suitably
-high, or accept that for twin predication VL must not exceed the range
-where overlap will occur, *or* that they use the same starting point
-but select different *bits* of the same CRs
-
-`offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
-
-# Appendix
-
-## XER, SO and other global flags
-
-Vector systems are expected to be high performance. This is achieved
-through parallelism, which requires that elements in the vector be
-independent. XER SO and other global "accumulation" flags (CR.OV) cause
-Read-Write Hazards on single-bit global resources, having a significant
-detrimental effect.
-
-Consequently in SV, XER.SO and CR.OV behaviour is disregarded (including in cmp ibstructions) . XER is
-simply neither read nor written. This includes when `scalar identity behaviour` occurs. If precise OpenPOWER v3.0/1 scalar behaviour is desired then OpenPOWER v3.0/1 instructions should be used without an SV Prefix.
-
-An interesting side-effect of this decision is that the OE flag is now free for other uses when SV Prefixing is used.
-
-Regarding XER.CA: this does not fit either: it was designed for a scalar ISA. Instead, both carry-in and carry-out go into the CR.so bit of a given Vector element. This provides a means to perform large parallel batches of Vectorised carry-capable additions. crweird instructions can be used to transfer the CRs in and out of an integer, where bitmanipulation may be performed to analyse the carry bits (including carry lookahead propagation) before continuing with further parallel additions.
-
-## v3.0B/v3.1B relevant instructions
-
-SV is primarily designed for use as an efficient hybrid 3D GPU / VPU / CPU ISA.
-
-As mentioned above, OE=1 is not applicable in SV, freeing this bit for alternative uses. Additionally, Vectorisation of the VSX SIMD system likewise makes no sense whatsoever. SV *replaces* VSX and provides, at the very minimum, predication (which VSX was designed without). Thus all VSX Major Opcodes - all of them - are "unused" and must raise illegal instruction exceptions in SV Prefix Mode.
-
-Likewise, `lq` (Load Quad), and Load/Store Multiple make no sense to have because they are not only provided by SV, the SV alternatives may be predicated as well, making them far better suited to use in function calls and context-switching.
-
-Additionally, some v3.0/1 instructions simply make no sense at all in a Vector context: `twi` and `tdi` fall into this category, as do branch operations as well as `sc` and `scv`. Here there is simply no point trying to Vectorise them: the standard OpenPOWER v3.0/1 instructions should be called instead.
-
-Fortuitously this leaves several Major Opcodes free for use by SV to fit alternative future instructions. In a 3D context this means Vector Product, Vector Normalise, [[sv/mv.swizzle]], Texture LD/ST operations, and others critical to an efficient, effective 3D GPU and VPU ISA. With such instructions being included as standard in other commercially-successful GPU ISAs it is likewise critical that a 3D GPU/VPU based on svp64 also have such instructions.
-
-Note however that svp64 is stand-alone and is in no way critically dependent on the existence or provision of 3D GPU or VPU instructions. These should be considered extensions, and their discussion and specification is out of scope for this document.
-
-Note, again: this is *only* under svp64 prefixing. Standard v3.0B / v3.1B is *not* altered by svp64 in any way.
-
-### Major opcode map (v3.0B)
-
-This table is taken from v3.0B.
-Table 9: Primary Opcode Map (opcode bits 0:5)
-
- | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
- 000 | | | tdi | twi | EXT04 | | | mulli | 000
- 001 | subfic | | cmpli | cmpi | addic | addic. | addi | addis | 001
- 010 | bc/l/a | EXT17 | b/l/a | EXT19 | rlwimi| rlwinm | | rlwnm | 010
- 011 | ori | oris | xori | xoris | andi. | andis. | EXT30 | EXT31 | 011
- 100 | lwz | lwzu | lbz | lbzu | stw | stwu | stb | stbu | 100
- 101 | lhz | lhzu | lha | lhau | sth | sthu | lmw | stmw | 101
- 110 | lfs | lfsu | lfd | lfdu | stfs | stfsu | stfd | stfdu | 110
- 111 | lq | EXT57 | EXT58 | EXT59 | EXT60 | EXT61 | EXT62 | EXT63 | 111
- | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
-
-### Suitable for svp64
-
-This is the same table containing v3.0B Primary Opcodes except those that make mo sense in a Vectorisation Context have been removed. These removed POs can, *in the SV Vector Context only*, be assigned to alternative (Vectorised-only) instructions, including future extensions.
-
-Note, again, to emphasise: outside of svp64 these opcodes **do not** change. When not prefixed with svp64 these opcodes **specifically** retain their v3.0B / v3.1B OpenPOWER Standard compliant meaning.
-
- | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
- 000 | | | | | | | | mulli | 000
- 001 | subfic | | cmpli | cmpi | addic | addic. | addi | addis | 001
- 010 | | | | EXT19 | rlwimi| rlwinm | | rlwnm | 010
- 011 | ori | oris | xori | xoris | andi. | andis. | EXT30 | EXT31 | 011
- 100 | lwz | lwzu | lbz | lbzu | stw | stwu | stb | stbu | 100
- 101 | lhz | lhzu | lha | lhau | sth | sthu | | | 101
- 110 | lfs | lfsu | lfd | lfdu | stfs | stfsu | stfd | stfdu | 110
- 111 | | | EXT58 | EXT59 | | EXT61 | | EXT63 | 111
- | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
-
-## Twin Predication
-
-This is a novel concept that allows predication to be applied to a single
-source and a single dest register. The following types of traditional
-Vector operations may be encoded with it, *without requiring explicit
-opcodes to do so*
-
-* VSPLAT (a single scalar distributed across a vector)
-* VEXTRACT (like LLVM IR [`extractelement`](https://releases.llvm.org/11.0.0/docs/LangRef.html#extractelement-instruction))
-* VINSERT (like LLVM IR [`insertelement`](https://releases.llvm.org/11.0.0/docs/LangRef.html#insertelement-instruction))
-* VCOMPRESS (like LLVM IR [`llvm.masked.compressstore.*`](https://releases.llvm.org/11.0.0/docs/LangRef.html#llvm-masked-compressstore-intrinsics))
-* VEXPAND (like LLVM IR [`llvm.masked.expandload.*`](https://releases.llvm.org/11.0.0/docs/LangRef.html#llvm-masked-expandload-intrinsics))
-
-Those patterns (and more) may be applied to:
-
-* mv (the usual way that V\* ISA operations are created)
-* exts\* sign-extension
-* rwlinm and other RS-RA shift operations (**note**: excluding
- those that take RA as both a src and dest. These are not
- 1-src 1-dest, they are 2-src, 1-dest)
-* LD and ST (treating AGEN as one source)
-* FP fclass, fsgn, fneg, fabs, fcvt, frecip, fsqrt etc.
-* Condition Register ops mfcr, mtcr and other similar
-
-This is a huge list that creates extremely powerful combinations,
-particularly given that one of the predicate options is `(1<<r3)`
-
-Additional unusual capabilities of Twin Predication include a back-to-back
-version of VCOMPRESS-VEXPAND which is effectively the ability to do
-sequentially ordered multiple VINSERTs. The source predicate selects a
-sequentially ordered subset of elements to be inserted; the destination predicate specifies the sequentially ordered recipient locations.
-This is equivalent to
-`llvm.masked.compressstore.*`
-followed by
-`llvm.masked.expandload.*`
-
-## Rounding, clamp and saturate
-
-see [[av_opcodes]].
-
-To help ensure that audio quality is not compromised by overflow,
-"saturation" is provided, as well as a way to detect when saturation
-occurred if desired (Rc=1). When Rc=1 there will be a *vector* of CRs, one CR per
-element in the result (Note: this is different from VSX which has a
-single CR per block).
-
-When N=0 the result is saturated to within the maximum range of an
-unsigned value. For integer ops this will be 0 to 2^elwidth-1. Similar
-logic applies to FP operations, with the result being saturated to
-maximum rather than returning INF, and the minimum to +0.0
-
-When N=1 the same occurs except that the result is saturated to the min
-or max of a signed result, and for FP to the min and max value rather than returning +/- INF.
-
-When Rc=1, the CR "overflow" bit is set on the CR associated with the
-element, to indicate whether saturation occurred. Note that due to
-the hugely detrimental effect it has on parallel processing, XER.SO is
-**ignored** completely and is **not** brought into play here. The CR
-overflow bit is therefore simply set to zero if saturation did not occur,
-and to one if it did.
-
-Note also that saturate on operations that produce a carry output are prohibited due to the conflicting use of the CR.so bit for storing if saturation occurred.
-
-Post-analysis of the Vector of CRs to find out if any given element hit
-saturation may be done using a mapreduced CR op (cror), or by using the
-new crweird instruction, transferring the relevant CR bits to a scalar
-integer and testing it for nonzero. see [[sv/cr_int_predication]]
-
-Note that the operation takes place at the maximum bitwidth (max of src and dest elwidth) and that truncation occurs to the range of the dest elwidth.
-
-## Reduce mode
-
-1. limited to single predicated dual src operations (add RT, RA, RB).
- triple source operations are prohibited (fma).
-2. limited to operations that make sense. divide is excluded, as is
- subtract (X - Y - Z produces different answers depending on the order)
- and asymmetric CRops (crandc, crorc). sane operations:
- multiply, min/max, add, logical bitwise OR, most other CR ops.
- operations that do have the same source and dest register type are
- also excluded (isel, cmp). operations involving carry or overflow
- (XER.CA / OV) are also prohibited.
-3. the destination is a vector but the result is stored, ultimately,
- in the first nonzero predicated element. all other nonzero predicated
- elements are undefined. *this includes the CR vector* when Rc=1
-4. implementations may use any ordering and any algorithm to reduce
- down to a single result. However it must be equivalent to a straight
- application of mapreduce. The destination vector (except masked out
- elements) may be used for storing any intermediate results. these may
- be left in the vector (undefined).
-5. CRM applies when Rc=1. When CRM is zero, the CR associated with
- the result is regarded as a "some results met standard CR result
- criteria". When CRM is one, this changes to "all results met standard
- CR criteria".
-6. implementations MAY use destoffs as well as srcoffs (see [[sv/sprs]])
- in order to store sufficient state to resume operation should an
- interrupt occur. this is also why implementations are permitted to use
- the destination vector to store intermediary computations
-7. *Predication may be applied*. zeroing mode is not an option. masked-out
- inputs are ignored; masked-out elements in the destination vector are
- unaltered (not used for the purposes of intermediary storage); the
- scalar result is placed in the first available unmasked element.
-
-Pseudocode for the case where RA==RB:
-
- result = op(iregs[RA], iregs[RA+1])
- CR = analyse(result)
- for i in range(2, VL):
- result = op(result, iregs[RA+i])
- CRnew = analyse(result)
- if Rc=1
- if CRM:
- CR = CR bitwise or CRnew
- else:
- CR = CR bitwise AND CRnew
-
-TODO: case where RA!=RB which involves first a vector of 2-operand
-results followed by a mapreduce on the intermediates.
-
-Note that when SVM is clear and SUBVL!=1 the sub-elements are *independent*, i.e. they
-are mapreduced per *sub-element* as a result. illustration with a vec2:
-
- result.x = op(iregs[RA].x, iregs[RA+1].x)
- result.y = op(iregs[RA].y, iregs[RA+1].y)
- for i in range(2, VL):
- result.x = op(result.x, iregs[RA+i].x)
- result.y = op(result.y, iregs[RA+i].y)
-
-Note here that Rc=1 does not make sense when SVM is clear and SUBVL!=1.
-
-
-When SVM is set and SUBVL!=1, another variant is enabled: horizontal subvector mode. Example for a vec3:
-
- for i in range(VL):
- result = op(iregs[RA+i].x, iregs[RA+i].x)
- result = op(result, iregs[RA+i].y)
- result = op(result, iregs[RA+i].z)
- iregs[RT+i] = result
-
-In this mode, when Rc=1 the Vector of CRs is as normal: each result element creates a corresponding CR element.
-
-## Fail-on-first
-
-Data-dependent fail-on-first has two distinct variants: one for LD/ST,
-the other for arithmetic operations (actually, CR-driven). Note in each
-case the assumption is that vector elements are required appear to be
-executed in sequential Program Order, element 0 being the first.
-
-* LD/ST ffirst treats the first LD/ST in a vector (element 0) as an
- ordinary one. Exceptions occur "as normal". However for elements 1
- and above, if an exception would occur, then VL is **truncated** to the
- previous element.
-* Data-driven (CR-driven) fail-on-first activates when Rc=1 or other
- CR-creating operation produces a result (including cmp). Similar to
- branch, an analysis of the CR is performed and if the test fails, the
- vector operation terminates and discards all element operations at and
- above the current one, and VL is truncated to the *previous* element.
- Thus the new VL comprises a contiguous vector of results, all of which
- pass the testing criteria (equal to zero, less than zero).
-
-The CR-based data-driven fail-on-first is new and not found in ARM SVE
-or RVV. It is extremely useful for reducing instruction count, however
-requires speculative execution involving modifications of VL to get high
-performance implementations.
-
-In CR-based data-driven fail-on-first there is only the option to select
-and test one bit of each CR (just as with branch BO). For more complex
-tests this may be insufficient. If that is the case, a vectorised crops
-(crand, cror) may be used, and ffirst applied to the crop instead of to
-the arithmetic vector.
-
-One extremely important aspect of ffirst is:
-
-* LDST ffirst may never set VL equal to zero. This because on the first
- element an exception must be raised "as normal".
-* CR-based data-dependent ffirst on the other hand **can** set VL equal
- to zero. This is the only means in the entirety of SV that VL may be set
- to zero (with the exception of via the SV.STATE SPR). When VL is set
- zero due to the first element failing the CR bit-test, all subsequent
- vectorised operations are effectively `nops` which is
- *precisely the desired and intended behaviour*.
-
-Another aspect is that for ffirst LD/STs, VL may be truncated arbitrarily to a nonzero value for any implementation-specific reason. For example: it is perfectly reasonable for implementations to alter VL when ffirst LD or ST operations are initiated on a nonaligned boundary, such that within a loop the subsequent iteration of that loop begins subsequent ffirst LD/ST operations on an aligned boundary. Likewise, to reduce workloads or balance resources.
-
-CR-based data-dependent first on the other hand MUST not truncate VL arbitrarily. This because it is a precise test on which algorithms will rely.
-
-## pred-result mode
-
-This mode merges common CR testing with predication, saving on instruction count. Below is the pseudocode excluding predicate zeroing and elwidth overrides.
-
- for i in range(VL):
- # predication test, skip all masked out elements.
- if predicate_masked_out(i):
- continue
- result = op(iregs[RA+i], iregs[RB+i])
- CRnew = analyse(result) # calculates eq/lt/gt
- # Rc=1 always stores the CR
- if Rc=1:
- crregs[offs+i] = CRnew
- # now test CR, similar to branch
- if CRnew[BO[0:1]] != BO[2]:
- continue # test failed: cancel store
- # result optionally stored but CR always is
- iregs[RT+i] = result
-
-The reason for allowing the CR element to be stored is so that post-analysis
-of the CR Vector may be carried out. For example: Saturation may have occurred (and been prevented from updating, by the test) but it is desirable to know *which* elements fail saturation.
-
-Note that predication is still respected: predicate zeroing is slightly different: elements that fail the CR test *or* are masked out are zero'd.
-
-## CR Operations
-
-CRs are slightly more involved than INT or FP registers due to the
-possibility for indexing individual bits (crops BA/BB/BT). Again however
-the access pattern needs to be understandable in relation to v3.0B / v3.1B
-numbering, with a clear linear relationship and mapping existing when
-SV is applied.
-
-### CR EXTRA mapping table and algorithm
-
-Numbering relationships for CR fields are already complex due to being
-in BE format (*the relationship is not clearly explained in the v3.0B
-or v3.1B specification*). However with some care and consideration
-the exact same mapping used for INT and FP regfiles may be applied,
-just to the upper bits, as explained below.
-
-In OpenPOWER v3.0/1, BF/BT/BA/BB are all 5 bits. The top 3 bits (2:4)
-select one of the 8 CRs; the bottom 2 bits (0:1) select one of 4 bits
-*in* that CR. The numbering was determined (after 4 months of
-analysis and research) to be as follows:
-
- CR_index = 7-(BA>>2) # top 3 bits but BE
- bit_index = 3-(BA & 0b11) # low 2 bits but BE
- CR_reg = CR[CR_index] # get the CR
- # finally get the bit from the CR.
- CR_bit = (CR_reg & (1<<bit_index)) != 0
-
-When it comes to applying SV, it is the CR\_reg number to which SV EXTRA2/3
-applies, **not** the CR\_bit portion (bits 0:1):
-
- if extra3_mode:
- spec = EXTRA3
- else:
- spec = EXTRA2<<1 | 0b0
- if spec[2]:
- # vector constructs "BA[2:4] spec[0:1] 0 BA[0:1]"
- return ((BA >> 2)<<5) | # hi 3 bits shifted up
- (spec[0:1]<<3) | # to make room for these
- (BA & 0b11) # CR_bit on the end
- else:
- # scalar constructs "0 spec[0:1] BA[0:4]"
- return (spec[0:1] << 5) | BA
-
-Thus, for example, to access a given bit for a CR in SV mode, the v3.0B
-algorithm to determin CR\_reg is modified to as follows:
-
- CR_index = 7-(BA>>2) # top 3 bits but BE
- if spec[2]:
- # vector mode
- CR_index = (CR_index<<3) | (spec[0:1] << 1)
- else:
- # scalar mode
- CR_index = (spec[0:1]<<3) | CR_index
- # same as for v3.0/v3.1 from this point onwards
- bit_index = 3-(BA & 0b11) # low 2 bits but BE
- CR_reg = CR[CR_index] # get the CR
- # finally get the bit from the CR.
- CR_bit = (CR_reg & (1<<bit_index)) != 0
-
-Note here that the decoding pattern to determine CR\_bit does not change.
-
-Note: high-performance implementations may read/write Vectors of CRs in
-batches of aligned 32-bit chunks (CR0-7, CR7-15). This is to greatly
-simplify internal design. If instructions are issued where CR Vectors
-do not start on a 32-bit aligned boundary, performance may be affected.
-
-### CR fields as inputs/outputs of vector operations
-
-CRs (or, the arithmetic operations associated with them)
-may be marked as Vectorised or Scalar. When Rc=1 in arithmetic operations that have no explicit EXTRA to cover the CR, the CR is Vectorised if the destination is Vectorised. Likewise if the destination is scalar then so is the CR.
-
-When vectorized, the CR inputs/outputs are sequentially read/written
-to 4-bit CR fields. Vectorised Integer results, when Rc=1, will begin
-writing to CR8 (TBD evaluate) and increase sequentially from there.
-This is so that:
-
-* implementations may rely on the Vector CRs being aligned to 8. This
- means that CRs may be read or written in aligned batches of 32 bits
- (8 CRs per batch), for high performance implementations.
-* scalar Rc=1 operation (CR0, CR1) and callee-saved CRs (CR2-4) are not
- overwritten by vector Rc=1 operations except for very large VL
-* CR-based predication, from CR32, is also not interfered with
- (except by large VL).
-
-However when the SV result (destination) is marked as a scalar by the
-EXTRA field the *standard* v3.0B behaviour applies: the accompanying
-CR when Rc=1 is written to. This is CR0 for integer operations and CR1
-for FP operations.
-
-Note that yes, the CRs are genuinely Vectorised. Unlike in SIMD VSX which
-has a single CR (CR6) for a given SIMD result, SV Vectorised OpenPOWER
-v3.0B scalar operations produce a **tuple** of element results: the
-result of the operation as one part of that element *and a corresponding
-CR element*. Greatly simplified pseudocode:
-
- for i in range(VL):
- # calculate the vector result of an add
- iregs[RT+i] = iregs[RA+i] + iregs[RB+i]
- # now calculate CR bits
- CRs[8+i].eq = iregs[RT+i] == 0
- CRs[8+i].gt = iregs[RT+i] > 0
- ... etc
-
-If a "cumulated" CR based analysis of results is desired (a la VSX CR6)
-then a followup instruction must be performed, setting "reduce" mode on
-the Vector of CRs, using cr ops (crand, crnor)to do so. This provides far
-more flexibility in analysing vectors than standard Vector ISAs. Normal
-Vector ISAs are typically restricted to "were all results nonzero" and
-"were some results nonzero". The application of mapreduce to Vectorised
-cr operations allows far more sophisticated analysis, particularly in
-conjunction with the new crweird operations see [[sv/cr_int_predication]].
-
-Note in particular that the use of a separate instruction in this way
-ensures that high performance multi-issue OoO inplementations do not
-have the computation of the cumulative analysis CR as a bottleneck and
-hindrance, regardless of the length of VL.
-
-(see [[discussion]]. some alternative schemes are described there)
-
-### Rc=1 when SUBVL!=1
-
-sub-vectors are effectively a form of SIMD (length 2 to 4). Only 1 bit of predicate is allocated per subvector; likewise only one CR is allocated
-per subvector.
-
-This leaves a conundrum as to how to apply CR computation per subvector, when normally Rc=1 is exclusively applied to scalar elements. A solution is to perform a bitwise OR or AND of the subvector tests. Given that OE is ignored, rhis field may (when available) be used to select OR or AND behavior.
-
-### Table of CR fields
-
-CR[i] is the notation used by the OpenPower spec to refer to CR field #i,
-so FP instructions with Rc=1 write to CR[1] aka SVCR1_000.
-
-CRs are not stored in SPRs: they are registers in their own right.
-Therefore context-switching the full set of CRs involves a Vectorised
-mfcr or mtcr, using VL=64, elwidth=8 to do so. This is exactly as how scalar OpenPOWER context-switches CRs: it is just that there are now more of them.
-
-The 64 SV CRs are arranged similarly to the way the 128 integer registers
-are arranged. TODO a python program that auto-generates a CSV file
-which can be included in a table, which is in a new page (so as not to
-overwhelm this one). [[svp64/cr_names]]
-
-## Register Profiles
-
-**NOTE THIS TABLE SHOULD NO LONGER BE HAND EDITED** see
-<https://bugs.libre-soc.org/show_bug.cgi?id=548> for details.
-
-Instructions are broken down by Register Profiles as listed in the
-following auto-generated page: [[opcode_regs_deduped]]. "Non-SV"
-indicates that the operations with this Register Profile cannot be
-Vectorised (mtspr, bc, dcbz, twi)
-
-TODO generate table which will be here [[svp64/reg_profiles]]
-
-## SV pseudocode illilustration
-
-### Single-predicated Instruction
-
-illustration of normal mode add operation: zeroing not included, elwidth overrides not included. if there is no predicate, it is set to all 1s
-
- function op_add(rd, rs1, rs2) # add not VADD!
- int i, id=0, irs1=0, irs2=0;
- predval = get_pred_val(FALSE, rd);
- for (i = 0; i < VL; i++)
- STATE.srcoffs = i # save context
- if (predval & 1<<i) # predication uses intregs
- ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
- if (!int_vec[rd ].isvec) break;
- if (rd.isvec) { id += 1; }
- if (rs1.isvec) { irs1 += 1; }
- if (rs2.isvec) { irs2 += 1; }
- if (id == VL or irs1 == VL or irs2 == VL) {
- # end VL hardware loop
- STATE.srcoffs = 0; # reset
- return;
- }
-
-This has several modes:
-
-* RT.v = RA.v RB.v
-* RT.v = RA.v RB.s (and RA.s RB.v)
-* RT.v = RA.s RB.s
-* RT.s = RA.v RB.v
-* RT.s = RA.v RB.s (and RA.s RB.v)
-* RT.s = RA.s RB.s
-
-All of these may be predicated. Vector-Vector is straightfoward. When one of source is a Vector and the other a Scalar, it is clear that each element of the Vector source should be added to the Scalar source, each result placed into the Vector (or, if the destination is a scalar, only the first nonpredicated result).
-
-The one that is not obvious is RT=vector but both RA/RB=scalar. Here this acts as a "splat scalar result", copying the same result into all nonpredicated result elements. If a fixed destination scalar was intended, then an all-Scalar operation should be used.
-
-See <https://bugs.libre-soc.org/show_bug.cgi?id=552>
-
-## Assembly Annotation
-
-Assembly code annotation is required for SV to be able to successfully
-mark instructions as "prefixed".
-
-A reasonable (prototype) starting point:
-
- svp64 [field=value]*
-
-Fields:
-
-* ew=8/16/32 - element width
-* sew=8/16/32 - source element width
-* vec=2/3/4 - SUBVL
-* mode=reduce/satu/sats/crpred
-* pred=1\<\<3/r3/~r3/r10/~r10/r30/~r30/lt/gt/le/ge/eq/ne
-* spred={reg spec}
-
-similar to x86 "rex" prefix.
+++ /dev/null
-# CR names
-
-TODO autogenerate CSV file to be included here
+++ /dev/null
-
-# Note about naming
-
-the original assessment for SVP from 18 months ago concluded that it should be easy for scalar (non SV) instructions to get at the exact same scalar registers when in SVP mode. otherwise scalar v3.0B code needs to restrict itself to a massively truncated subset of the scalar registers numbered 0-31 (only r0, r4, r8...) which hugely interferes with ABIs to such an extent that it would compromise SV.
-
-question: has anything changed about the assessment that was done, which concluded that for scalar SVP regs they should overlap completely with scalar ISA regs?
-
-
-# Notes on requirements for bit allocations
-
-do not try to jam VL or MAXVL in. go with the flow of 24 bits spare.
-
-* 2: SUBVL
-* 2: elwidth
-* 2: twin-predication (src, dest) elwidth
-* 1: select INT or CR predication
-* 3: predicate selection and inversion (QTY 2 for tpred)
-* 4x2 or 3x3: src1/2/3/dest Vector/Scalar reg
-* 5: mode
-
-totals: 24 bits (dest elwidth shared)
-
-http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001434.html
-
-## All zeros indicates "disable SVP"
-
-The defaults for all capabilities of SVP should be zero to indicate "no action". SUBVL=1 encoded as 0b00. register name prefixes, scalar=0b0, elwidth overrides DEFAULT=0b00, predication off=0b000 etc.
-
-this way SV may be entirely disabled, leaving an "all zeros" to indicate to v3.1B 64bit prefixing that the standard OpenPOWER v3.1B encodings are in full effect (and that SV is not). As all zeros meshes with current "reserved" encodings this should work well.
-
-
-## twin predication
-
-twin predication and twin elwidth overrides is extremely important to have to be able to override both the src and dest elwidth yet keep the underlying scalar operation intact. examples include mr with an elwidth=8, VL=8 on the src will take a byte at a time from one 64 bit reg and place it into 8x 64-bit regs, zero-extended. more complex operations involve SUBVL and Audio/Video DSP operations, see [[av_opcodes]]
-
-something like:
-
-| 0 1 | 2 3 | 4 5 | 6 | 7 9 | 10 12 | 13 18 | 19 23 |
-|-------|-----|-----|------|------|-------|-------|-------|
-| subvl | sew | dew | ptyp | psrc | pdst | vspec | mode |
-
-table:
-
-* subvl - 1 to 4 scalar / vec2 / vec3 / vec4
-* sew / dew - DEFAULT / 8 / 16 /32 element width
-* ptyp - predication INT / CR
-* psrc / pdst - predicate mask selector and inversion
-* vspec - 3 bit src / dest scalar-vector extension
-* mode: 5 bits
-
-## twin predication, CR based.
-
-separate src and dest predicates are a critical part of SV for provision of VEXPAND, VCOMPRESS, VSPLAT, VINSERT and many more operations.
-
-Twin CR predication could be done in two ways:
-
-* start from different CRs for the src and dest
-* start from the same CR.
-
-With different bits being selectable (CR[0..3]) starting from the same CR makes some sense.
-
-# standard arith ops (single predication)
-
-these are of the form res = op(src1, src2, ...)
-
-| 0 1 | 2 3 | 4 5 | 6 | 7 9 | 10 18 | 19 23 |
-|-------|-----|-----|------|------|-------|--------|
-| subvl | sew | dew | ptyp | pred | vspec | mode |
-
-table:
-
-* subvl - 1 to 4 scalar / vec2 / vec3 / vec4
-* sew / dew - DEFAULT / 8 / 16 /32 element width
-* ptyp - predication INT / CR
-* pred - predicate mask selector and inversion
-* vspec - 2/3 bit src / dest scalar-vector extension
-* mode - 5 bit
-
-For 2 op (dest/src1/src2) the tag may be 3 bits: total 9 bits. for 3 op (dest/src1/2/3) the vspec may be 2 bits per reg: total 8 bits.
-
-Note:
-
-* the operation should always be done at max(srcwidth, dstwidth), unless it can
- be proven using the lower will lead to the same result
-* saturation is done on the result at the **dest** elwidth
-
-Some examples on different operation widths:
-
- u16 / u16 = u8
- 256 / 2 = 128 # if we used the smaller width, we'd get 0. Wrong
-
- u8 * u8 = u16
- 255 * 2 = 510 # if we used the smaller width, we'd get 254. Wrong
-
- u16 + u16 = u8
- 256 + 2 = 2 # this is correct whether we use the larger or smaller width
- # aka hw can optimize narrowing addition
-
-
-# Notes about Swizzle
-
-Basically, there isn't enough room to try to fit two src src1/2 swizzle, and SV, even into 64 bit (actually 24) without severely compromising on the number of bits allocated to either swizzle, or SV, or both.
-
-therefore the strategy proposed is:
-
-* design 16bit scalar ops
-* use the 11 bit old SV prefix to create 32bit insns
-* when those are embedded into v3.1B 64 prefix, the 24 bits are entirely allocated to swizzle.
-
-with 2x12 this would mean no need to have complex encoding of swizzle.
-
-if we really do need 2 bits spare then the complex encoder of swizzle could be deployed. (*an analysis shows this to be very unlikely. 7^4 is around 2400 which still requires 12 bits to encode* (that's miscalculated, see Single Swizzle section below.) it isn't because you missed out predicate mask skip as thr 7th option.)
-
-## Single Swizzle
-
-I expect swizzle to not be common enough to warrant 2 swizzles in a single instruction, therefor the above swizzle strategy is probably unnecessary.
-
-Also, if a swizzle supports up to subvl=4, then 11 bits is sufficient since each swizzle element needs to be able to select 1 of 6 different values: 0, 1, x, y, z, w. 6^4 = 1296 which easily fits in 11 bits (only by dropping "predicate mask" from the list of options, which makes 7 options not 6. see [[mv.swizzle]])
-
-What about subvl=4 that skips one element? src vec is 4 but one of the elements is to be left alone? This is not 6 options, it is 7 options (including "skip" i.e combining with a predicate mask in effect). note that this is not the same as a vec3-with-a-skip
-
-What could hypothetically be done is: when SUBVL=3 a different encoding is used, one that allows the "skip" to be specified. X Y skip W for example. this would then be interpreted, "actually the vector is vec4 but one rlement is skipped"
-
-the problem with that is that now SUBVL has become critically dependent on the swizzle, worse than that the swizzle is embedded in the instruction, even worse than that it's encoded in a complex multi-gate fashion.
-
-all of which screams, "this is going in completely the wrong direction". keep it simple. 7 options, 3 bits, 4x3, 12 bits for swizzle, ignore some if SUBVL is 1 2 or 3.
-
-# note about INT predicate
-
-001 ALWAYS (implicit) Operation is not masked
-
-this means by default that 001 will always be in nonpredicated ops, which seems anomalous. would 000 be better to indicate "no predication"?
-
-000 would indicate "the predicate is an immediate of all 1s" i.e. "no operation is masked out"
-
-programmerjake:
-I picked 0001 to indicate ALWAYS since that matches with the other semantics: the LSB bit is invert-the-mask, and you can think about the table as-if it is really:
-
-this is the opposite of what feels natural. inversion should switch *off* something. also 000 is the canonical "this feature is off by default" number.
-
-the constant should be an immediate of all 1s (not r0), which is the natural way to think of "predication is off".
-
-i get the idea "r0 to be used therefore it is all zeros" but that makes 001 the "default", not 000.
-
-| Value | Mnemonic |
-|-------|-------------|
-| 000 | R0 (zero) set to all 1s, naturally means "no predication" |
-| 001 | ~R0 (~zero) |
-| 010 | R3 |
-| 011 | ~R3 |
-| 100 | R10 |
-| 101 | ~R10 |
-| 110 | R30 |
-| 111 | ~R30 |
-
-
-# CR Vectorisation
-
-Some thoughts on this: the sensible (sane) number of CRs to have is 64. A case could be made for having 128 but it is an awful lot. 64 CRs also has the advantage that it is only 4x 64 bit registers on a context-switch (programmerjake: yeah, but we already have 256 64-bit registers, a few more won't change much).
-
-A practical issue stems from the fact that accessing the CR regfile on a non-aligned 8-CR boundary during Vector operations would significantly increase internal routing. By aligning Vector Reads/Writes to 8 CRs this requires only 32 bit aligned read/writes. (programmerjake: simple solution -- rename them internally such that CR6 is the first one)
-
-How to number them as vectors gets particularly interesting. A case could be made for treating the 64 CRs as a square, and using CR numbering (CR0-7) to begin VL for-loop incrementing first by row and when rolling over to increment the column. CR6 CR14 ... CR62 then CR7 CR15 ...
-
-When the SV prefix marks them with 2 bits, one of those could be used to indicate scalar, and the other to indicate whether the 3 bit CR number is to be treated as a horizontal vector (CR incrementing straight by 1) or a vertical vector (incrementing by 8)
-
-When there are 3 bits it would be possible to indicate whether to begin from a position offset by 4 (middle of matrix, edge of matrix).
-
-Note: considerable care needs to be taken when putting these horiz/vertical CRs through the Dependency Matrices
-
-Indexing algorithm illustrating how the H/V modes would work. Note that BA is the 3 bit CR register field that normsll, in scalar ISA, would reference only CR0-7 as CR[BA].
-
- for i in range(VL)
- y = i % 8
- x = i // 8
- if verticalmode:
- CRINDEX = BA + y*8 + x
- else:
- CRINDEX = BA*8 + i
- CR[CRINDEX] = ...
-
-# Should twin-predication (src=1, dest=1) have DEST SUBVL?
-
-this is tricky: there isn't really enough space unless the reg scalar-vector extension (currently 3 bits per reg) is compacted to only 2 bits each, which would provide 2 extra bits.
-
-so before adding this, an evaluation is needed: *is it necessary*?
-
-what actual operations out of this list need - and work - with a separate SRC and DEST SUBVL?
-
-* mv (the usual way that V* operations are created)
-* exts* sign-extension
-* rwlinm and other RS-RA shift operations
-* LD and ST (treating AGEN as one source)
-* FP fclass, fsgn, fneg, fabs, fcvt, frecip, fsqrt etc.
-* Condition Register ops mfcr, mtcr and other similar
-
-Evaluation:
-
-* mv: yes. these may need merge/split
-* exts: no. no transformation.
-* rwlinm shift operations: no
-* LD and ST: no
-* FP ops: no
-* CR ops: maybe on mvs, not on arithmetic.
-
-therefore it makes no sense to have DEST SUBVL, and instead to have special mv operations. see [[mv.vec]]
+++ /dev/null
-# table to be autogenerated
-
-## LDST-1R-1W-imm
-
-`RM-2P-1S1D`
-
-LD immediate
-
-## LDST-1R-2W-imm
-
-LD immediate with update
-
-## LDST-2R-imm
-
-ST immediate
-
-## LDST-2R-1W
-
-`RM-2P-2S1D`
-
-LD Indexed with update
-
-## LDST-2R-1W-imm
-
-ST Indexed with update
-
-## LDST-2R-2W
-
-LD Indexed with update
-
-## LDST-3R
-
-ST Indexed
-
-## LDST-3R-CRo
-
-ST Indexed cache
-
-## LDST-3R-1W
-
-ST Indexed with update
-
-## CRio
-TBD
-## CR=2R1W
-
-Remapped Encoding Fields: `RM-1P-2S1D`
-
-
-## 1W-CRi
-
-Remapped Encoding Fields: `RM-2P-1S1D`
-
-
-
-## 1R-CRo
-
-Remapped Encoding Fields: `RM-2P-1S1D`
-
-
-## 1R-CRio
-
-Remapped Encoding Fields: `RM-2P-1S1D`
-
-
-
-## 1R-1W
-
-Remapped Encoding Fields: `RM-2P-1S1D`
-
-
-## 1R-1W-imm
-
-Remapped Encoding Fields: `RM-2P-1S1D`
-
-
-
-## 1R-1W-CRo
-
-Remapped Encoding Fields: `RM-2P-1S1D`
-
-
-
-## 1R-1W-CRio
-
-Remapped Encoding Fields: `RM-2P-1S1D`
-
-
-
-## 2R-CRo
-
-Remapped Encoding Fields: `RM-1P-2S1D`
-# table to be autogenerated
-
-
-## 2R-CRio
-
-Remapped Encoding Fields: `RM-1P-2S1D`
-
-
-
-## 2R-1W
-
-Remapped Encoding Fields: `RM-1P-2S1D`
-
-
-
-## 2R-1W-CRo
-
-Remapped Encoding Fields: `RM-1P-2S1D`
-
-*Note that analysis of `rl(w|d)imi` shows that these are correctly identified as 2S1D. The pseudocode in [[isa/fixedshift]] although RA is used as both a src and a dest the EXTRA3 extension of each of these gives different meanings to the src RA and dest RA.*
-
-
-## 2R-1W-CRi
-TBD
-
-## 2R-1W-CRio
-
-Remapped Encoding Fields: `RM-1P-2S1D`
-
-
-
-## 3R-1W-CRio
-
-Remapped Encoding Fields: `RM-1P-3S1D`
-
projects / libreriscv.git / commitdiff