Fixed sharing of reduce operator
authorClifford Wolf <clifford@clifford.at>
Fri, 8 Aug 2014 12:24:09 +0000 (14:24 +0200)
committerClifford Wolf <clifford@clifford.at>
Fri, 8 Aug 2014 12:24:09 +0000 (14:24 +0200)
passes/sat/share.cc

index 0c88b4d3cca7b4c199fafc42fc5f8c7a3baee57a..7141cea2ad224dfac397d4e1433c55a8218fdda2 100644 (file)
@@ -252,6 +252,19 @@ struct ShareWorker
 
                if (config.generic_uni_ops.count(c1->type))
                {
+                       if (c1->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool") && c1->getParam("\\A_WIDTH").as_int() != c2->getParam("\\A_WIDTH").as_int())
+                       {
+                               RTLIL::SigBit extbit = c1->type == "$reduce_and" ? RTLIL::State::S1 : RTLIL::State::S0;
+                               while (c1->getParam("\\A_WIDTH").as_int() < c2->getParam("\\A_WIDTH").as_int()) {
+                                       c1->setParam("\\A_WIDTH", c1->getParam("\\A_WIDTH").as_int() + 1);
+                                       c1->setPort("\\A", {extbit, c1->getPort("\\A")});
+                               }
+                               while (c2->getParam("\\A_WIDTH").as_int() < c1->getParam("\\A_WIDTH").as_int()) {
+                                       c2->setParam("\\A_WIDTH", c2->getParam("\\A_WIDTH").as_int() + 1);
+                                       c2->setPort("\\A", {extbit, c2->getPort("\\A")});
+                               }
+                       }
+
                        if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool())
                        {
                                RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;