x86: Call the base class's regStats in X86ISA::TLB

When I try to build x86 architecture and run the se.py sample script
with helloworld example, there is a panic warning stated "Not all stats
have been initialized. You may need to add <ParentClass>::regStats() to
a new SimObject's regStats() function."

I see that in x86 tlb.cc, there is no initialization in regStats() function
that causes memory allocation error in some machine which make gem5 exit
abnormally. I add the BaseTLB::regStats(); on TLB::regStats() method and
can solve the problem

Change-Id: I8b62bebc15f896c3136ff4f8253dabbf998f618f
Reviewed-on: https://gem5-review.googlesource.com/c/16522
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 589b2b7eb7834751a1204e4716484d50cb5a30a6..829ebce0092fba89088799d3c4ded56616cb8910 100644 (file)
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -455,7 +455,7 @@ void
 TLB::regStats()
 {
     using namespace Stats;
-
+    BaseTLB::regStats();
     rdAccesses
         .name(name() + ".rdAccesses")
         .desc("TLB accesses on read requests");