---------- Begin Simulation Statistics ----------
-sim_seconds 1.898811 # Number of seconds simulated
-sim_ticks 1898811181000 # Number of ticks simulated
-final_tick 1898811181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.899762 # Number of seconds simulated
+sim_ticks 1899762444000 # Number of ticks simulated
+final_tick 1899762444000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 163774 # Simulator instruction rate (inst/s)
-host_op_rate 163774 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5540525376 # Simulator tick rate (ticks/s)
-host_mem_usage 339592 # Number of bytes of host memory used
-host_seconds 342.71 # Real time elapsed on the host
-sim_insts 56127436 # Number of instructions simulated
-sim_ops 56127436 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 739584 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24165760 # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2650368 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 241984 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 1058688 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28856384 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 739584 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 241984 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 981568 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7824192 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7824192 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 11556 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 377590 # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41412 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 3781 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 16542 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 450881 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 122253 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 122253 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 389498 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 12726784 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1395804 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 127440 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 557553 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15197079 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 389498 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 127440 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 516938 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4120574 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4120574 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4120574 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 389498 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 12726784 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1395804 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 127440 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 557553 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19317653 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 450881 # Total number of read requests seen
-system.physmem.writeReqs 122253 # Total number of write requests seen
-system.physmem.cpureqs 582476 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28856384 # Total number of bytes read from memory
-system.physmem.bytesWritten 7824192 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28856384 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7824192 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 66 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 3389 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 28644 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 28625 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 28393 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 28250 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 28253 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 28243 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 28343 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 28155 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 28192 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 27999 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 28056 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 27883 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 27988 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 28022 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 27871 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 27898 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 8087 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7991 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7846 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 7763 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7721 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7658 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7765 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 7698 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 7705 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7559 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7625 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 7394 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7457 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 7400 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 7239 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 7345 # Track writes on a per bank basis
+host_inst_rate 165662 # Simulator instruction rate (inst/s)
+host_op_rate 165662 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5547317951 # Simulator tick rate (ticks/s)
+host_mem_usage 338604 # Number of bytes of host memory used
+host_seconds 342.47 # Real time elapsed on the host
+sim_insts 56733550 # Number of instructions simulated
+sim_ops 56733550 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 853120 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24660608 # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide 2651648 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 123456 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 536896 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28825728 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 853120 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 123456 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 976576 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7795456 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7795456 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 13330 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 385322 # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide 41432 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 1929 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 8389 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 450402 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 121804 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 121804 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 449067 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 12980890 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1395779 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 64985 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 282612 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15173333 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 449067 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 64985 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 514052 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4103385 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4103385 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4103385 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 449067 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 12980890 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1395779 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 64985 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 282612 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19276718 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 450402 # Total number of read requests seen
+system.physmem.writeReqs 121804 # Total number of write requests seen
+system.physmem.cpureqs 579957 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28825728 # Total number of bytes read from memory
+system.physmem.bytesWritten 7795456 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28825728 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7795456 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 5038 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 28521 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 28327 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 28189 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 28015 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 28417 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 28335 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 28297 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 28180 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 28276 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 28045 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 28104 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 27882 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 27807 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 28046 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 27946 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 27954 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7961 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::2 7706 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 7580 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7839 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7697 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7703 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 7676 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7799 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 7587 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7619 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 7293 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7271 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 7481 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7325 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7481 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1873 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1898811160000 # Total gap between requests
+system.physmem.numWrRetry 2713 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1899757983000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 450881 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 124126 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 3389 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 320280 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 59619 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 33102 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
+system.physmem.readPktSize::6 450402 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 121804 # Categorize write packet sizes
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3158 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3856 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 4395 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::24 1460 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::26 869 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 362 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 8261632913 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 16092226663 # Sum of mem lat for all requests
-system.physmem.totBusLat 2254075000 # Total cycles spent in databus access
-system.physmem.totBankLat 5576518750 # Total cycles spent in bank access
-system.physmem.avgQLat 18325.99 # Average queueing delay per request
-system.physmem.avgBankLat 12369.86 # Average bank access latency per request
+system.physmem.wrQLenPdf::0 3182 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 3821 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 4354 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::5 5270 # What write queue length does an incoming req see
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-system.iocache.overall_avg_mshr_miss_latency::total 203915.191119 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68792.367232 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 68792.367232 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 202812.008327 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 202812.008327 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202243.543315 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 202243.543315 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202243.543315 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 202243.543315 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 10581841 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 8959361 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 281985 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 7046138 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 4567974 # Number of BTB hits
+system.cpu0.branchPred.lookups 12335027 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 10393813 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 330568 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 7867422 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 5239774 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 64.829471 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 656046 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 29257 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 66.600902 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 784891 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 32664 # Number of incorrect RAS predictions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 7560815 # DTB read hits
-system.cpu0.dtb.read_misses 30461 # DTB read misses
-system.cpu0.dtb.read_acv 538 # DTB read access violations
-system.cpu0.dtb.read_accesses 623625 # DTB read accesses
-system.cpu0.dtb.write_hits 5040625 # DTB write hits
-system.cpu0.dtb.write_misses 7520 # DTB write misses
-system.cpu0.dtb.write_acv 334 # DTB write access violations
-system.cpu0.dtb.write_accesses 206551 # DTB write accesses
-system.cpu0.dtb.data_hits 12601440 # DTB hits
-system.cpu0.dtb.data_misses 37981 # DTB misses
-system.cpu0.dtb.data_acv 872 # DTB access violations
-system.cpu0.dtb.data_accesses 830176 # DTB accesses
-system.cpu0.itb.fetch_hits 911527 # ITB hits
-system.cpu0.itb.fetch_misses 30644 # ITB misses
-system.cpu0.itb.fetch_acv 921 # ITB acv
-system.cpu0.itb.fetch_accesses 942171 # ITB accesses
+system.cpu0.dtb.read_hits 8753494 # DTB read hits
+system.cpu0.dtb.read_misses 29787 # DTB read misses
+system.cpu0.dtb.read_acv 536 # DTB read access violations
+system.cpu0.dtb.read_accesses 623801 # DTB read accesses
+system.cpu0.dtb.write_hits 5745053 # DTB write hits
+system.cpu0.dtb.write_misses 8131 # DTB write misses
+system.cpu0.dtb.write_acv 346 # DTB write access violations
+system.cpu0.dtb.write_accesses 207769 # DTB write accesses
+system.cpu0.dtb.data_hits 14498547 # DTB hits
+system.cpu0.dtb.data_misses 37918 # DTB misses
+system.cpu0.dtb.data_acv 882 # DTB access violations
+system.cpu0.dtb.data_accesses 831570 # DTB accesses
+system.cpu0.itb.fetch_hits 986254 # ITB hits
+system.cpu0.itb.fetch_misses 27996 # ITB misses
+system.cpu0.itb.fetch_acv 985 # ITB acv
+system.cpu0.itb.fetch_accesses 1014250 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 89753559 # number of cpu cycles simulated
+system.cpu0.numCycles 101860002 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 21107693 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 54367118 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 10581841 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 5224020 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 10262063 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1458036 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles 30903552 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 30207 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 199263 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 186050 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 96 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 6657299 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 195043 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 63623646 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.854511 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.189260 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 24837828 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 63180848 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 12335027 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 6024665 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 11886569 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1686741 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles 36619319 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 32566 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 195803 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 292498 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 224 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 7637223 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 223881 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples 74953254 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.842937 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.180655 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 53361583 83.87% 83.87% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 672459 1.06% 84.93% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 1316592 2.07% 87.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 583007 0.92% 87.91% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 2295308 3.61% 91.52% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 445844 0.70% 92.22% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 472664 0.74% 92.96% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 743494 1.17% 94.13% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 3732695 5.87% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 63066685 84.14% 84.14% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 761791 1.02% 85.16% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 1555671 2.08% 87.23% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 698950 0.93% 88.17% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 2562608 3.42% 91.58% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 513718 0.69% 92.27% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 568258 0.76% 93.03% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 822289 1.10% 94.13% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4403284 5.87% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 63623646 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.117899 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.605738 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 22232367 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 30357900 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 9303163 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 825009 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 905206 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 419214 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 29823 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 53368764 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 92723 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 905206 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 23093913 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 11627753 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 15736016 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 8768275 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 3492481 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 50503220 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 6655 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 393829 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1341574 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands 33876980 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 61564678 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 61250531 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 314147 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 29813717 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 4063255 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 1268860 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 187899 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 9409132 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 7922191 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5257693 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 964170 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 651506 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 44858999 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1558626 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 43884207 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 67322 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 4967350 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 2566909 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 1055206 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 63623646 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.689747 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.329677 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 74953254 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.121098 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.620271 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 26053984 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 36115594 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 10809914 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 920077 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1053684 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 507198 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 35097 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 62027396 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 105101 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1053684 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 27061357 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 14627985 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 18001405 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 10130422 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 4078399 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 58721682 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 6643 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 642092 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1424191 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands 39329555 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 71492090 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 71110334 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 381756 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 34559979 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 4769568 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 1435328 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 208629 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 11112444 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 9161053 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 6009456 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1123532 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 742915 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 52110985 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1787265 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 50968553 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 87650 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 5843461 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 2979197 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 1210641 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 74953254 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.680005 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.329199 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 43919799 69.03% 69.03% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 9075335 14.26% 83.29% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 4098408 6.44% 89.74% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2614119 4.11% 93.85% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2006211 3.15% 97.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1055812 1.66% 98.66% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 551217 0.87% 99.52% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 263467 0.41% 99.94% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 39278 0.06% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 52302643 69.78% 69.78% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 10307098 13.75% 83.53% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 4640048 6.19% 89.72% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 3056236 4.08% 93.80% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2433864 3.25% 97.05% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1212107 1.62% 98.66% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 643283 0.86% 99.52% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 306838 0.41% 99.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 51137 0.07% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 63623646 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 74953254 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 62740 10.88% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 271097 47.03% 57.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 242616 42.09% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 83602 12.51% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.51% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 310944 46.54% 59.05% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 273567 40.95% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 3777 0.01% 0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 30137882 68.68% 68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 45897 0.10% 68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 14285 0.03% 68.82% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.82% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.82% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.82% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 7870096 17.93% 86.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5096964 11.61% 98.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess 713427 1.63% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 35163137 68.99% 69.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 56167 0.11% 69.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 15648 0.03% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 9108259 17.87% 87.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5813234 11.41% 98.42% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess 806455 1.58% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 43884207 # Type of FU issued
-system.cpu0.iq.rate 0.488941 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 576453 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.013136 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 151584762 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 51176195 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 43017955 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 451072 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 219118 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 212749 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 44220901 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 235982 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 487348 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 50968553 # Type of FU issued
+system.cpu0.iq.rate 0.500378 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 668113 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.013108 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 177097926 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 59488760 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 49954313 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 548196 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 265355 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 258816 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 51345953 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 286939 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 543981 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 958085 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2941 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 10552 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 366818 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1095536 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 3484 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 12649 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 447527 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 13186 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 117811 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 18428 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 123543 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 905206 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 8069118 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 677733 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 49115212 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 536411 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 7922191 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5257693 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 1375945 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 564143 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 4652 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 10552 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 138850 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 301409 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 440259 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 43556869 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 7611218 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 327337 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1053684 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 10434033 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 794004 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 57098821 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 607587 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 9161053 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 6009456 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 1574353 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 581874 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 5211 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 12649 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 164505 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 346352 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 510857 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 50581166 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 8806339 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 387386 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 2697587 # number of nop insts executed
-system.cpu0.iew.exec_refs 12670581 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 6879787 # Number of branches executed
-system.cpu0.iew.exec_stores 5059363 # Number of stores executed
-system.cpu0.iew.exec_rate 0.485294 # Inst execution rate
-system.cpu0.iew.wb_sent 43311636 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 43230704 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 21537449 # num instructions producing a value
-system.cpu0.iew.wb_consumers 28771492 # num instructions consuming a value
+system.cpu0.iew.exec_nop 3200571 # number of nop insts executed
+system.cpu0.iew.exec_refs 14573024 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 8058196 # Number of branches executed
+system.cpu0.iew.exec_stores 5766685 # Number of stores executed
+system.cpu0.iew.exec_rate 0.496575 # Inst execution rate
+system.cpu0.iew.wb_sent 50300704 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 50213129 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 25063994 # num instructions producing a value
+system.cpu0.iew.wb_consumers 33773959 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.481660 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.748569 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.492962 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.742110 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 5358562 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 503420 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 412035 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 62718440 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.696169 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.614251 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6307351 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 576624 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 477479 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 73899570 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.685982 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.603952 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 46279929 73.79% 73.79% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 6945490 11.07% 84.86% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 3654930 5.83% 90.69% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 2050520 3.27% 93.96% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 1130391 1.80% 95.76% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 454158 0.72% 96.49% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 393863 0.63% 97.12% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 373108 0.59% 97.71% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1436051 2.29% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 54870784 74.25% 74.25% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 7931577 10.73% 84.98% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 4331737 5.86% 90.85% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 2351789 3.18% 94.03% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 1313178 1.78% 95.80% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 548800 0.74% 96.55% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 466874 0.63% 97.18% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 433224 0.59% 97.77% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1651607 2.23% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 62718440 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 43662606 # Number of instructions committed
-system.cpu0.commit.committedOps 43662606 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 73899570 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 50693798 # Number of instructions committed
+system.cpu0.commit.committedOps 50693798 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 11854981 # Number of memory references committed
-system.cpu0.commit.loads 6964106 # Number of loads committed
-system.cpu0.commit.membars 168172 # Number of memory barriers committed
-system.cpu0.commit.branches 6551324 # Number of branches committed
-system.cpu0.commit.fp_insts 210613 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 40489033 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 540020 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 1436051 # number cycles where commit BW limit reached
+system.cpu0.commit.refs 13627446 # Number of memory references committed
+system.cpu0.commit.loads 8065517 # Number of loads committed
+system.cpu0.commit.membars 196376 # Number of memory barriers committed
+system.cpu0.commit.branches 7658577 # Number of branches committed
+system.cpu0.commit.fp_insts 256550 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 46944411 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 646517 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 1651607 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 110111593 # The number of ROB reads
-system.cpu0.rob.rob_writes 98948174 # The number of ROB writes
-system.cpu0.timesIdled 879648 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 26129913 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 3707863967 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 41199881 # Number of Instructions Simulated
-system.cpu0.committedOps 41199881 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 41199881 # Number of Instructions Simulated
-system.cpu0.cpi 2.178491 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.178491 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.459033 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.459033 # IPC: Total IPC of All Threads
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+system.cpu0.committedInsts_total 47774945 # Number of Instructions Simulated
+system.cpu0.cpi 2.132080 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.132080 # CPI: Total CPI of All Threads
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system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu0.icache.replacements 728874 # number of replacements
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-system.cpu0.icache.avg_refs 8.075920 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 20962478000 # Cycle when the warmup percentage was hit.
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-system.cpu0.icache.overall_miss_rate::total 0.115191 # miss rate for overall accesses
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-system.cpu0.icache.demand_avg_miss_latency::total 14077.340709 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14077.340709 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14077.340709 # average overall miss latency
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-system.cpu0.icache.demand_mshr_miss_latency::total 8901782997 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.icache.overall_mshr_miss_latency::total 8901782997 # number of overall MSHR miss cycles
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-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for overall accesses
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-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12201.878709 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average overall mshr miss latency
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+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12206.456947 # average overall mshr miss latency
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-system.cpu0.dcache.replacements 1051655 # number of replacements
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050799 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050799 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088093 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088093 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015957 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015957 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095640 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.095640 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095640 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.095640 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21506.853565 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21506.853565 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35618.739744 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35618.739744 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11537.632042 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11537.632042 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5334.670679 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5334.670679 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24528.668975 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24528.668975 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24528.668975 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24528.668975 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 4327546 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 3555815 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 137782 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 2736457 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 1529937 # Number of BTB hits
+system.cpu1.branchPred.lookups 2650086 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 2188228 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 78181 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 1530727 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 883629 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 55.909411 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 311519 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 14646 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 57.726100 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 184091 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 8336 # Number of incorrect RAS predictions.
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 3068448 # DTB read hits
-system.cpu1.dtb.read_misses 13337 # DTB read misses
-system.cpu1.dtb.read_acv 21 # DTB read access violations
-system.cpu1.dtb.read_accesses 325420 # DTB read accesses
-system.cpu1.dtb.write_hits 1915630 # DTB write hits
-system.cpu1.dtb.write_misses 2521 # DTB write misses
-system.cpu1.dtb.write_acv 68 # DTB write access violations
-system.cpu1.dtb.write_accesses 132592 # DTB write accesses
-system.cpu1.dtb.data_hits 4984078 # DTB hits
-system.cpu1.dtb.data_misses 15858 # DTB misses
-system.cpu1.dtb.data_acv 89 # DTB access violations
-system.cpu1.dtb.data_accesses 458012 # DTB accesses
-system.cpu1.itb.fetch_hits 498592 # ITB hits
-system.cpu1.itb.fetch_misses 6957 # ITB misses
-system.cpu1.itb.fetch_acv 210 # ITB acv
-system.cpu1.itb.fetch_accesses 505549 # ITB accesses
+system.cpu1.dtb.read_hits 1963408 # DTB read hits
+system.cpu1.dtb.read_misses 10761 # DTB read misses
+system.cpu1.dtb.read_acv 27 # DTB read access violations
+system.cpu1.dtb.read_accesses 325022 # DTB read accesses
+system.cpu1.dtb.write_hits 1266270 # DTB write hits
+system.cpu1.dtb.write_misses 2185 # DTB write misses
+system.cpu1.dtb.write_acv 66 # DTB write access violations
+system.cpu1.dtb.write_accesses 133146 # DTB write accesses
+system.cpu1.dtb.data_hits 3229678 # DTB hits
+system.cpu1.dtb.data_misses 12946 # DTB misses
+system.cpu1.dtb.data_acv 93 # DTB access violations
+system.cpu1.dtb.data_accesses 458168 # DTB accesses
+system.cpu1.itb.fetch_hits 437746 # ITB hits
+system.cpu1.itb.fetch_misses 6892 # ITB misses
+system.cpu1.itb.fetch_acv 236 # ITB acv
+system.cpu1.itb.fetch_accesses 444638 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 28341850 # number of cpu cycles simulated
+system.cpu1.numCycles 16144974 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 9666058 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 20746660 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 4327546 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 1841456 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 3769607 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 667538 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles 11516910 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 24752 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 65971 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 157862 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 2430728 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 90320 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 25638274 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.809207 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.171586 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 6121442 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 12493756 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 2650086 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 1067720 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 2240899 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 409596 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles 6344466 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 26232 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 65860 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 57508 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 1513677 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 52961 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 15118787 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.826373 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.200485 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 21868667 85.30% 85.30% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 217825 0.85% 86.15% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 471767 1.84% 87.99% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 290566 1.13% 89.12% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 572691 2.23% 91.35% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 192619 0.75% 92.11% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 225020 0.88% 92.98% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 283328 1.11% 94.09% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 1515791 5.91% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 12877888 85.18% 85.18% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 143885 0.95% 86.13% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 241695 1.60% 87.73% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 180531 1.19% 88.92% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 309762 2.05% 90.97% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 120449 0.80% 91.77% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 135595 0.90% 92.66% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 201831 1.33% 94.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 907151 6.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 25638274 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.152691 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.732015 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 9733408 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 11767392 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 3496252 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 218180 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 423041 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 197160 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 14107 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 20339380 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 42509 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 423041 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 10090973 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 3436285 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 7189136 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 3265501 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 1233336 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 19035683 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 265 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 302354 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 266371 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands 12573410 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 22727510 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 22552449 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 175061 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 10671795 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 1901615 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 598380 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 62207 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 3655619 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 3246585 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 2021315 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 341799 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 191681 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 16730301 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 718132 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 16236732 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 38678 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 2401085 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 1178363 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 514161 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 25638274 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.633301 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.313801 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 15118787 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.164143 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.773848 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 6052870 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 6602402 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 2094481 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 114057 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 254976 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 116126 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 7500 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 12249807 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 22555 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 254976 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 6262682 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 497209 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 5456490 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 1996397 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 651031 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 11355545 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 50 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 56660 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 160008 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands 7474719 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 13559101 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 13415671 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 143430 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 6386740 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 1087979 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 456269 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 43986 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 2005882 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 2076975 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 1341554 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 190968 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 103806 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 9970569 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 502731 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 9700952 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 30075 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 1449475 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 723922 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 361264 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 15118787 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.641649 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.316312 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 18618463 72.62% 72.62% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 3106773 12.12% 84.74% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 1368758 5.34% 90.08% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 986929 3.85% 93.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 856057 3.34% 97.26% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 349630 1.36% 98.63% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 219211 0.86% 99.48% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 115612 0.45% 99.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 16841 0.07% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 10852712 71.78% 71.78% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 1956314 12.94% 84.72% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 839077 5.55% 90.27% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 560111 3.70% 93.98% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 472963 3.13% 97.11% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 218451 1.44% 98.55% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 140254 0.93% 99.48% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 70720 0.47% 99.95% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 8185 0.05% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 25638274 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 15118787 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 22162 7.89% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 144030 51.29% 59.18% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 114619 40.82% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 3675 1.85% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 107078 53.97% 55.83% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 87636 44.17% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 3527 0.02% 0.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 10692350 65.85% 65.87% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 24766 0.15% 66.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 11484 0.07% 66.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 3204356 19.74% 85.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 1945149 11.98% 97.82% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess 353337 2.18% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 6050828 62.37% 62.41% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 16408 0.17% 62.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 10849 0.11% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 2054303 21.18% 83.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 1289929 13.30% 97.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess 273346 2.82% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 16236732 # Type of FU issued
-system.cpu1.iq.rate 0.572889 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 280811 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.017295 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 58178646 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 19730507 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 15830008 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 252581 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 122599 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 119620 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 16382145 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 131871 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 151965 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 9700952 # Type of FU issued
+system.cpu1.iq.rate 0.600865 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 198389 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.020450 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 34541883 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 11823308 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 9430294 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 207272 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 101213 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 98067 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 9787736 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 108079 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 94689 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 456957 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 998 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 3692 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 187617 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 288018 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 887 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 1813 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 126704 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 5626 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 16438 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 386 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 10289 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 423041 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 2638422 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 162147 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 18437863 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 211636 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 3246585 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 2021315 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 643129 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 60084 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 2152 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 3692 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 66784 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 149088 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 215872 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 16080551 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 3090638 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 156181 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 254976 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 327284 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 41516 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 10988492 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 148711 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 2076975 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 1341554 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 455253 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 34417 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 1886 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 1813 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 35814 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 100493 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 136307 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 9610649 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 1981550 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 90303 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 989430 # number of nop insts executed
-system.cpu1.iew.exec_refs 5015230 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 2535241 # Number of branches executed
-system.cpu1.iew.exec_stores 1924592 # Number of stores executed
-system.cpu1.iew.exec_rate 0.567378 # Inst execution rate
-system.cpu1.iew.wb_sent 15988482 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 15949628 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 7724743 # num instructions producing a value
-system.cpu1.iew.wb_consumers 10881499 # num instructions consuming a value
+system.cpu1.iew.exec_nop 515192 # number of nop insts executed
+system.cpu1.iew.exec_refs 3256018 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 1435370 # Number of branches executed
+system.cpu1.iew.exec_stores 1274468 # Number of stores executed
+system.cpu1.iew.exec_rate 0.595272 # Inst execution rate
+system.cpu1.iew.wb_sent 9557675 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 9528361 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 4461159 # num instructions producing a value
+system.cpu1.iew.wb_consumers 6259469 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.562759 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.709897 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.590175 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.712706 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 2575173 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 203971 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 201824 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 25215233 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.626683 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.561616 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 1504147 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 141467 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 128937 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 14863811 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.633307 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.576989 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 19361338 76.78% 76.78% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 2499341 9.91% 86.70% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 1261575 5.00% 91.70% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 645749 2.56% 94.26% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 410067 1.63% 95.89% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 193046 0.77% 96.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 184525 0.73% 97.38% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 147171 0.58% 97.97% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 512421 2.03% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 11340708 76.30% 76.30% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 1645490 11.07% 87.37% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 614395 4.13% 91.50% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 372484 2.51% 94.01% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 264045 1.78% 95.78% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 106401 0.72% 96.50% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 110365 0.74% 97.24% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 108140 0.73% 97.97% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 301783 2.03% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 25215233 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 15801951 # Number of instructions committed
-system.cpu1.commit.committedOps 15801951 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 14863811 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 9413351 # Number of instructions committed
+system.cpu1.commit.committedOps 9413351 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 4623326 # Number of memory references committed
-system.cpu1.commit.loads 2789628 # Number of loads committed
-system.cpu1.commit.membars 68640 # Number of memory barriers committed
-system.cpu1.commit.branches 2366242 # Number of branches committed
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-system.cpu1.committedInsts_total 14927555 # Number of Instructions Simulated
-system.cpu1.cpi 1.898626 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.898626 # CPI: Total CPI of All Threads
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-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13962.665575 # average overall miss latency
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-system.cpu1.icache.ReadReq_mshr_misses::total 360489 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 360489 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 360489 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 360489 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 360489 # number of overall MSHR misses
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-system.cpu1.icache.ReadReq_mshr_miss_latency::total 4342433998 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4342433998 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 4342433998 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4342433998 # number of overall MSHR miss cycles
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+system.cpu1.dcache.avg_refs 24.195042 # Average number of references to valid blocks.
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system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu1.dcache.writebacks::total 289966 # number of writebacks
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+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 678608500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043459 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043459 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033490 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033490 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.121823 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.121823 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087975 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087975 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039563 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.039563 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039563 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.039563 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12212.859138 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12212.859138 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28473.486877 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28473.486877 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8108.274281 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8108.274281 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5193.738080 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5193.738080 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17592.215059 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17592.215059 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17592.215059 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17592.215059 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 4837 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 159566 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 54412 39.60% 39.60% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 131 0.10% 39.69% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1925 1.40% 41.09% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 16 0.01% 41.10% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 80931 58.90% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 137415 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 53531 49.06% 49.06% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 131 0.12% 49.18% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1925 1.76% 50.94% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 16 0.01% 50.96% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 53515 49.04% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 109118 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1866933879000 98.32% 98.32% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 62852000 0.00% 98.32% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 558860500 0.03% 98.35% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 8730000 0.00% 98.35% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 31246000500 1.65% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1898810322000 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.983809 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce 6548 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 181674 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 64152 40.43% 40.43% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21 136 0.09% 40.52% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22 1926 1.21% 41.73% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30 194 0.12% 41.86% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 92254 58.14% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 158662 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 63162 49.20% 49.20% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21 136 0.11% 49.30% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22 1926 1.50% 50.80% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30 194 0.15% 50.95% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 62971 49.05% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 128389 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1864385169000 98.14% 98.14% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 63278000 0.00% 98.14% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 567602000 0.03% 98.17% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 94599000 0.00% 98.18% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 34650950500 1.82% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1899761598500 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.984568 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.661242 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.794076 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31 0.682583 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total 0.809198 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed
system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 202 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 107 0.07% 0.07% # number of callpals executed
-system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed
-system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 2838 1.96% 2.03% # number of callpals executed
-system.cpu0.kern.callpal::tbi 48 0.03% 2.07% # number of callpals executed
-system.cpu0.kern.callpal::wrent 7 0.00% 2.07% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 131134 90.46% 92.54% # number of callpals executed
-system.cpu0.kern.callpal::rdps 6127 4.23% 96.76% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp 1 0.00% 96.76% # number of callpals executed
-system.cpu0.kern.callpal::wrusp 3 0.00% 96.77% # number of callpals executed
-system.cpu0.kern.callpal::rdusp 8 0.01% 96.77% # number of callpals executed
-system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed
-system.cpu0.kern.callpal::rti 4208 2.90% 99.68% # number of callpals executed
-system.cpu0.kern.callpal::callsys 333 0.23% 99.91% # number of callpals executed
-system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 144957 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 6180 # number of protection mode switches
+system.cpu0.kern.callpal::wripir 297 0.18% 0.18% # number of callpals executed
+system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed
+system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed
+system.cpu0.kern.callpal::swpctx 3469 2.08% 2.26% # number of callpals executed
+system.cpu0.kern.callpal::tbi 48 0.03% 2.29% # number of callpals executed
+system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed
+system.cpu0.kern.callpal::swpipl 151918 91.03% 93.32% # number of callpals executed
+system.cpu0.kern.callpal::rdps 6167 3.70% 97.02% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp 1 0.00% 97.02% # number of callpals executed
+system.cpu0.kern.callpal::wrusp 3 0.00% 97.02% # number of callpals executed
+system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed
+system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed
+system.cpu0.kern.callpal::rti 4490 2.69% 99.72% # number of callpals executed
+system.cpu0.kern.callpal::callsys 333 0.20% 99.92% # number of callpals executed
+system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed
+system.cpu0.kern.callpal::total 166884 # number of callpals executed
+system.cpu0.kern.mode_switch::kernel 6992 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1258 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1257
system.cpu0.kern.mode_good::user 1258
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.203398 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.179777 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.338129 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1896878389500 99.90% 99.90% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 1931924500 0.10% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total 0.304848 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 1897853280000 99.90% 99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 1908310500 0.10% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 2839 # number of times the context was actually changed
+system.cpu0.kern.swap_context 3470 # number of times the context was actually changed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 3835 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 77998 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 27220 39.42% 39.42% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1923 2.78% 42.20% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 107 0.15% 42.36% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 39804 57.64% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 69054 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 26724 48.26% 48.26% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1923 3.47% 51.74% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 107 0.19% 51.93% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 26617 48.07% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 55371 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1869610475000 98.48% 98.48% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 533425500 0.03% 98.51% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 50588500 0.00% 98.51% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 28306196500 1.49% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1898500685500 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.981778 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce 2463 # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei 58134 # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0 18218 36.94% 36.94% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22 1925 3.90% 40.84% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30 297 0.60% 41.45% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31 28877 58.55% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 49317 # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0 17831 47.44% 47.44% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22 1925 5.12% 52.56% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 297 0.79% 53.35% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 17534 46.65% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 37587 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1874537930000 98.69% 98.69% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 532213500 0.03% 98.72% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 134642000 0.01% 98.72% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 24250176000 1.28% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1899454961500 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.978757 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.668702 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.801851 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31 0.607196 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total 0.762151 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed
system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed
system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed
system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 124 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed
-system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 1407 1.97% 2.00% # number of callpals executed
-system.cpu1.kern.callpal::tbi 6 0.01% 2.01% # number of callpals executed
-system.cpu1.kern.callpal::wrent 7 0.01% 2.02% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 64017 89.75% 91.76% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2632 3.69% 95.45% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 95.45% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 4 0.01% 95.46% # number of callpals executed
-system.cpu1.kern.callpal::rdusp 1 0.00% 95.46% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.00% 95.47% # number of callpals executed
-system.cpu1.kern.callpal::rti 3006 4.21% 99.68% # number of callpals executed
-system.cpu1.kern.callpal::callsys 184 0.26% 99.94% # number of callpals executed
-system.cpu1.kern.callpal::imb 43 0.06% 100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir 194 0.38% 0.38% # number of callpals executed
+system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed
+system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed
+system.cpu1.kern.callpal::swpctx 1140 2.22% 2.61% # number of callpals executed
+system.cpu1.kern.callpal::tbi 6 0.01% 2.62% # number of callpals executed
+system.cpu1.kern.callpal::wrent 7 0.01% 2.63% # number of callpals executed
+system.cpu1.kern.callpal::swpipl 43997 85.81% 88.44% # number of callpals executed
+system.cpu1.kern.callpal::rdps 2594 5.06% 93.50% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp 1 0.00% 93.50% # number of callpals executed
+system.cpu1.kern.callpal::wrusp 4 0.01% 93.51% # number of callpals executed
+system.cpu1.kern.callpal::rdusp 1 0.00% 93.51% # number of callpals executed
+system.cpu1.kern.callpal::whami 3 0.01% 93.52% # number of callpals executed
+system.cpu1.kern.callpal::rti 3097 6.04% 99.56% # number of callpals executed
+system.cpu1.kern.callpal::callsys 184 0.36% 99.91% # number of callpals executed
+system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 71331 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 1876 # number of protection mode switches
+system.cpu1.kern.callpal::total 51275 # number of callpals executed
+system.cpu1.kern.mode_switch::kernel 1424 # number of protection mode switches
system.cpu1.kern.mode_switch::user 488 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2061 # number of protection mode switches
-system.cpu1.kern.mode_good::kernel 557
+system.cpu1.kern.mode_switch::idle 2438 # number of protection mode switches
+system.cpu1.kern.mode_good::kernel 709
system.cpu1.kern.mode_good::user 488
-system.cpu1.kern.mode_good::idle 69
-system.cpu1.kern.mode_switch_good::kernel 0.296908 # fraction of useful protection mode switches
+system.cpu1.kern.mode_good::idle 221
+system.cpu1.kern.mode_switch_good::kernel 0.497893 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.033479 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 0.251751 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 39690497500 2.09% 2.09% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 850597000 0.04% 2.14% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1857949530000 97.86% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 1408 # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle 0.090648 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total 0.325977 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel 4822300000 0.25% 0.25% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user 832322500 0.04% 0.30% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle 1893789827000 99.70% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 1141 # number of times the context was actually changed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 1.854310 # Number of seconds simulated
-sim_ticks 1854310111000 # Number of ticks simulated
-final_tick 1854310111000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.854307 # Number of seconds simulated
+sim_ticks 1854307399500 # Number of ticks simulated
+final_tick 1854307399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 145253 # Simulator instruction rate (inst/s)
-host_op_rate 145253 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5083862253 # Simulator tick rate (ticks/s)
-host_mem_usage 332668 # Number of bytes of host memory used
-host_seconds 364.74 # Real time elapsed on the host
-sim_insts 52980262 # Number of instructions simulated
-sim_ops 52980262 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 964224 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24877184 # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28493696 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 964224 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 964224 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7514944 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7514944 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 15066 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 388706 # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 445214 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 117421 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 117421 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 519991 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 13415870 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1430337 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15366198 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 519991 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 519991 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4052690 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4052690 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4052690 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 519991 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 13415870 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1430337 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19418888 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 445214 # Total number of read requests seen
-system.physmem.writeReqs 117421 # Total number of write requests seen
-system.physmem.cpureqs 564314 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28493696 # Total number of bytes read from memory
-system.physmem.bytesWritten 7514944 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28493696 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7514944 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 174 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 28116 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 27866 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 27714 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 27520 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 27750 # Track reads on a per bank basis
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-system.physmem.perBankRdReqs::15 27717 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7633 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7399 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7274 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 7170 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7277 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7235 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::14 7264 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 7200 # Track writes on a per bank basis
+host_inst_rate 106006 # Simulator instruction rate (inst/s)
+host_op_rate 106006 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3711029376 # Simulator tick rate (ticks/s)
+host_mem_usage 333480 # Number of bytes of host memory used
+host_seconds 499.67 # Real time elapsed on the host
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+sim_ops 52968721 # Number of ops (including micro ops) simulated
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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-system.physmem.totGap 1854304705000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
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-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
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-system.physmem.totQLat 7913395266 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 15649662766 # Sum of mem lat for all requests
-system.physmem.totBusLat 2225790000 # Total cycles spent in databus access
-system.physmem.totBankLat 5510477500 # Total cycles spent in bank access
-system.physmem.avgQLat 17776.60 # Average queueing delay per request
-system.physmem.avgBankLat 12378.70 # Average bank access latency per request
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+system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see
+system.physmem.totQLat 7499469250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 15210035500 # Sum of mem lat for all requests
+system.physmem.totBusLat 2225595000 # Total cycles spent in databus access
+system.physmem.totBankLat 5484971250 # Total cycles spent in bank access
+system.physmem.avgQLat 16848.23 # Average queueing delay per request
+system.physmem.avgBankLat 12322.48 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 35155.30 # Average memory access latency
-system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 34170.72 # Average memory access latency
+system.physmem.avgRdBW 15.36 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 15.36 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.15 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 11.52 # Average write queue length over time
-system.physmem.readRowHits 417628 # Number of row buffer hits during reads
-system.physmem.writeRowHits 91533 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.82 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 77.95 # Row buffer hit rate for writes
-system.physmem.avgGap 3295750.72 # Average gap between requests
+system.physmem.avgWrQLen 14.44 # Average write queue length over time
+system.physmem.readRowHits 417746 # Number of row buffer hits during reads
+system.physmem.writeRowHits 91351 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 93.85 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 77.94 # Row buffer hit rate for writes
+system.physmem.avgGap 3297216.82 # Average gap between requests
system.iocache.replacements 41685 # number of replacements
-system.iocache.tagsinuse 1.265053 # Cycle average of tags in use
+system.iocache.tagsinuse 1.265036 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 1704474436000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide 1.265053 # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide 0.079066 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.079066 # Average percentage of cache occupancy
+system.iocache.warmup_cycle 1704474218000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide 1.265036 # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide 0.079065 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.079065 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 10610366806 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10610366806 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 10631294804 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10631294804 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 10631294804 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10631294804 # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 10707310806 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10707310806 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 10728238804 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10728238804 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 10728238804 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 10728238804 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255351.530757 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 255351.530757 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 254794.363188 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 254794.363188 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 254794.363188 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 254794.363188 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 282772 # number of cycles access was blocked
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 257684.607384 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 257684.607384 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 257117.766423 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 257117.766423 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 257117.766423 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 257117.766423 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 287181 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 27194 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 27254 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 10.398323 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10.537206 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8448369274 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 8448369274 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 8460300524 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 8460300524 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 8460300524 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 8460300524 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8545305081 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 8545305081 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 8557236330 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 8557236330 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 8557236330 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8557236330 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203320.400318 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 203320.400318 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202763.343895 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 202763.343895 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202763.343895 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 202763.343895 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 205653.279770 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 205653.279770 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205086.550749 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 205086.550749 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205086.550749 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 205086.550749 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 13838840 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11607895 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 399412 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9524270 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 5814876 # Number of BTB hits
+system.cpu.branchPred.lookups 13852347 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11625691 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 399405 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9419832 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 5813293 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 61.053246 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 905729 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 39052 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 61.713341 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 901451 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 38715 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9926019 # DTB read hits
-system.cpu.dtb.read_misses 41533 # DTB read misses
-system.cpu.dtb.read_acv 530 # DTB read access violations
-system.cpu.dtb.read_accesses 942239 # DTB read accesses
-system.cpu.dtb.write_hits 6593693 # DTB write hits
-system.cpu.dtb.write_misses 10528 # DTB write misses
-system.cpu.dtb.write_acv 400 # DTB write access violations
-system.cpu.dtb.write_accesses 337995 # DTB write accesses
-system.cpu.dtb.data_hits 16519712 # DTB hits
-system.cpu.dtb.data_misses 52061 # DTB misses
-system.cpu.dtb.data_acv 930 # DTB access violations
-system.cpu.dtb.data_accesses 1280234 # DTB accesses
-system.cpu.itb.fetch_hits 1304342 # ITB hits
-system.cpu.itb.fetch_misses 39856 # ITB misses
-system.cpu.itb.fetch_acv 1022 # ITB acv
-system.cpu.itb.fetch_accesses 1344198 # ITB accesses
+system.cpu.dtb.read_hits 9912757 # DTB read hits
+system.cpu.dtb.read_misses 41466 # DTB read misses
+system.cpu.dtb.read_acv 543 # DTB read access violations
+system.cpu.dtb.read_accesses 941271 # DTB read accesses
+system.cpu.dtb.write_hits 6601987 # DTB write hits
+system.cpu.dtb.write_misses 10361 # DTB write misses
+system.cpu.dtb.write_acv 401 # DTB write access violations
+system.cpu.dtb.write_accesses 337783 # DTB write accesses
+system.cpu.dtb.data_hits 16514744 # DTB hits
+system.cpu.dtb.data_misses 51827 # DTB misses
+system.cpu.dtb.data_acv 944 # DTB access violations
+system.cpu.dtb.data_accesses 1279054 # DTB accesses
+system.cpu.itb.fetch_hits 1307981 # ITB hits
+system.cpu.itb.fetch_misses 36519 # ITB misses
+system.cpu.itb.fetch_acv 1105 # ITB acv
+system.cpu.itb.fetch_accesses 1344500 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 109629781 # number of cpu cycles simulated
+system.cpu.numCycles 108624305 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 28054548 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 70673295 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 13838840 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 6720605 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 13244077 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1985157 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 37404215 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 32636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 256282 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 293547 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 8545648 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 265175 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 80570729 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.877158 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.220803 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 28031603 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 70677368 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 13852347 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 6714744 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 13246931 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1983028 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 37386086 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 31591 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 253691 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 294769 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 735 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 8549977 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 266732 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 80529349 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.877660 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.221433 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 67326652 83.56% 83.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 851821 1.06% 84.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1698513 2.11% 86.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 825554 1.02% 87.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2751975 3.42% 91.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 562639 0.70% 91.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 645154 0.80% 92.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1011601 1.26% 93.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 4896820 6.08% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 67282418 83.55% 83.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 855134 1.06% 84.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1701405 2.11% 86.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 823363 1.02% 87.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2750758 3.42% 91.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 561116 0.70% 91.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 645464 0.80% 92.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1009589 1.25% 93.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 4900102 6.08% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 80570729 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.126232 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.644654 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 29191187 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 37065229 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 12109046 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 962419 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1242847 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 584292 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 42668 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 69380603 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 129620 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1242847 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 30314558 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 13623750 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 19784463 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 11341758 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4263351 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 65627824 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 6945 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 510530 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 1483365 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 43820100 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 79668795 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 79189543 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 479252 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 38180356 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 5639736 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1682796 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 239926 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12145356 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 10440685 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 6902590 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1325482 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 872752 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 58180873 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2047058 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 56813064 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 111741 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 6883646 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3532849 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1386082 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 80570729 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.705133 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.366225 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 80529349 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.127525 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.650659 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 29153342 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 37060255 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 12110722 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 963448 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1241581 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 585928 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 42780 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 69380340 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 129844 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1241581 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 30275533 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 13620847 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 19786861 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 11346001 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4258524 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 65625141 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 6921 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 508210 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 1478954 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 43830191 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 79653139 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 79174156 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 478983 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 38170900 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 5659283 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1683041 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 240056 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12113189 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 10427468 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 6890622 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1312006 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 847421 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 58167835 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2052016 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 56809344 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 88346 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 6890448 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3503635 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1391090 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 80529349 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.705449 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.366907 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 55925631 69.41% 69.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 10804122 13.41% 82.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 5164072 6.41% 89.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 3379310 4.19% 93.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 2651147 3.29% 96.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 1461283 1.81% 98.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 759145 0.94% 99.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 331157 0.41% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 94862 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 55889300 69.40% 69.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 10803861 13.42% 82.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 5162711 6.41% 89.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 3375118 4.19% 93.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 2651639 3.29% 96.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 1461034 1.81% 98.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 755339 0.94% 99.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 331829 0.41% 99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 98518 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 80570729 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 80529349 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 89963 11.41% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 373446 47.37% 58.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 325006 41.22% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 91375 11.51% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 373733 47.09% 58.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 328605 41.40% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 38735893 68.18% 68.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 61716 0.11% 68.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 38736276 68.19% 68.20% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 61707 0.11% 68.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 10357569 18.23% 86.59% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 6672257 11.74% 98.33% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 949100 1.67% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 10345170 18.21% 86.57% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 6680665 11.76% 98.33% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess 948997 1.67% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 56813064 # Type of FU issued
-system.cpu.iq.rate 0.518227 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 788415 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.013877 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 194404430 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 66788743 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 55573367 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 692582 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 336629 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 327887 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 57232794 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 361399 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 600057 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 56809344 # Type of FU issued
+system.cpu.iq.rate 0.522989 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 793713 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.013972 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 194336981 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 66788043 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 55575971 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 693114 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 336007 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 327916 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 57233562 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 362209 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 600992 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1348422 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 4157 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14125 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 524715 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1337423 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 4170 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 14100 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 513944 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 17951 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 174954 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 17964 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 173464 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1242847 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 9951157 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 684131 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 63754506 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 676985 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 10440685 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 6902590 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1803123 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 512112 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 18418 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14125 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 202045 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 411832 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 613877 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 56345945 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 9995759 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 467118 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1241581 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 9950428 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 684284 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 63748308 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 674797 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 10427468 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 6890622 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1807435 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 512768 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 18119 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 14100 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 203235 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 412070 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 615305 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 56339118 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 9982368 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 470225 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 3526575 # number of nop insts executed
-system.cpu.iew.exec_refs 16615200 # number of memory reference insts executed
-system.cpu.iew.exec_branches 8926807 # Number of branches executed
-system.cpu.iew.exec_stores 6619441 # Number of stores executed
-system.cpu.iew.exec_rate 0.513966 # Inst execution rate
-system.cpu.iew.wb_sent 56016691 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 55901254 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 27769565 # num instructions producing a value
-system.cpu.iew.wb_consumers 37614191 # num instructions consuming a value
+system.cpu.iew.exec_nop 3528457 # number of nop insts executed
+system.cpu.iew.exec_refs 16609952 # number of memory reference insts executed
+system.cpu.iew.exec_branches 8925181 # Number of branches executed
+system.cpu.iew.exec_stores 6627584 # Number of stores executed
+system.cpu.iew.exec_rate 0.518660 # Inst execution rate
+system.cpu.iew.wb_sent 56017641 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 55903887 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 27773544 # num instructions producing a value
+system.cpu.iew.wb_consumers 37603829 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.509909 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.738274 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.514654 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.738583 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 7465102 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 660976 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 568169 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 79327882 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.708087 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.637784 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 7472187 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 660926 # The number of times commit has been forced to stall to communicate backwards
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+system.cpu.commit.committed_per_cycle::mean 0.708292 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.638038 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 58561818 73.82% 73.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 8602415 10.84% 84.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4601651 5.80% 90.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2532853 3.19% 93.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1516154 1.91% 95.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 607730 0.77% 96.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 522045 0.66% 97.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 534524 0.67% 97.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1848692 2.33% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 58526272 73.82% 73.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 8600403 10.85% 84.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4599837 5.80% 90.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2533746 3.20% 93.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1516837 1.91% 95.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 606860 0.77% 96.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 524643 0.66% 97.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 525259 0.66% 97.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 1853911 2.34% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 79327882 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 56171016 # Number of instructions committed
-system.cpu.commit.committedOps 56171016 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 79287768 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 56158922 # Number of instructions committed
+system.cpu.commit.committedOps 56158922 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 15470138 # Number of memory references committed
-system.cpu.commit.loads 9092263 # Number of loads committed
-system.cpu.commit.membars 226349 # Number of memory barriers committed
-system.cpu.commit.branches 8440338 # Number of branches committed
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+system.cpu.commit.membars 226335 # Number of memory barriers committed
+system.cpu.commit.branches 8439344 # Number of branches committed
system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 52020652 # Number of committed integer instructions.
-system.cpu.commit.function_calls 740552 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 1848692 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 52009184 # Number of committed integer instructions.
+system.cpu.commit.function_calls 740395 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 1853911 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 140865752 # The number of ROB reads
-system.cpu.rob.rob_writes 128516921 # The number of ROB writes
-system.cpu.timesIdled 1179002 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 29059052 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 3598984001 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 52980262 # Number of Instructions Simulated
-system.cpu.committedOps 52980262 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 52980262 # Number of Instructions Simulated
-system.cpu.cpi 2.069257 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.069257 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.483265 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.483265 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 73880365 # number of integer regfile reads
-system.cpu.int_regfile_writes 40316413 # number of integer regfile writes
-system.cpu.fp_regfile_reads 166011 # number of floating regfile reads
-system.cpu.fp_regfile_writes 167446 # number of floating regfile writes
-system.cpu.misc_regfile_reads 1987331 # number of misc regfile reads
-system.cpu.misc_regfile_writes 938994 # number of misc regfile writes
+system.cpu.rob.rob_reads 140815408 # The number of ROB reads
+system.cpu.rob.rob_writes 128505533 # The number of ROB writes
+system.cpu.timesIdled 1178112 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 28094956 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 3599984053 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 52968721 # Number of Instructions Simulated
+system.cpu.committedOps 52968721 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 52968721 # Number of Instructions Simulated
+system.cpu.cpi 2.050725 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.050725 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.487632 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.487632 # IPC: Total IPC of All Threads
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+system.cpu.misc_regfile_writes 938918 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu.icache.replacements 1008798 # number of replacements
-system.cpu.icache.tagsinuse 510.238342 # Cycle average of tags in use
-system.cpu.icache.total_refs 7480626 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 1009306 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 7.411653 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 20723156000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 510.238342 # Average occupied blocks per requestor
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-system.cpu.icache.occ_percent::total 0.996559 # Average percentage of cache occupancy
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-system.cpu.icache.ReadReq_miss_latency::total 14700112992 # number of ReadReq miss cycles
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-system.cpu.icache.demand_accesses::total 8545645 # number of demand (read+write) accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13802.689712 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13802.689712 # average ReadReq miss latency
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11935.066613 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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-system.cpu.dcache.tagsinuse 511.995159 # Cycle average of tags in use
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system.cpu.dcache.warmup_cycle 21807000 # Cycle when the warmup percentage was hit.
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+system.cpu.dcache.LoadLockedReq_miss_latency::total 306197000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 76500 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total 76500 # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 98616822025 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 98616822025 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 98616822025 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 98616822025 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 9001639 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 9001639 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 6146469 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6146469 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209038 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 209038 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 215509 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 215509 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 15148108 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 15148108 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 15148108 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 15148108 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200238 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.200238 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316135 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.316135 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108368 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108368 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000019 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000019 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.247264 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.247264 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.247264 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.247264 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18774.524000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 18774.524000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33336.348009 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33336.348009 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13516.841037 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13516.841037 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19125 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19125 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26328.831059 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26328.831059 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26328.831059 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26328.831059 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 2181836 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 774 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 95774 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 6 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.781089 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 129 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 840875 # number of writebacks
-system.cpu.dcache.writebacks::total 840875 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718560 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 718560 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642321 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1642321 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5210 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 5210 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 2360881 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 2360881 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 2360881 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 2360881 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084017 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1084017 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300427 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 300427 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17539 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 17539 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1384444 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1384444 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1384444 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1384444 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21793042000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 21793042000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9888893772 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 9888893772 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199306000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199306000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31681935772 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 31681935772 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31681935772 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 31681935772 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423882500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423882500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997678998 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997678998 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421561498 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421561498 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120250 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120250 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048869 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048869 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083994 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083994 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091308 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.091308 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091308 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.091308 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20103.967004 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20103.967004 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32916.128617 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32916.128617 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11363.589714 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11363.589714 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22884.230617 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22884.230617 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22884.230617 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22884.230617 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 840320 # number of writebacks
+system.cpu.dcache.writebacks::total 840320 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718906 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 718906 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642971 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1642971 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5109 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 5109 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 2361877 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 2361877 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2361877 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2361877 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083563 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1083563 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300143 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 300143 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17544 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 17544 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1383706 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1383706 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1383706 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1383706 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21325000500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 21325000500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9835893766 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 9835893766 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200292500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200292500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 68500 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 68500 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31160894266 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 31160894266 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31160894266 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 31160894266 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423890500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423890500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997911498 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997911498 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421801998 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421801998 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120374 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120374 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048832 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048832 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083927 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083927 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000019 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091345 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.091345 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091345 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.091345 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19680.443592 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19680.443592 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32770.691857 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32770.691857 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11416.581167 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11416.581167 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17125 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17125 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22519.880861 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22519.880861 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22519.880861 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22519.880861 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei 211025 # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0 74671 40.97% 40.97% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei 210999 # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 105575 57.93% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 182256 # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0 73304 49.32% 49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::31 105559 57.93% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total 182230 # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31 73304 49.32% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1817868211500 98.03% 98.03% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 63824000 0.00% 98.04% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 559692500 0.03% 98.07% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 35817544000 1.93% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1854309272000 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0 1818335798500 98.06% 98.06% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21 63864000 0.00% 98.06% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22 549180000 0.03% 98.09% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 35357724000 1.91% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1854306566500 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31 0.694331 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total 0.815435 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31 0.694342 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total 0.815442 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl 175141 91.23% 93.44% # number of callpals executed
+system.cpu.kern.callpal::swpipl 175115 91.23% 93.43% # number of callpals executed
system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 191985 # number of callpals executed
+system.cpu.kern.callpal::total 191959 # number of callpals executed
system.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches
system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 29467227000 1.59% 1.59% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 2708568500 0.15% 1.74% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1822133468500 98.26% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::kernel 29457551500 1.59% 1.59% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 2704315000 0.15% 1.73% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1822144692000 98.27% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 1.841686 # Number of seconds simulated
-sim_ticks 1841685645500 # Number of ticks simulated
-final_tick 1841685645500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 1841685557500 # Number of ticks simulated
+final_tick 1841685557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 300759 # Simulator instruction rate (inst/s)
-host_op_rate 300759 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 7981184825 # Simulator tick rate (ticks/s)
-host_mem_usage 313952 # Number of bytes of host memory used
-host_seconds 230.75 # Real time elapsed on the host
-sim_insts 69401254 # Number of instructions simulated
-sim_ops 69401254 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 474368 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 19389440 # Number of bytes read from this memory
+host_inst_rate 244491 # Simulator instruction rate (inst/s)
+host_op_rate 244491 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6478446279 # Simulator tick rate (ticks/s)
+host_mem_usage 315916 # Number of bytes of host memory used
+host_seconds 284.28 # Real time elapsed on the host
+sim_insts 69503534 # Number of instructions simulated
+sim_ops 69503534 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 474240 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 19348096 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 150272 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 2812736 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 293952 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 2665600 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28438656 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 474368 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 150272 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 293952 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 918592 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7476160 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7476160 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 7412 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 302960 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu1.inst 150080 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 2814720 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 294912 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 2705088 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28439424 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 474240 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 150080 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 294912 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 919232 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7476992 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7476992 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 7410 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 302314 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2348 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 43949 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 4593 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 41650 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 444354 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 116815 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 116815 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 257573 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 10528094 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu1.inst 2345 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 43980 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 4608 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 42267 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 444366 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 116828 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 116828 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 257503 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 10505646 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1440142 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 81595 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1527262 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 159610 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 1447370 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15441645 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 257573 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 81595 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 159610 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 498778 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4059412 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4059412 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4059412 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 257573 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 10528094 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 81491 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 1528339 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 160132 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 1468811 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15442063 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 257503 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 81491 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 160132 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 499125 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4059864 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4059864 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4059864 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 257503 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 10505646 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1440142 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 81595 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 1527262 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 159610 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 1447370 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19501057 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 109303 # Total number of read requests seen
-system.physmem.writeReqs 45531 # Total number of write requests seen
-system.physmem.cpureqs 156037 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 6995392 # Total number of bytes read from memory
-system.physmem.bytesWritten 2913984 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 6995392 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 2913984 # bytesWritten derated as per pkt->getSize()
+system.physmem.bw_total::cpu1.inst 81491 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 1528339 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 160132 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 1468811 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19501926 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 109963 # Total number of read requests seen
+system.physmem.writeReqs 45515 # Total number of write requests seen
+system.physmem.cpureqs 155620 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 7037632 # Total number of bytes read from memory
+system.physmem.bytesWritten 2912960 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 7037632 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 2912960 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 6 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 41 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 6941 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 6714 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 6576 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 6492 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 6845 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 6834 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 6769 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 6799 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 7016 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 6828 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 7161 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 6927 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 6799 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 6925 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 6890 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 6781 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 2987 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 2793 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 2679 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 2608 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 2843 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 2755 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 2723 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 2826 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 3041 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 2937 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 3162 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 2868 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 2817 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 2876 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 2850 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 2766 # Track writes on a per bank basis
+system.physmem.neitherReadNorWrite 40 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 6991 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 6778 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 6646 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 6540 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 6897 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 6863 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 6800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 6833 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 7049 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 6858 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 7191 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 6954 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 6826 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 6963 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 6923 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 6845 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 2979 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 2790 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 2684 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 2595 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 2850 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 2752 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 2726 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 2828 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 3044 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 2935 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 3156 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 2867 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 2811 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 2879 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 2851 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 2768 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1002 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1840673558000 # Total gap between requests
+system.physmem.numWrRetry 102 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1840673470000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 109303 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 46533 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 41 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 80133 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 9534 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 5401 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1969 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 1272 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1200 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1099 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 1096 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1079 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1052 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 614 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 596 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 576 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 554 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 569 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 582 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 666 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 614 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 379 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see
+system.physmem.readPktSize::6 109963 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 45515 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 80954 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 9408 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 5332 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1972 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 1281 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1214 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1104 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 1103 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 1081 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1065 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 619 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 593 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 572 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 559 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 551 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 575 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 664 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 615 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 374 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 319 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1276 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1440 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1626 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1648 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1852 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1983 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1980 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1976 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1975 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::10 1979 # What write queue length does an incoming req see
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system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
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-system.cpu0.num_func_calls 807221 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4255838 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 30227600 # number of integer instructions
-system.cpu0.num_fp_insts 167714 # number of float instructions
-system.cpu0.num_int_register_reads 42120330 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 22107857 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 86620 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 88185 # number of times the floating registers were written
-system.cpu0.num_mem_refs 8395829 # number of memory refs
-system.cpu0.num_load_insts 4891258 # Number of load instructions
-system.cpu0.num_store_insts 3504571 # Number of store instructions
-system.cpu0.num_idle_cycles 213109834303.356140 # Number of idle cycles
-system.cpu0.num_busy_cycles -212181309746.356140 # Number of busy cycles
-system.cpu0.not_idle_fraction -228.514484 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 229.514484 # Percentage of idle cycles
+system.cpu0.committedInsts 32518253 # Number of instructions committed
+system.cpu0.committedOps 32518253 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 30397519 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 168035 # Number of float alu accesses
+system.cpu0.num_func_calls 808172 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 4307008 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 30397519 # number of integer instructions
+system.cpu0.num_fp_insts 168035 # number of float instructions
+system.cpu0.num_int_register_reads 42396693 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 22221610 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 86774 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 88345 # number of times the floating registers were written
+system.cpu0.num_mem_refs 8404498 # number of memory refs
+system.cpu0.num_load_insts 4895120 # Number of load instructions
+system.cpu0.num_store_insts 3509378 # Number of store instructions
+system.cpu0.num_idle_cycles 214025441196.436279 # Number of idle cycles
+system.cpu0.num_busy_cycles -213096901471.436279 # Number of busy cycles
+system.cpu0.not_idle_fraction -229.496806 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 230.496806 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 211363 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 74796 40.97% 40.97% # number of times we switched to this ipl
+system.cpu0.kern.inst.quiesce 6423 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 211357 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 105684 57.89% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 182561 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 73429 49.30% 49.30% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_count::31 105682 57.89% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 182557 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 73429 49.30% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 148939 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1818585888500 98.75% 98.75% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 39023500 0.00% 98.75% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 363355500 0.02% 98.77% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 22696621500 1.23% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1841684889000 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1818586321500 98.75% 98.75% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 38755000 0.00% 98.75% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 363405500 0.02% 98.77% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 22696319000 1.23% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1841684801000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.694798 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.815831 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31 0.694792 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total 0.815827 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
+system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed
system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 175304 91.20% 93.41% # number of callpals executed
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system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 192218 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches
+system.cpu0.kern.callpal::total 192213 # number of callpals executed
+system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches
+system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 2095 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1908
-system.cpu0.kern.mode_good::user 1738
+system.cpu0.kern.mode_good::kernel 1909
+system.cpu0.kern.mode_good::user 1739
system.cpu0.kern.mode_good::idle 170
-system.cpu0.kern.mode_switch_good::kernel 0.322134 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.322357 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 29741940500 1.61% 1.61% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 2557110500 0.14% 1.75% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle 1809385834500 98.25% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 4178 # number of times the context was actually changed
+system.cpu0.kern.mode_switch_good::total 0.391349 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 29734416500 1.61% 1.61% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 2561211500 0.14% 1.75% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::idle 1809389169500 98.25% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.swap_context 4177 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu0.icache.replacements 952688 # number of replacements
-system.cpu0.icache.tagsinuse 511.197182 # Cycle average of tags in use
-system.cpu0.icache.total_refs 41854962 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 953199 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 43.909994 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 10248069000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 255.807414 # Average occupied blocks per requestor
-system.cpu0.icache.occ_blocks::cpu1.inst 79.618511 # Average occupied blocks per requestor
-system.cpu0.icache.occ_blocks::cpu2.inst 175.771257 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.499624 # Average percentage of cache occupancy
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-system.cpu0.icache.occ_percent::total 0.998432 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 31831928 # number of ReadReq hits
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+system.cpu0.icache.warmup_cycle 10246755000 # Cycle when the warmup percentage was hit.
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system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27001.966169 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25244.761290 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25878.481590 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11191.290470 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12723.962127 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12286.597267 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21505.542266 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18626.405471 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19502.171169 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21505.542266 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18626.405471 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19502.171169 # average overall mshr miss latency
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5558 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7751 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 1 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data 152567 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data 347068 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 499635 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data 152567 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data 347068 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 499635 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1975725000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4306208500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6281933500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1299140000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2144349624 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3443489624 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24977000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 70824000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95801000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3274865000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6450558124 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 9725423124 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3274865000 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6450558124 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 9725423124 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287731500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 345150500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 632882000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 357324500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 421745500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 779070000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 645056000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 766896000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1411952000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086890 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088411 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041068 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.052979 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045452 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021633 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.102047 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.100173 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.038166 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072309 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071790 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.033138 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072309 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071790 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.033138 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18905.735666 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16432.836989 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17137.858645 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27029.939871 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25222.004775 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25874.946454 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11389.420885 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12742.713206 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12359.824539 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21465.094024 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18585.862494 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19465.055739 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21465.094024 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18585.862494 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19465.055739 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 1220324 # DTB read hits
-system.cpu1.dtb.read_misses 1556 # DTB read misses
-system.cpu1.dtb.read_acv 46 # DTB read access violations
-system.cpu1.dtb.read_accesses 144016 # DTB read accesses
-system.cpu1.dtb.write_hits 928239 # DTB write hits
-system.cpu1.dtb.write_misses 207 # DTB write misses
+system.cpu1.dtb.read_hits 1221793 # DTB read hits
+system.cpu1.dtb.read_misses 1550 # DTB read misses
+system.cpu1.dtb.read_acv 45 # DTB read access violations
+system.cpu1.dtb.read_accesses 143987 # DTB read accesses
+system.cpu1.dtb.write_hits 928954 # DTB write hits
+system.cpu1.dtb.write_misses 206 # DTB write misses
system.cpu1.dtb.write_acv 24 # DTB write access violations
-system.cpu1.dtb.write_accesses 60107 # DTB write accesses
-system.cpu1.dtb.data_hits 2148563 # DTB hits
-system.cpu1.dtb.data_misses 1763 # DTB misses
-system.cpu1.dtb.data_acv 70 # DTB access violations
-system.cpu1.dtb.data_accesses 204123 # DTB accesses
-system.cpu1.itb.fetch_hits 875123 # ITB hits
-system.cpu1.itb.fetch_misses 774 # ITB misses
+system.cpu1.dtb.write_accesses 60098 # DTB write accesses
+system.cpu1.dtb.data_hits 2150747 # DTB hits
+system.cpu1.dtb.data_misses 1756 # DTB misses
+system.cpu1.dtb.data_acv 69 # DTB access violations
+system.cpu1.dtb.data_accesses 204085 # DTB accesses
+system.cpu1.itb.fetch_hits 875028 # ITB hits
+system.cpu1.itb.fetch_misses 772 # ITB misses
system.cpu1.itb.fetch_acv 46 # ITB acv
-system.cpu1.itb.fetch_accesses 875897 # ITB accesses
+system.cpu1.itb.fetch_accesses 875800 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 953544041 # number of cpu cycles simulated
+system.cpu1.numCycles 953543873 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 7861950 # Number of instructions committed
-system.cpu1.committedOps 7861950 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 7314131 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 45433 # Number of float alu accesses
-system.cpu1.num_func_calls 212083 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 960162 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 7314131 # number of integer instructions
-system.cpu1.num_fp_insts 45433 # number of float instructions
-system.cpu1.num_int_register_reads 10166174 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 5323213 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 24545 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 24803 # number of times the floating registers were written
-system.cpu1.num_mem_refs 2156447 # number of memory refs
-system.cpu1.num_load_insts 1225739 # Number of load instructions
-system.cpu1.num_store_insts 930708 # Number of store instructions
-system.cpu1.num_idle_cycles 195910527.476772 # Number of idle cycles
-system.cpu1.num_busy_cycles 757633513.523228 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.794545 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.205455 # Percentage of idle cycles
+system.cpu1.committedInsts 7871049 # Number of instructions committed
+system.cpu1.committedOps 7871049 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 7322486 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 45486 # Number of float alu accesses
+system.cpu1.num_func_calls 212361 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 961543 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 7322486 # number of integer instructions
+system.cpu1.num_fp_insts 45486 # number of float instructions
+system.cpu1.num_int_register_reads 10177666 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 5328829 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 24537 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 24857 # number of times the floating registers were written
+system.cpu1.num_mem_refs 2158619 # number of memory refs
+system.cpu1.num_load_insts 1227197 # Number of load instructions
+system.cpu1.num_store_insts 931422 # Number of store instructions
+system.cpu1.num_idle_cycles -1678612352.135852 # Number of idle cycles
+system.cpu1.num_busy_cycles 2632156225.135852 # Number of busy cycles
+system.cpu1.not_idle_fraction 2.760393 # Percentage of non-idle cycles
+system.cpu1.idle_fraction -1.760393 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu1.kern.swap_context 0 # number of times the context was actually changed
-system.cpu2.branchPred.lookups 8412639 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 7718594 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 129283 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 6816710 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 5762097 # Number of BTB hits
+system.cpu2.branchPred.lookups 8388883 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 7698653 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 129790 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 6809522 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 5746337 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 84.529003 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 288281 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 15520 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 84.386790 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 285994 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 15305 # Number of incorrect RAS predictions.
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
-system.cpu2.dtb.read_hits 3230838 # DTB read hits
-system.cpu2.dtb.read_misses 11458 # DTB read misses
-system.cpu2.dtb.read_acv 112 # DTB read access violations
-system.cpu2.dtb.read_accesses 217040 # DTB read accesses
-system.cpu2.dtb.write_hits 2001661 # DTB write hits
-system.cpu2.dtb.write_misses 2605 # DTB write misses
-system.cpu2.dtb.write_acv 143 # DTB write access violations
-system.cpu2.dtb.write_accesses 81606 # DTB write accesses
-system.cpu2.dtb.data_hits 5232499 # DTB hits
-system.cpu2.dtb.data_misses 14063 # DTB misses
-system.cpu2.dtb.data_acv 255 # DTB access violations
-system.cpu2.dtb.data_accesses 298646 # DTB accesses
-system.cpu2.itb.fetch_hits 371716 # ITB hits
-system.cpu2.itb.fetch_misses 5691 # ITB misses
-system.cpu2.itb.fetch_acv 245 # ITB acv
-system.cpu2.itb.fetch_accesses 377407 # ITB accesses
+system.cpu2.dtb.read_hits 3222753 # DTB read hits
+system.cpu2.dtb.read_misses 11767 # DTB read misses
+system.cpu2.dtb.read_acv 114 # DTB read access violations
+system.cpu2.dtb.read_accesses 216394 # DTB read accesses
+system.cpu2.dtb.write_hits 1997746 # DTB write hits
+system.cpu2.dtb.write_misses 2597 # DTB write misses
+system.cpu2.dtb.write_acv 133 # DTB write access violations
+system.cpu2.dtb.write_accesses 81219 # DTB write accesses
+system.cpu2.dtb.data_hits 5220499 # DTB hits
+system.cpu2.dtb.data_misses 14364 # DTB misses
+system.cpu2.dtb.data_acv 247 # DTB access violations
+system.cpu2.dtb.data_accesses 297613 # DTB accesses
+system.cpu2.itb.fetch_hits 371919 # ITB hits
+system.cpu2.itb.fetch_misses 5650 # ITB misses
+system.cpu2.itb.fetch_acv 270 # ITB acv
+system.cpu2.itb.fetch_accesses 377569 # ITB accesses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
system.cpu2.itb.data_misses 0 # DTB misses
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
-system.cpu2.numCycles 30535693 # number of cpu cycles simulated
+system.cpu2.numCycles 30487191 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 8533990 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 34964700 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 8412639 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 6050378 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 8133501 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 621341 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles 9684407 # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles 10316 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 1948 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 62496 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 78611 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 2608255 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 90277 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples 26910349 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.299303 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.309788 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 8524791 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 34873991 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 8388883 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 6032331 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 8111828 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 622665 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles 9676306 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles 10691 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 1940 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 62420 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 80561 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 496 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 2604903 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 90729 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples 26874751 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.297649 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.309099 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 18776848 69.78% 69.78% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 272793 1.01% 70.79% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 440434 1.64% 72.43% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 4254202 15.81% 88.23% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 737771 2.74% 90.98% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 167398 0.62% 91.60% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 196636 0.73% 92.33% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 433593 1.61% 93.94% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 1630674 6.06% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 18762923 69.82% 69.82% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 273694 1.02% 70.83% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 440641 1.64% 72.47% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 4237897 15.77% 88.24% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 736346 2.74% 90.98% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 166761 0.62% 91.60% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 196079 0.73% 92.33% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 433619 1.61% 93.95% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 1626791 6.05% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 26910349 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.275502 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 1.145044 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 8661368 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 9779389 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 7537152 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 294171 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 392385 # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved 168928 # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred 12969 # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts 34563096 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 40760 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 392385 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 9017327 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 2819479 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 5795758 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 7393745 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 1245780 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 33400490 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 2356 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 234346 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 410986 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands 22419818 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 41624592 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 41459015 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 165577 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 20587002 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 1832816 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 505460 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 60216 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 3692921 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 3393863 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 2097986 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 374319 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 252386 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 30873003 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 630971 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 30415505 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 38395 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 2194500 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 1105040 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 445283 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 26910349 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.130253 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.565605 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 26874751 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.275161 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 1.143890 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 8657787 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 9768162 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 7515953 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 293497 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 393434 # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved 168963 # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred 12933 # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts 34472576 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 40526 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 393434 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 9012684 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 2836795 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 5769605 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 7372565 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 1243759 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 33316352 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 2373 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 234595 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents 408588 # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands 22366948 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 41510379 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 41345500 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 164879 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 20534540 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 1832408 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 504738 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 60071 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 3686935 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 3385510 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 2088081 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 373278 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 254690 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 30792200 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 629969 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 30337437 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 32004 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 2187587 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 1093629 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 444846 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 26874751 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.128845 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.565283 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 15319532 56.93% 56.93% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 3107477 11.55% 68.48% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 1555924 5.78% 74.26% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 5075651 18.86% 93.12% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 913363 3.39% 96.51% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 492005 1.83% 98.34% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 286833 1.07% 99.41% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 141760 0.53% 99.93% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 17804 0.07% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 15311841 56.97% 56.97% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 3103500 11.55% 68.52% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 1551808 5.77% 74.30% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 5059769 18.83% 93.12% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 912287 3.39% 96.52% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 489619 1.82% 98.34% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 286015 1.06% 99.40% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 141615 0.53% 99.93% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 18297 0.07% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 26910349 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 26874751 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 34989 13.90% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.90% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 113310 45.00% 58.89% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 103504 41.11% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 34821 13.89% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.89% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 112497 44.88% 58.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 103352 41.23% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 2444 0.01% 0.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 24705611 81.23% 81.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 20302 0.07% 81.30% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass 2448 0.01% 0.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 24640378 81.22% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 20252 0.07% 81.30% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 8486 0.03% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 1222 0.00% 81.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 8482 0.03% 81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 3362290 11.05% 92.39% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 2024696 6.66% 99.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess 290454 0.95% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 3354206 11.06% 92.38% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 2020424 6.66% 99.04% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess 290023 0.96% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 30415505 # Type of FU issued
-system.cpu2.iq.rate 0.996064 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 251803 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.008279 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 87793654 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 33586184 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 30009842 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 237903 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 116334 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 112629 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 30540947 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 123917 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 191281 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 30337437 # Type of FU issued
+system.cpu2.iq.rate 0.995088 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 250670 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.008263 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 87595744 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 33498169 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 29934734 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 236555 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 115613 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 112132 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 30462481 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 123178 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 189585 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 420180 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 991 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 4150 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 166079 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 417411 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 964 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 4105 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 161809 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 4737 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 23355 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 4731 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 22958 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 392385 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 2039220 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 211536 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 32790350 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 224390 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 3393863 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 2097986 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 560382 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 149727 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 2248 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 4150 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 66680 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 129831 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 196511 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 30250749 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 3250588 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 164756 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 393434 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 2055085 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 212014 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 32707784 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 224122 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 3385510 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 2088081 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 559310 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 150319 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 2295 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 4105 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 66873 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 130024 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 196897 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 30173481 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 3242841 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 163956 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 1286376 # number of nop insts executed
-system.cpu2.iew.exec_refs 5259365 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 6817857 # Number of branches executed
-system.cpu2.iew.exec_stores 2008777 # Number of stores executed
-system.cpu2.iew.exec_rate 0.990668 # Inst execution rate
-system.cpu2.iew.wb_sent 30155480 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 30122471 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 17393530 # num instructions producing a value
-system.cpu2.iew.wb_consumers 20640200 # num instructions consuming a value
+system.cpu2.iew.exec_nop 1285615 # number of nop insts executed
+system.cpu2.iew.exec_refs 5247672 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 6797242 # Number of branches executed
+system.cpu2.iew.exec_stores 2004831 # Number of stores executed
+system.cpu2.iew.exec_rate 0.989710 # Inst execution rate
+system.cpu2.iew.wb_sent 30079535 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 30046866 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 17352028 # num instructions producing a value
+system.cpu2.iew.wb_consumers 20589621 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 0.986468 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.842702 # average fanout of values written-back
+system.cpu2.iew.wb_rate 0.985557 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.842756 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 2374784 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 185688 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 182289 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 26517964 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.145283 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.851177 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 2372790 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 185123 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 182681 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 26481317 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.143824 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.850690 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 16375646 61.75% 61.75% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 2329504 8.78% 70.54% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1218959 4.60% 75.13% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 4807373 18.13% 93.26% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 502647 1.90% 95.16% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 186921 0.70% 95.86% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 179411 0.68% 96.54% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 180660 0.68% 97.22% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 736843 2.78% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 16366667 61.80% 61.80% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 2324205 8.78% 70.58% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1216165 4.59% 75.17% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 4790733 18.09% 93.26% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 501931 1.90% 95.16% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 186373 0.70% 95.86% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 179761 0.68% 96.54% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 180772 0.68% 97.23% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 734710 2.77% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 26517964 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 30370564 # Number of instructions committed
-system.cpu2.commit.committedOps 30370564 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 26481317 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 30289973 # Number of instructions committed
+system.cpu2.commit.committedOps 30289973 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 4905590 # Number of memory references committed
-system.cpu2.commit.loads 2973683 # Number of loads committed
-system.cpu2.commit.membars 65235 # Number of memory barriers committed
-system.cpu2.commit.branches 6667985 # Number of branches committed
-system.cpu2.commit.fp_insts 111312 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 28908366 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 232233 # Number of function calls committed.
-system.cpu2.commit.bw_lim_events 736843 # number cycles where commit BW limit reached
+system.cpu2.commit.refs 4894371 # Number of memory references committed
+system.cpu2.commit.loads 2968099 # Number of loads committed
+system.cpu2.commit.membars 65019 # Number of memory barriers committed
+system.cpu2.commit.branches 6647353 # Number of branches committed
+system.cpu2.commit.fp_insts 110870 # Number of committed floating point instructions.
+system.cpu2.commit.int_insts 28830509 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 231619 # Number of function calls committed.
+system.cpu2.commit.bw_lim_events 734710 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 58454819 # The number of ROB reads
-system.cpu2.rob.rob_writes 65882909 # The number of ROB writes
-system.cpu2.timesIdled 242872 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 3625344 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 1745288097 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 29192895 # Number of Instructions Simulated
-system.cpu2.committedOps 29192895 # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total 29192895 # Number of Instructions Simulated
-system.cpu2.cpi 1.045997 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 1.045997 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.956025 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.956025 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 39779596 # number of integer regfile reads
-system.cpu2.int_regfile_writes 21289109 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 68643 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 68941 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 4607989 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 260558 # number of misc regfile writes
+system.cpu2.rob.rob_reads 58337288 # The number of ROB reads
+system.cpu2.rob.rob_writes 65718838 # The number of ROB writes
+system.cpu2.timesIdled 243105 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 3612440 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 1745337726 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 29114232 # Number of Instructions Simulated
+system.cpu2.committedOps 29114232 # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total 29114232 # Number of Instructions Simulated
+system.cpu2.cpi 1.047158 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.047158 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.954966 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.954966 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 39679960 # number of integer regfile reads
+system.cpu2.int_regfile_writes 21237504 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 68414 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 68689 # number of floating regfile writes
+system.cpu2.misc_regfile_reads 4591435 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 259923 # number of misc regfile writes
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed
---------- Begin Simulation Statistics ----------
-sim_seconds 2.533148 # Number of seconds simulated
-sim_ticks 2533147650000 # Number of ticks simulated
-final_tick 2533147650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.533144 # Number of seconds simulated
+sim_ticks 2533143504000 # Number of ticks simulated
+final_tick 2533143504000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 55856 # Simulator instruction rate (inst/s)
-host_op_rate 71871 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2346171672 # Simulator tick rate (ticks/s)
-host_mem_usage 407620 # Number of bytes of host memory used
-host_seconds 1079.69 # Real time elapsed on the host
-sim_insts 60307315 # Number of instructions simulated
-sim_ops 77598799 # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 65433 # Simulator instruction rate (inst/s)
+host_op_rate 84194 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2748425484 # Simulator tick rate (ticks/s)
+host_mem_usage 408856 # Number of bytes of host memory used
+host_seconds 921.67 # Real time elapsed on the host
+sim_insts 60307579 # Number of instructions simulated
+sim_ops 77599125 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 795840 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9093648 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129429904 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 795840 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 795840 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3782016 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 796736 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9093520 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129430672 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 796736 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 796736 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3782592 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6798088 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6798664 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12435 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142122 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096808 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59094 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12449 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142120 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096820 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59103 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813112 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47189379 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813121 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47189456 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 314170 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3589861 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51094497 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 314170 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314170 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1493010 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1190642 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2683652 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1493010 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47189379 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 314525 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3589816 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51094883 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 314525 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 314525 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1493240 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1190644 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2683884 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1493240 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47189456 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314170 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4780503 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53778149 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15096808 # Total number of read requests seen
-system.physmem.writeReqs 813112 # Total number of write requests seen
-system.physmem.cpureqs 218335 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 966195712 # Total number of bytes read from memory
-system.physmem.bytesWritten 52039168 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 129429904 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6798088 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 295 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4677 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 943938 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 943447 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 943391 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 943143 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 943273 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 943781 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 943299 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 943231 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 943694 # Track reads on a per bank basis
+system.physmem.bw_total::cpu.inst 314525 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4780460 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53778768 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096820 # Total number of read requests seen
+system.physmem.writeReqs 813121 # Total number of write requests seen
+system.physmem.cpureqs 218357 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 966196480 # Total number of bytes read from memory
+system.physmem.bytesWritten 52039744 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 129430672 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6798664 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 227 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4678 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 943951 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 943388 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 944196 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 943983 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 943145 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 943274 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 943869 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 943805 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 943304 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 943207 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 943616 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 943708 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 943087 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 942964 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 943610 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50827 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50416 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50443 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51149 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 50907 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::14 942997 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 943623 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50838 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50409 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 50910 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 50180 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50280 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51358 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51187 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51246 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 50619 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51228 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 50279 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51367 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 50902 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 50800 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51241 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 50709 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 50623 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 2236976 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2533146526000 # Total gap between requests
+system.physmem.numWrRetry 2238337 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2533142364000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 36 # Categorize read packet sizes
system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154564 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 2990994 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 59094 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 4677 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1039969 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 980923 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 950073 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3550359 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2676584 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2688258 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2649649 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 60661 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 59173 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 108720 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 157659 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 108272 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 16731 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 21899 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 10876 # What read queue length does an incoming req see
+system.physmem.readPktSize::6 154576 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 754018 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 59103 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 1040115 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 981189 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 950309 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::4 2676376 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2687982 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2649582 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 60790 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 59171 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 108701 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 157630 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 108239 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 16713 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 16586 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 21915 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 10858 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2580 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 2633 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 2680 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 2721 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 2742 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 2771 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 2796 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 2817 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::4 2739 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 2769 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 2793 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 2815 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32773 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 32720 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 32673 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::27 32611 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 32582 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 32557 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 32771 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 32719 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 32676 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 32638 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 32614 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 32584 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 32560 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 32538 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 393223278963 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 485615648963 # Sum of mem lat for all requests
-system.physmem.totBusLat 75482565000 # Total cycles spent in databus access
-system.physmem.totBankLat 16909805000 # Total cycles spent in bank access
-system.physmem.avgQLat 26047.29 # Average queueing delay per request
-system.physmem.avgBankLat 1120.11 # Average bank access latency per request
+system.physmem.totQLat 393245939250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 485641693000 # Sum of mem lat for all requests
+system.physmem.totBusLat 75482965000 # Total cycles spent in databus access
+system.physmem.totBankLat 16912788750 # Total cycles spent in bank access
+system.physmem.avgQLat 26048.65 # Average queueing delay per request
+system.physmem.avgBankLat 1120.31 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 32167.41 # Average memory access latency
+system.physmem.avgMemAccLat 32168.96 # Average memory access latency
system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.14 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.19 # Average read queue length over time
-system.physmem.avgWrQLen 11.48 # Average write queue length over time
-system.physmem.readRowHits 15020221 # Number of row buffer hits during reads
-system.physmem.writeRowHits 793131 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 9.55 # Average write queue length over time
+system.physmem.readRowHits 15020273 # Number of row buffer hits during reads
+system.physmem.writeRowHits 793117 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes
-system.physmem.avgGap 159218.06 # Average gap between requests
+system.physmem.avgGap 159217.58 # Average gap between requests
+system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 14676489 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11762878 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 704619 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9800840 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7950249 # Number of BTB hits
+system.cpu.branchPred.lookups 14678084 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11764424 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 705314 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9806272 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7951789 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 81.118037 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1398960 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 72172 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 81.088807 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1399019 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72620 # Number of incorrect RAS predictions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 14987326 # DTB read hits
+system.cpu.checker.dtb.read_hits 14987411 # DTB read hits
system.cpu.checker.dtb.read_misses 7302 # DTB read misses
-system.cpu.checker.dtb.write_hits 11227680 # DTB write hits
+system.cpu.checker.dtb.write_hits 11227746 # DTB write hits
system.cpu.checker.dtb.write_misses 2189 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 14994628 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 11229869 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 14994713 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 11229935 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 26215006 # DTB hits
+system.cpu.checker.dtb.hits 26215157 # DTB hits
system.cpu.checker.dtb.misses 9491 # DTB misses
-system.cpu.checker.dtb.accesses 26224497 # DTB accesses
-system.cpu.checker.itb.inst_hits 61481313 # ITB inst hits
+system.cpu.checker.dtb.accesses 26224648 # DTB accesses
+system.cpu.checker.itb.inst_hits 61481576 # ITB inst hits
system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 61485784 # ITB inst accesses
-system.cpu.checker.itb.hits 61481313 # DTB hits
+system.cpu.checker.itb.inst_accesses 61486047 # ITB inst accesses
+system.cpu.checker.itb.hits 61481576 # DTB hits
system.cpu.checker.itb.misses 4471 # DTB misses
-system.cpu.checker.itb.accesses 61485784 # DTB accesses
-system.cpu.checker.numCycles 77884604 # number of cpu cycles simulated
+system.cpu.checker.itb.accesses 61486047 # DTB accesses
+system.cpu.checker.numCycles 77884929 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51394402 # DTB read hits
-system.cpu.dtb.read_misses 64202 # DTB read misses
-system.cpu.dtb.write_hits 11700782 # DTB write hits
-system.cpu.dtb.write_misses 15842 # DTB write misses
+system.cpu.dtb.read_hits 51401633 # DTB read hits
+system.cpu.dtb.read_misses 64365 # DTB read misses
+system.cpu.dtb.write_hits 11702282 # DTB write hits
+system.cpu.dtb.write_misses 15903 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 6555 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2475 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 6544 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2575 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 399 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1357 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51458604 # DTB read accesses
-system.cpu.dtb.write_accesses 11716624 # DTB write accesses
+system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51465998 # DTB read accesses
+system.cpu.dtb.write_accesses 11718185 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63095184 # DTB hits
-system.cpu.dtb.misses 80044 # DTB misses
-system.cpu.dtb.accesses 63175228 # DTB accesses
-system.cpu.itb.inst_hits 12330326 # ITB inst hits
-system.cpu.itb.inst_misses 11351 # ITB inst misses
+system.cpu.dtb.hits 63103915 # DTB hits
+system.cpu.dtb.misses 80268 # DTB misses
+system.cpu.dtb.accesses 63184183 # DTB accesses
+system.cpu.itb.inst_hits 12333169 # ITB inst hits
+system.cpu.itb.inst_misses 11311 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 4952 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 4950 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2994 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2979 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 12341677 # ITB inst accesses
-system.cpu.itb.hits 12330326 # DTB hits
-system.cpu.itb.misses 11351 # DTB misses
-system.cpu.itb.accesses 12341677 # DTB accesses
-system.cpu.numCycles 471833351 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 12344480 # ITB inst accesses
+system.cpu.itb.hits 12333169 # DTB hits
+system.cpu.itb.misses 11311 # DTB misses
+system.cpu.itb.accesses 12344480 # DTB accesses
+system.cpu.numCycles 471839315 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 30572359 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 96029601 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14676489 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9349209 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 21156129 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5298120 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 120373 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 95586316 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 87050 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 195749 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 271 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 12326631 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 900507 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5718 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 151357354 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.785025 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.150266 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 30570275 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 96049459 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14678084 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9350808 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 21162167 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5300670 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 119262 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 95593563 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2640 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 87521 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 195771 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 307 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 12329483 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 900673 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5698 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 151369698 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.785111 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.150333 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 130216652 86.03% 86.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1302204 0.86% 86.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1711626 1.13% 88.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2495193 1.65% 89.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2215033 1.46% 91.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1107976 0.73% 91.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2757688 1.82% 93.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 745754 0.49% 94.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8805228 5.82% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 130222829 86.03% 86.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1303268 0.86% 86.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1713149 1.13% 88.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2496945 1.65% 89.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2215858 1.46% 91.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1107759 0.73% 91.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2757122 1.82% 93.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 745476 0.49% 94.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8807292 5.82% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 151357354 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.031105 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.203524 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 32536934 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 95207461 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19182239 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 963280 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3467440 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1956290 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 171623 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 112620131 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 567256 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3467440 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 34479585 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36699027 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 52520178 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18147266 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6043858 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 106106757 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 20523 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1005521 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4063485 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 592 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 110532069 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 485468581 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 485377824 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 90757 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78389582 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 32142486 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 830463 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 737014 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12171984 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 20324763 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13518088 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1981188 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2478536 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 97936678 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1983499 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 124321529 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 167156 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 21750573 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 57066044 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 501117 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 151357354 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.821378 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.534899 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 151369698 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.031108 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.203564 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 32533087 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 95216874 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 19187667 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 962846 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3469224 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1957624 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 171486 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 112641564 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 566291 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3469224 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 34475717 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36705773 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 52523534 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 18152425 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6043025 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 106121315 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 20520 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1004083 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4063852 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 628 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 110544866 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 485535846 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 485445234 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 90612 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78389874 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 32154991 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 830680 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 737251 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12167564 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 20329502 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13519419 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1975005 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2483431 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 97943833 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1983956 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 124335595 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 167777 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 21753420 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 57059209 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 501571 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 151369698 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.821403 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.534931 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 107117235 70.77% 70.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13550856 8.95% 79.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7067177 4.67% 84.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5940673 3.92% 88.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12604400 8.33% 96.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2784028 1.84% 98.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1701066 1.12% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 465188 0.31% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 126731 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 107127102 70.77% 70.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13547292 8.95% 79.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7070046 4.67% 84.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5943115 3.93% 88.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12603566 8.33% 96.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2786171 1.84% 98.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1700250 1.12% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 465001 0.31% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 127155 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 151357354 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 151369698 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 61039 0.69% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 3 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 60916 0.69% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8364044 94.63% 95.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 413790 4.68% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8365801 94.64% 95.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 413031 4.67% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 58631158 47.16% 47.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 93232 0.07% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 58634354 47.16% 47.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 93273 0.08% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 18 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52911235 42.56% 90.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12320074 9.91% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52919784 42.56% 90.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12322346 9.91% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 124321529 # Type of FU issued
-system.cpu.iq.rate 0.263486 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8838876 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071097 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 409062941 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 121687155 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 85967434 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23205 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12488 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10289 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 132784424 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12315 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 622437 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 124335595 # Type of FU issued
+system.cpu.iq.rate 0.263513 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8839750 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071096 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 409105295 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 121697619 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 85975011 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23030 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12486 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10280 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 132799466 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12213 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 624029 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4670323 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6258 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30023 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1786078 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4674977 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6508 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 30066 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1787339 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107730 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 893047 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34107736 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 893802 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3467440 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 27945377 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 433355 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 100140842 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 200439 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 20324763 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13518088 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1411116 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 112674 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3579 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30023 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 350481 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 268612 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 619093 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 121545908 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52081707 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2775621 # Number of squashed instructions skipped in execute
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+system.cpu.iew.iewUnblockCycles 432986 # Number of cycles IEW is unblocking
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+system.cpu.iew.iewLSQFullEvents 3588 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 220665 # number of nop insts executed
-system.cpu.iew.exec_refs 64294282 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11561887 # Number of branches executed
-system.cpu.iew.exec_stores 12212575 # Number of stores executed
-system.cpu.iew.exec_rate 0.257603 # Inst execution rate
-system.cpu.iew.wb_sent 120387103 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 85977723 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47219839 # num instructions producing a value
-system.cpu.iew.wb_consumers 88163371 # num instructions consuming a value
+system.cpu.iew.exec_nop 220929 # number of nop insts executed
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.182221 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.535595 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.182234 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535590 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 21484846 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1482382 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 535483 # The number of times a branch was mispredicted
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-system.cpu.commit.committed_per_cycle::mean 0.525723 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.514974 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 120439692 81.44% 81.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13316642 9.00% 90.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3906186 2.64% 93.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2120970 1.43% 94.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1946250 1.32% 95.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 970441 0.66% 96.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1598227 1.08% 97.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 701359 0.47% 98.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2890147 1.95% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 120451739 81.44% 81.44% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::2 3905098 2.64% 93.09% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::4 1946193 1.32% 95.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 968094 0.65% 96.49% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::7 702304 0.47% 98.05% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 147889914 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60457696 # Number of instructions committed
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
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-system.cpu.commit.function_calls 991256 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2890147 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu.idleCycles 320475997 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4594378908 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60307315 # Number of Instructions Simulated
-system.cpu.committedOps 77598799 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 60307315 # Number of Instructions Simulated
-system.cpu.cpi 7.823816 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.823816 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.127815 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.127815 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 550300284 # number of integer regfile reads
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-system.cpu.icache.avg_refs 11.491631 # Average number of references to valid blocks.
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+system.cpu.committedOps 77599125 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 60307579 # Number of Instructions Simulated
+system.cpu.cpi 7.823881 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.823881 # CPI: Total CPI of All Threads
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system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit.
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use
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system.cpu.dcache.warmup_cycle 42249000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36729406082 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36729406082 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219125045582 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 219125045582 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026617 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026617 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024357 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047424 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047424 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12466.156523 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12466.156523 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32865.097408 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32865.097408 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11564.117309 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11564.117309 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14600 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14600 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20469.298364 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20469.298364 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20469.298364 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20469.298364 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 607840 # number of writebacks
+system.cpu.dcache.writebacks::total 607840 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351729 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 351729 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713855 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2713855 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1338 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1338 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3065584 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3065584 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3065584 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3065584 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385880 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 385880 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248957 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 248957 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12175 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12175 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 634837 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 634837 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 634837 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 634837 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4811592500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4811592500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8182885914 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8182885914 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141167000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141167000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 190000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 190000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12994478414 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 12994478414 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12994478414 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 12994478414 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395775000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395775000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36742499011 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36742499011 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219138274011 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 219138274011 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026624 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026624 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024354 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024354 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047431 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047431 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025685 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025685 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025685 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025685 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12469.141961 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12469.141961 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32868.671755 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32868.671755 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11594.825462 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11594.825462 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13571.428571 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13571.428571 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20468.999781 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20468.999781 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20468.999781 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20468.999781 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1229589046447 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1229589046447 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1229610747140 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1229610747140 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 83042 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 1.102937 # Number of seconds simulated
-sim_ticks 1102937390000 # Number of ticks simulated
-final_tick 1102937390000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.102950 # Number of seconds simulated
+sim_ticks 1102950399000 # Number of ticks simulated
+final_tick 1102950399000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 67484 # Simulator instruction rate (inst/s)
-host_op_rate 86868 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1208579190 # Simulator tick rate (ticks/s)
-host_mem_usage 412736 # Number of bytes of host memory used
-host_seconds 912.59 # Real time elapsed on the host
-sim_insts 61585042 # Number of instructions simulated
-sim_ops 79274675 # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 57810 # Simulator instruction rate (inst/s)
+host_op_rate 74418 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1035290197 # Simulator tick rate (ticks/s)
+host_mem_usage 414988 # Number of bytes of host memory used
+host_seconds 1065.35 # Real time elapsed on the host
+sim_insts 61588287 # Number of instructions simulated
+sim_ops 79281553 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 408896 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4378804 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 1280 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 405888 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 5226160 # Number of bytes read from this memory
-system.physmem.bytes_read::total 59180644 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 408896 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 405888 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 814784 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4259456 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 409024 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4368244 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 405632 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 5247408 # Number of bytes read from this memory
+system.physmem.bytes_read::total 59191204 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 409024 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 405632 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 814656 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4268864 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7286800 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7296208 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 6389 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 68491 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 20 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 6342 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 81685 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6257788 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 66554 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 6391 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 68326 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 6338 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 82017 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 6257953 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 66701 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 823390 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 44208116 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 823537 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 44207595 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 116 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 370734 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 3970129 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 1161 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 368006 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 4738401 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 53657301 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 370734 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 368006 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 738740 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3861920 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 232 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 370845 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 3960508 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 367770 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 4757610 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 53666243 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 370845 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 367770 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 738615 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3870404 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 2729388 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6606721 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3861920 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 44208116 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 2729356 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6615173 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3870404 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 44207595 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 116 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 370734 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3985543 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 1161 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 368006 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 7467789 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 60264023 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 6257788 # Total number of read requests seen
-system.physmem.writeReqs 823390 # Total number of write requests seen
-system.physmem.cpureqs 281560 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 400498432 # Total number of bytes read from memory
-system.physmem.bytesWritten 52696960 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 59180644 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7286800 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 80 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 12623 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 391400 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 391208 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 390865 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 391604 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 391517 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 390867 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 390930 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 391637 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 391401 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 390707 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 390849 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 391231 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 391237 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 390522 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 390468 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 391265 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 51411 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 51226 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 51010 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51681 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 51542 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 50958 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50977 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 51664 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 52039 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51352 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51491 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51878 # Track writes on a per bank basis
+system.physmem.bw_total::cpu0.itb.walker 232 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 370845 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 3975921 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 367770 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 7486966 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 60281416 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 6257953 # Total number of read requests seen
+system.physmem.writeReqs 823537 # Total number of write requests seen
+system.physmem.cpureqs 242283 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 400508992 # Total number of bytes read from memory
+system.physmem.bytesWritten 52706368 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 59191204 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7296208 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 121 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 12582 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 391384 # Track reads on a per bank basis
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+system.physmem.perBankRdReqs::3 391625 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 391537 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 390907 # Track reads on a per bank basis
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+system.physmem.perBankWrReqs::0 51392 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::5 50996 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 51845 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51250 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51172 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51894 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 51248 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 51167 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51895 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 2242937 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1102936257500 # Total gap between requests
+system.physmem.numWrRetry 2243059 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1102949217500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 105 # Categorize read packet sizes
system.physmem.readPktSize::3 6094848 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 162835 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 2999773 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
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-system.physmem.writePktSize::5 0 # categorize write packet sizes
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-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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-system.physmem.rdQLenPdf::16 138 # What read queue length does an incoming req see
+system.physmem.readPktSize::6 163000 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
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+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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-system.physmem.wrQLenPdf::20 35799 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 35799 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 199170690855 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 238991050855 # Sum of mem lat for all requests
-system.physmem.totBusLat 31288540000 # Total cycles spent in databus access
-system.physmem.totBankLat 8531820000 # Total cycles spent in bank access
-system.physmem.avgQLat 31828.06 # Average queueing delay per request
-system.physmem.avgBankLat 1363.41 # Average bank access latency per request
+system.physmem.wrQLenPdf::0 2900 # What write queue length does an incoming req see
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+system.physmem.totQLat 199191841750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 239011336750 # Sum of mem lat for all requests
+system.physmem.totBusLat 31289160000 # Total cycles spent in databus access
+system.physmem.totBankLat 8530335000 # Total cycles spent in bank access
+system.physmem.avgQLat 31830.81 # Average queueing delay per request
+system.physmem.avgBankLat 1363.15 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 38191.47 # Average memory access latency
-system.physmem.avgRdBW 363.12 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 47.78 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 53.66 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 38193.95 # Average memory access latency
+system.physmem.avgRdBW 363.13 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 47.79 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 53.67 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 6.62 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.21 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.22 # Average read queue length over time
-system.physmem.avgWrQLen 10.24 # Average write queue length over time
-system.physmem.readRowHits 6213872 # Number of row buffer hits during reads
-system.physmem.writeRowHits 799892 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 11.98 # Average write queue length over time
+system.physmem.readRowHits 6213974 # Number of row buffer hits during reads
+system.physmem.writeRowHits 800028 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 97.15 # Row buffer hit rate for writes
-system.physmem.avgGap 155756.04 # Average gap between requests
-system.l2c.replacements 72539 # number of replacements
-system.l2c.tagsinuse 53752.248637 # Cycle average of tags in use
-system.l2c.total_refs 1841179 # Total number of references to valid blocks.
-system.l2c.sampled_refs 137732 # Sample count of references to valid blocks.
-system.l2c.avg_refs 13.367838 # Average number of references to valid blocks.
+system.physmem.avgGap 155751.01 # Average gap between requests
+system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 72704 # number of replacements
+system.l2c.tagsinuse 53743.106475 # Cycle average of tags in use
+system.l2c.total_refs 1840692 # Total number of references to valid blocks.
+system.l2c.sampled_refs 137860 # Sample count of references to valid blocks.
+system.l2c.avg_refs 13.351893 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 39388.476412 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.dtb.walker 3.826353 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.itb.walker 0.000803 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 4008.993875 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 2816.909683 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker 12.612753 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 3717.226162 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 3804.202595 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.601020 # Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks 39373.484726 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.dtb.walker 3.828040 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.itb.walker 1.177687 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 4008.510797 # Average occupied blocks per requestor
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+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000899 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015949 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.244624 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.244934 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.098720 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000501 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000899 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015949 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.244624 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.244934 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.098720 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45524.469657 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49953.990123 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 46439.556638 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10054.798131 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10171.225755 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10104.107732 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10100.024961 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.560386 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10071.588626 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37275.370609 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41145.112190 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 39398.566983 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38030.596506 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41809.695445 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40473.049037 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38030.596506 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41809.695445 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40473.049037 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 5998436 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 4575399 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 294209 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 3753379 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 2912017 # Number of BTB hits
+system.cpu0.branchPred.lookups 6001263 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 4576664 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 295188 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 3775279 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 2913941 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 77.583878 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 673016 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 28669 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 77.184786 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 673658 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 28611 # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 8902974 # DTB read hits
-system.cpu0.dtb.read_misses 28685 # DTB read misses
-system.cpu0.dtb.write_hits 5134917 # DTB write hits
-system.cpu0.dtb.write_misses 5599 # DTB write misses
+system.cpu0.dtb.read_hits 8907872 # DTB read hits
+system.cpu0.dtb.read_misses 28815 # DTB read misses
+system.cpu0.dtb.write_hits 5138143 # DTB write hits
+system.cpu0.dtb.write_misses 5606 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 1816 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1018 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 297 # Number of TLB faults due to prefetch
+system.cpu0.dtb.align_faults 1053 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 8931659 # DTB read accesses
-system.cpu0.dtb.write_accesses 5140516 # DTB write accesses
+system.cpu0.dtb.perms_faults 532 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 8936687 # DTB read accesses
+system.cpu0.dtb.write_accesses 5143749 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 14037891 # DTB hits
-system.cpu0.dtb.misses 34284 # DTB misses
-system.cpu0.dtb.accesses 14072175 # DTB accesses
-system.cpu0.itb.inst_hits 4215172 # ITB inst hits
-system.cpu0.itb.inst_misses 5141 # ITB inst misses
+system.cpu0.dtb.hits 14046015 # DTB hits
+system.cpu0.dtb.misses 34421 # DTB misses
+system.cpu0.dtb.accesses 14080436 # DTB accesses
+system.cpu0.itb.inst_hits 4220167 # ITB inst hits
+system.cpu0.itb.inst_misses 5223 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1342 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1350 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1479 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1535 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 4220313 # ITB inst accesses
-system.cpu0.itb.hits 4215172 # DTB hits
-system.cpu0.itb.misses 5141 # DTB misses
-system.cpu0.itb.accesses 4220313 # DTB accesses
-system.cpu0.numCycles 67779631 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 4225390 # ITB inst accesses
+system.cpu0.itb.hits 4220167 # DTB hits
+system.cpu0.itb.misses 5223 # DTB misses
+system.cpu0.itb.accesses 4225390 # DTB accesses
+system.cpu0.numCycles 67827032 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 11746060 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 31992288 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 5998436 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 3585033 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 7509031 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1449341 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 60597 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 20626968 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 4901 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 47542 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 85433 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 195 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 4213506 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 157466 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 2283 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 41121561 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.005038 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.385329 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 11757994 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 32012326 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 6001263 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 3587599 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 7516289 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1452567 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 61154 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 20647681 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 4894 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 47403 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 85456 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 4218433 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 158199 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 2369 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 41163993 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.004932 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.385225 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 33620027 81.76% 81.76% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 564307 1.37% 83.13% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 815894 1.98% 85.11% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 676094 1.64% 86.76% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 772709 1.88% 88.64% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 559273 1.36% 90.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 668674 1.63% 91.62% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 351557 0.85% 92.48% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 3093026 7.52% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 33655210 81.76% 81.76% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 565659 1.37% 83.13% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 816805 1.98% 85.12% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 675504 1.64% 86.76% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 773580 1.88% 88.64% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 559421 1.36% 90.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 670235 1.63% 91.62% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 352235 0.86% 92.48% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 3095344 7.52% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 41121561 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.088499 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.472004 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 12250531 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 20568387 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 6812697 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 512769 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 977177 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 933938 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 64793 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 39972827 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 213127 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 977177 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 12817507 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 5739937 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 12718334 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 6708425 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 2160181 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 38878118 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 1834 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 434730 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1233458 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 20 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 39234243 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 175587138 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 175552572 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 34566 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 30916046 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 8318196 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 410984 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 370136 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 5348015 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 7641998 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5680264 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1129998 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1207028 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 36802265 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 895658 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 37215076 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 80061 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 6274404 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 13150521 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 257091 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 41121561 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.905002 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.512830 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 41163993 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.088479 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.471970 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 12263422 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 20589298 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 6819290 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 512710 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 979273 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 935723 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 64727 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 40009195 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 212284 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 979273 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 12830808 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 5739819 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 12737837 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 6714966 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 2161290 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 38908996 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 1807 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 435519 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1234283 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 39260907 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 175730932 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 175696732 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 34200 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 30930361 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 8330545 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 411120 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 370260 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 5349265 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 7648868 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5685535 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1126587 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1232322 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 36830553 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 895643 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 37237747 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 80326 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 6284476 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 13189556 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 256860 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 41163993 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.904619 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.512118 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 25997548 63.22% 63.22% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 5725018 13.92% 77.14% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 3161670 7.69% 84.83% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2471559 6.01% 90.84% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2093564 5.09% 95.93% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 947248 2.30% 98.24% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 486513 1.18% 99.42% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 185061 0.45% 99.87% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 53380 0.13% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 26023978 63.22% 63.22% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 5734172 13.93% 77.15% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3165060 7.69% 84.84% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2475453 6.01% 90.85% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2094791 5.09% 95.94% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 945417 2.30% 98.24% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 488035 1.19% 99.42% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 184059 0.45% 99.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 53028 0.13% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 41121561 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 41163993 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 25811 2.41% 2.41% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 454 0.04% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 841861 78.66% 81.12% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 202059 18.88% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 25953 2.43% 2.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 456 0.04% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 841491 78.81% 81.29% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 199811 18.71% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 22315653 59.96% 60.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 46928 0.13% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 22327853 59.96% 60.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 46961 0.13% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 9358800 25.15% 85.38% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5440823 14.62% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 9364731 25.15% 85.38% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5445265 14.62% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 37215076 # Type of FU issued
-system.cpu0.iq.rate 0.549060 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 1070185 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.028757 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 116727564 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 43980171 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 34315180 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 8451 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 4750 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 3900 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 38228693 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 4419 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 306291 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 37237747 # Type of FU issued
+system.cpu0.iq.rate 0.549010 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 1067711 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.028673 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 116813355 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 44018555 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 34334136 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 8379 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 3876 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 38248858 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 4386 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 306561 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1370106 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2445 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 13123 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 533688 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1372448 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2379 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 13100 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 535058 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 2192694 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 5412 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 2192712 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 5628 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 977177 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 4122288 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 97984 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 37816345 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 85218 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 7641998 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5680264 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 571541 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 39816 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 2781 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 13123 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 149547 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 116915 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 266462 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 36841770 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 9218382 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 373306 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 979273 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 4122692 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 98715 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 37844885 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 85302 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 7648868 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 5685535 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 571530 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 40279 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 2826 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 13100 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 150418 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 117037 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 267455 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 36861439 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 9223512 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 376308 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 118422 # number of nop insts executed
-system.cpu0.iew.exec_refs 14612857 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 4852888 # Number of branches executed
-system.cpu0.iew.exec_stores 5394475 # Number of stores executed
-system.cpu0.iew.exec_rate 0.543552 # Inst execution rate
-system.cpu0.iew.wb_sent 36648414 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 34319080 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 18273947 # num instructions producing a value
-system.cpu0.iew.wb_consumers 35157700 # num instructions consuming a value
+system.cpu0.iew.exec_nop 118689 # number of nop insts executed
+system.cpu0.iew.exec_refs 14621351 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 4854206 # Number of branches executed
+system.cpu0.iew.exec_stores 5397839 # Number of stores executed
+system.cpu0.iew.exec_rate 0.543462 # Inst execution rate
+system.cpu0.iew.wb_sent 36666981 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 34338012 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 18281082 # num instructions producing a value
+system.cpu0.iew.wb_consumers 35173096 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.506333 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.519771 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.506259 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.519746 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 6086541 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 638567 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 230552 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 40144384 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.778927 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.740713 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6098128 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 638783 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 231564 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 40184720 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.778562 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.740417 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 28480985 70.95% 70.95% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 5711149 14.23% 85.17% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 1913332 4.77% 89.94% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 974787 2.43% 92.37% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 784907 1.96% 94.32% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 524754 1.31% 95.63% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 386537 0.96% 96.59% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 218696 0.54% 97.14% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1149237 2.86% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 28508400 70.94% 70.94% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 5724488 14.25% 85.19% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 1913763 4.76% 89.95% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 974414 2.42% 92.38% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 785086 1.95% 94.33% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 523080 1.30% 95.63% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 385100 0.96% 96.59% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 218421 0.54% 97.13% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1151968 2.87% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 40144384 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 23670531 # Number of instructions committed
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system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu0.committedOps 31188820 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 23589789 # Number of Instructions Simulated
-system.cpu0.cpi 2.873261 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.873261 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.348037 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.348037 # IPC: Total IPC of All Threads
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+system.cpu0.cpi_total 2.874148 # CPI: Total CPI of All Threads
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system.cpu0.fp_regfile_writes 900 # number of floating regfile writes
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+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13687.941416 # average overall miss latency
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system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31532500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6416479991 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 6416479991 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6416479991 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 6416479991 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514893000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514893000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180267878 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180267878 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695160878 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695160878 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030518 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030518 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027487 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027487 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056132 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056132 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051629 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051629 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029201 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.029201 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029201 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.029201 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12621.537710 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12621.537710 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30973.722492 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30973.722492 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7978.383911 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7978.383911 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4225.743768 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4225.743768 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20126.912999 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20126.912999 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20126.912999 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20126.912999 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 9086614 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 7469023 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 411441 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 6087298 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 5252816 # Number of BTB hits
+system.cpu1.branchPred.lookups 9071093 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 7457126 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 408382 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 6063336 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 5242542 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 86.291422 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 771111 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 43004 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 86.462997 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 772870 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 42976 # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 42908069 # DTB read hits
-system.cpu1.dtb.read_misses 37093 # DTB read misses
-system.cpu1.dtb.write_hits 6828111 # DTB write hits
-system.cpu1.dtb.write_misses 10566 # DTB write misses
+system.cpu1.dtb.read_hits 42899284 # DTB read hits
+system.cpu1.dtb.read_misses 36667 # DTB read misses
+system.cpu1.dtb.write_hits 6823776 # DTB write hits
+system.cpu1.dtb.write_misses 10740 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2002 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 2479 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 308 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 2487 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 658 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 42945162 # DTB read accesses
-system.cpu1.dtb.write_accesses 6838677 # DTB write accesses
+system.cpu1.dtb.perms_faults 676 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 42935951 # DTB read accesses
+system.cpu1.dtb.write_accesses 6834516 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 49736180 # DTB hits
-system.cpu1.dtb.misses 47659 # DTB misses
-system.cpu1.dtb.accesses 49783839 # DTB accesses
-system.cpu1.itb.inst_hits 8400139 # ITB inst hits
-system.cpu1.itb.inst_misses 5511 # ITB inst misses
+system.cpu1.dtb.hits 49723060 # DTB hits
+system.cpu1.dtb.misses 47407 # DTB misses
+system.cpu1.dtb.accesses 49770467 # DTB accesses
+system.cpu1.itb.inst_hits 8396614 # ITB inst hits
+system.cpu1.itb.inst_misses 5496 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1535 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1516 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1557 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 8405650 # ITB inst accesses
-system.cpu1.itb.hits 8400139 # DTB hits
-system.cpu1.itb.misses 5511 # DTB misses
-system.cpu1.itb.accesses 8405650 # DTB accesses
-system.cpu1.numCycles 408778710 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 8402110 # ITB inst accesses
+system.cpu1.itb.hits 8396614 # DTB hits
+system.cpu1.itb.misses 5496 # DTB misses
+system.cpu1.itb.accesses 8402110 # DTB accesses
+system.cpu1.numCycles 408759365 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 19802343 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 66108771 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 9086614 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 6023927 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 14149480 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 3968467 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 63429 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 77260462 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 4652 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 42943 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 130023 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 107 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 8398224 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 741385 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 2977 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 114156752 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.701240 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.046062 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 19792479 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 66053661 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 9071093 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 6015412 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 14141488 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3960570 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 63871 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 77254295 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 4578 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 41467 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 129632 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 8394649 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 740550 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 3020 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 114126730 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.700802 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.045190 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 100014473 87.61% 87.61% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 796994 0.70% 88.31% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 939704 0.82% 89.13% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 1889255 1.65% 90.79% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1506031 1.32% 92.11% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 574931 0.50% 92.61% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 2131854 1.87% 94.48% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 410857 0.36% 94.84% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 5892653 5.16% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 99992423 87.62% 87.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 796833 0.70% 88.31% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 937270 0.82% 89.13% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 1888150 1.65% 90.79% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1516879 1.33% 92.12% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 570874 0.50% 92.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 2130694 1.87% 94.49% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 410492 0.36% 94.85% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 5883115 5.15% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 114156752 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.022229 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.161723 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 21320888 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 76914540 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 12790943 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 524179 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 2606202 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1106995 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 98605 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 75226388 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 330391 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 2606202 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 22704982 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 31945118 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 40735326 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 11835422 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 4329702 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 69763643 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 18779 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 668299 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 3087296 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 338 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 73772994 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 321197839 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 321138769 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 59070 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 49056932 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 24716062 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 445445 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 388435 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 7877150 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 13206045 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 8148691 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 1035919 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1598177 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 63545873 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1154873 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 89160933 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 94911 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 16250476 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 45782181 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 274059 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 114156752 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.781040 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.519067 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 114126730 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.022192 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.161595 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 21309229 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 76907002 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 12785223 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 523232 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2602044 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1105609 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 98242 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 75190345 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 327184 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 2602044 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 22692364 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 31945147 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 40728563 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 11830258 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 4328354 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 69732759 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 18777 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 668377 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 3086520 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents 411 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 73724172 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 321062566 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 321003544 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 59022 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 49048322 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 24675850 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 444626 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 387642 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 7869295 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 13203135 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 8142815 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 1033166 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1534389 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 63494746 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1157882 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 89124827 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 94932 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 16221194 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 45699544 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 277241 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 114126730 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.780929 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.519205 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 83738528 73.35% 73.35% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 8425243 7.38% 80.73% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 4289902 3.76% 84.49% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 3781770 3.31% 87.81% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 10587758 9.27% 97.08% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1962324 1.72% 98.80% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 1024618 0.90% 99.70% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 272656 0.24% 99.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 73953 0.06% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 83735089 73.37% 73.37% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 8399712 7.36% 80.73% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 4300489 3.77% 84.50% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 3770900 3.30% 87.80% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 10582685 9.27% 97.08% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1966579 1.72% 98.80% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 1024954 0.90% 99.70% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 272498 0.24% 99.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 73824 0.06% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 114156752 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 114126730 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 29608 0.38% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 998 0.01% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 29743 0.38% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 996 0.01% 0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 7547947 95.93% 96.32% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 289296 3.68% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 7545200 95.88% 96.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 293621 3.73% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 37637940 42.21% 42.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 59271 0.07% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 43972305 49.32% 91.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 7175883 8.05% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 37614506 42.20% 42.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 59141 0.07% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 43964242 49.33% 91.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 7171411 8.05% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 89160933 # Type of FU issued
-system.cpu1.iq.rate 0.218115 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 7867849 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.088243 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 300473883 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 80959646 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 53671142 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 14975 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 8034 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 6858 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 96706888 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 7897 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 342362 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 89124827 # Type of FU issued
+system.cpu1.iq.rate 0.218037 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 7869560 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.088298 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 300373215 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 80882348 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 53634324 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 14862 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 8064 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 6807 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 96672574 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 7816 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 343282 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 3450901 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 3895 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 17010 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1308558 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 3450539 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 3807 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 17140 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1304937 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 31911884 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 888923 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 31906056 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 888018 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 2606202 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 24177339 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 360038 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 64805263 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 113338 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 13206045 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 8148691 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 865764 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 64951 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 3491 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 17010 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 203575 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 156879 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 360454 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 86736990 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 43278008 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 2423943 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 2602044 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 24184461 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 360387 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 64757250 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 110652 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 13203135 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 8142815 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 869312 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 65433 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 3547 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 17140 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 201642 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 155418 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 357060 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 86694604 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 43269055 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 2430223 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 104517 # number of nop insts executed
-system.cpu1.iew.exec_refs 50391999 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 7007502 # Number of branches executed
-system.cpu1.iew.exec_stores 7113991 # Number of stores executed
-system.cpu1.iew.exec_rate 0.212186 # Inst execution rate
-system.cpu1.iew.wb_sent 85759457 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 53678000 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 29917161 # num instructions producing a value
-system.cpu1.iew.wb_consumers 53364078 # num instructions consuming a value
+system.cpu1.iew.exec_nop 104622 # number of nop insts executed
+system.cpu1.iew.exec_refs 50378581 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 7000416 # Number of branches executed
+system.cpu1.iew.exec_stores 7109526 # Number of stores executed
+system.cpu1.iew.exec_rate 0.212092 # Inst execution rate
+system.cpu1.iew.wb_sent 85717179 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 53641131 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 29911901 # num instructions producing a value
+system.cpu1.iew.wb_consumers 53368558 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.131313 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.560624 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.131229 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.560478 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 16174786 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 880814 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 314330 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 111550550 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.431692 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.400024 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 16124623 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 880641 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 311654 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 111524686 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.431704 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.400261 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 94808427 84.99% 84.99% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 8234297 7.38% 92.37% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 2114478 1.90% 94.27% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1250833 1.12% 95.39% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1245005 1.12% 96.51% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 571421 0.51% 97.02% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 1000699 0.90% 97.92% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 504697 0.45% 98.37% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1820693 1.63% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 94788278 84.99% 84.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 8230770 7.38% 92.37% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 2113389 1.89% 94.27% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1254382 1.12% 95.39% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1243785 1.12% 96.51% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 567669 0.51% 97.02% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 997860 0.89% 97.91% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 504120 0.45% 98.36% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1824433 1.64% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 111550550 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 38064892 # Number of instructions committed
-system.cpu1.commit.committedOps 48155494 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 111524686 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 38058920 # Number of instructions committed
+system.cpu1.commit.committedOps 48145643 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 16595277 # Number of memory references committed
-system.cpu1.commit.loads 9755144 # Number of loads committed
-system.cpu1.commit.membars 190149 # Number of memory barriers committed
-system.cpu1.commit.branches 5967637 # Number of branches committed
-system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 42690457 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 534638 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 1820693 # number cycles where commit BW limit reached
+system.cpu1.commit.refs 16590474 # Number of memory references committed
+system.cpu1.commit.loads 9752596 # Number of loads committed
+system.cpu1.commit.membars 190088 # Number of memory barriers committed
+system.cpu1.commit.branches 5966646 # Number of branches committed
+system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 42681359 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 534484 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 1824433 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 173015978 # The number of ROB reads
-system.cpu1.rob.rob_writes 131360292 # The number of ROB writes
-system.cpu1.timesIdled 1408221 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 294621958 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 1796461003 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 37995253 # Number of Instructions Simulated
-system.cpu1.committedOps 48085855 # Number of Ops (including micro ops) Simulated
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-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125444 # miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15290.207815 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39479.123795 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 39479.123795 # average WriteReq miss latency
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-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5072.248894 # average StoreCondReq miss latency
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+system.cpu1.dcache.avg_refs 35.123770 # Average number of references to valid blocks.
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system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu1.dcache.writebacks::total 324651 # number of writebacks
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+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35691030962 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35691030962 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204681014962 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204681014962 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026197 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026197 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028354 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028354 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112139 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112139 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100501 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100501 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.027050 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.027050 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.448906 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.448906 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31783.458064 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31783.458064 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7032.024628 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7032.024628 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3082.169811 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3082.169811 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20501.520528 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20501.520528 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20501.520528 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20501.520528 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540120016505 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 540120016505 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540120016505 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 540120016505 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540140520228 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 540140520228 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540140520228 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 540140520228 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 41707 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 41725 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 48866 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 48857 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.533148 # Number of seconds simulated
-sim_ticks 2533147650000 # Number of ticks simulated
-final_tick 2533147650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.533144 # Number of seconds simulated
+sim_ticks 2533143504000 # Number of ticks simulated
+final_tick 2533143504000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 66149 # Simulator instruction rate (inst/s)
-host_op_rate 85115 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2778505291 # Simulator tick rate (ticks/s)
-host_mem_usage 406592 # Number of bytes of host memory used
-host_seconds 911.69 # Real time elapsed on the host
-sim_insts 60307315 # Number of instructions simulated
-sim_ops 77598799 # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 80573 # Simulator instruction rate (inst/s)
+host_op_rate 103675 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3384348477 # Simulator tick rate (ticks/s)
+host_mem_usage 408856 # Number of bytes of host memory used
+host_seconds 748.49 # Real time elapsed on the host
+sim_insts 60307579 # Number of instructions simulated
+sim_ops 77599125 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 795840 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9093648 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129429904 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 795840 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 795840 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3782016 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 796736 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9093520 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129430672 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 796736 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 796736 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3782592 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6798088 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6798664 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12435 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142122 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096808 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59094 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12449 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142120 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096820 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59103 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813112 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47189379 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813121 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47189456 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 314170 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3589861 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51094497 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 314170 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314170 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1493010 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1190642 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2683652 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1493010 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47189379 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 314525 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3589816 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51094883 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 314525 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 314525 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1493240 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1190644 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2683884 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1493240 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47189456 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314170 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4780503 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53778149 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15096808 # Total number of read requests seen
-system.physmem.writeReqs 813112 # Total number of write requests seen
-system.physmem.cpureqs 218335 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 966195712 # Total number of bytes read from memory
-system.physmem.bytesWritten 52039168 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 129429904 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6798088 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 295 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4677 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 943938 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 943447 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 943391 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 943143 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 943273 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 943781 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 943299 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 943231 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 943694 # Track reads on a per bank basis
+system.physmem.bw_total::cpu.inst 314525 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4780460 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53778768 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096820 # Total number of read requests seen
+system.physmem.writeReqs 813121 # Total number of write requests seen
+system.physmem.cpureqs 218357 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 966196480 # Total number of bytes read from memory
+system.physmem.bytesWritten 52039744 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 129430672 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6798664 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 227 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4678 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 943951 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 943388 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 944196 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 943983 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 943145 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 943274 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 943869 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 943805 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 943304 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 943207 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 943616 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 943708 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 943087 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 942964 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 943610 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50827 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50416 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50443 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51149 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 50907 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::14 942997 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 943623 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50838 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50409 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 50910 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 50180 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50280 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51358 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51187 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51246 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 50619 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51228 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 50279 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51367 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 50902 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 50800 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51241 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 50709 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 50623 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 2236976 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2533146526000 # Total gap between requests
+system.physmem.numWrRetry 2238337 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2533142364000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 36 # Categorize read packet sizes
system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154564 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 2990994 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 59094 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 4677 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1039969 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 980923 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 950073 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3550359 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2676584 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2688258 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2649649 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 60661 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 59173 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 108720 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 157659 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 108272 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 16731 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 21899 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 10876 # What read queue length does an incoming req see
+system.physmem.readPktSize::6 154576 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 754018 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 59103 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 1040115 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 981189 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 950309 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 3550321 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2676376 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2687982 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2649582 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 60790 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 59171 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 108701 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 157630 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 108239 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 16713 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 16586 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 21915 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2580 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 2633 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 2680 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 2721 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 2742 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 2771 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 2796 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 2817 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::2 2677 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 2715 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 2739 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 2769 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 2793 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32773 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 32720 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 32673 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::27 32614 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::29 32560 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 393223278963 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 485615648963 # Sum of mem lat for all requests
-system.physmem.totBusLat 75482565000 # Total cycles spent in databus access
-system.physmem.totBankLat 16909805000 # Total cycles spent in bank access
-system.physmem.avgQLat 26047.29 # Average queueing delay per request
-system.physmem.avgBankLat 1120.11 # Average bank access latency per request
+system.physmem.totQLat 393245939250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 485641693000 # Sum of mem lat for all requests
+system.physmem.totBusLat 75482965000 # Total cycles spent in databus access
+system.physmem.totBankLat 16912788750 # Total cycles spent in bank access
+system.physmem.avgQLat 26048.65 # Average queueing delay per request
+system.physmem.avgBankLat 1120.31 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 32167.41 # Average memory access latency
+system.physmem.avgMemAccLat 32168.96 # Average memory access latency
system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.14 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.19 # Average read queue length over time
-system.physmem.avgWrQLen 11.48 # Average write queue length over time
-system.physmem.readRowHits 15020221 # Number of row buffer hits during reads
-system.physmem.writeRowHits 793131 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 9.55 # Average write queue length over time
+system.physmem.readRowHits 15020273 # Number of row buffer hits during reads
+system.physmem.writeRowHits 793117 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes
-system.physmem.avgGap 159218.06 # Average gap between requests
+system.physmem.avgGap 159217.58 # Average gap between requests
+system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 14676489 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11762878 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 704619 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9800840 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7950249 # Number of BTB hits
+system.cpu.branchPred.lookups 14678084 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11764424 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 705314 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9806272 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7951789 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 81.118037 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1398960 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 72172 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 81.088807 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1399019 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72620 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51394402 # DTB read hits
-system.cpu.dtb.read_misses 64202 # DTB read misses
-system.cpu.dtb.write_hits 11700782 # DTB write hits
-system.cpu.dtb.write_misses 15842 # DTB write misses
+system.cpu.dtb.read_hits 51401633 # DTB read hits
+system.cpu.dtb.read_misses 64365 # DTB read misses
+system.cpu.dtb.write_hits 11702282 # DTB write hits
+system.cpu.dtb.write_misses 15903 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 3565 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2475 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 3559 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2575 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 399 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1357 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51458604 # DTB read accesses
-system.cpu.dtb.write_accesses 11716624 # DTB write accesses
+system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51465998 # DTB read accesses
+system.cpu.dtb.write_accesses 11718185 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63095184 # DTB hits
-system.cpu.dtb.misses 80044 # DTB misses
-system.cpu.dtb.accesses 63175228 # DTB accesses
-system.cpu.itb.inst_hits 12330326 # ITB inst hits
-system.cpu.itb.inst_misses 11351 # ITB inst misses
+system.cpu.dtb.hits 63103915 # DTB hits
+system.cpu.dtb.misses 80268 # DTB misses
+system.cpu.dtb.accesses 63184183 # DTB accesses
+system.cpu.itb.inst_hits 12333169 # ITB inst hits
+system.cpu.itb.inst_misses 11311 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2478 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2477 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2994 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2979 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 12341677 # ITB inst accesses
-system.cpu.itb.hits 12330326 # DTB hits
-system.cpu.itb.misses 11351 # DTB misses
-system.cpu.itb.accesses 12341677 # DTB accesses
-system.cpu.numCycles 471833351 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 12344480 # ITB inst accesses
+system.cpu.itb.hits 12333169 # DTB hits
+system.cpu.itb.misses 11311 # DTB misses
+system.cpu.itb.accesses 12344480 # DTB accesses
+system.cpu.numCycles 471839315 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 30572359 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 96029601 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14676489 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9349209 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 21156129 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5298120 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 120373 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 95586316 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 87050 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 195749 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 271 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 12326631 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 900507 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5718 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 151357354 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.785025 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.150266 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 30570275 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 96049459 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14678084 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9350808 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 21162167 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5300670 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 119262 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 95593563 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2640 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 87521 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 195771 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 307 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 12329483 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 900673 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5698 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 151369698 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.785111 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.150333 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 130216652 86.03% 86.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1302204 0.86% 86.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1711626 1.13% 88.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2495193 1.65% 89.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2215033 1.46% 91.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1107976 0.73% 91.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2757688 1.82% 93.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 745754 0.49% 94.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8805228 5.82% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 130222829 86.03% 86.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1303268 0.86% 86.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1713149 1.13% 88.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2496945 1.65% 89.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2215858 1.46% 91.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1107759 0.73% 91.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2757122 1.82% 93.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 745476 0.49% 94.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8807292 5.82% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 151357354 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.031105 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.203524 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 32536934 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 95207461 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19182239 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 963280 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3467440 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1956290 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 171623 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 112620131 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 567256 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3467440 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 34479585 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36699027 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 52520178 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18147266 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6043858 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 106106757 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 20523 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1005521 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4063485 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 592 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 110532069 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 485468581 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 485377824 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 90757 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78389582 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 32142486 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 830463 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 737014 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12171984 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 20324763 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13518088 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1981188 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2478536 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 97936678 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1983499 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 124321529 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 167156 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 21750573 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 57066044 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 501117 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 151357354 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.821378 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.534899 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 151369698 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.031108 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.203564 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 32533087 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 95216874 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 19187667 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 962846 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3469224 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1957624 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 171486 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 112641564 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 566291 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3469224 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 34475717 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36705773 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 52523534 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 18152425 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6043025 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 106121315 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 20520 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1004083 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4063852 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 628 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 110544866 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 485535846 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 485445234 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 90612 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78389874 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 32154991 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 830680 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 737251 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12167564 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 20329502 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13519419 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1975005 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2483431 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 97943833 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1983956 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 124335595 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 167777 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 21753420 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 57059209 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 501571 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 151369698 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.821403 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.534931 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 107117235 70.77% 70.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13550856 8.95% 79.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7067177 4.67% 84.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5940673 3.92% 88.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12604400 8.33% 96.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2784028 1.84% 98.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1701066 1.12% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 465188 0.31% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 126731 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 107127102 70.77% 70.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13547292 8.95% 79.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7070046 4.67% 84.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5943115 3.93% 88.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12603566 8.33% 96.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2786171 1.84% 98.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1700250 1.12% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 465001 0.31% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 127155 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 151357354 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 151369698 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 61039 0.69% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 3 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 60916 0.69% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8364044 94.63% 95.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 413790 4.68% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8365801 94.64% 95.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 413031 4.67% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 58631158 47.16% 47.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 93232 0.07% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 58634354 47.16% 47.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 93273 0.08% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 18 0.00% 47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52911235 42.56% 90.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12320074 9.91% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52919784 42.56% 90.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12322346 9.91% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 124321529 # Type of FU issued
-system.cpu.iq.rate 0.263486 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8838876 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071097 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 409062941 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 121687155 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 85967434 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23205 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12488 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10289 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 132784424 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12315 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 622437 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 124335595 # Type of FU issued
+system.cpu.iq.rate 0.263513 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8839750 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071096 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 409105295 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 121697619 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 85975011 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23030 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12486 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10280 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 132799466 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12213 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 624029 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4670323 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6258 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30023 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1786078 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4674977 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6508 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 30066 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1787339 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107730 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 893047 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34107736 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 893802 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3467440 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 27945377 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 433355 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 100140842 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 200439 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 20324763 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13518088 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1411116 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 112674 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3579 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30023 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 350481 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 268612 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 619093 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 121545908 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52081707 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2775621 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3469224 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 27949054 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 432986 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 100148718 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 201036 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 20329502 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13519419 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1411238 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 112362 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3588 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 30066 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 350846 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 269150 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 619996 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 121555637 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 52088672 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2779958 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 220665 # number of nop insts executed
-system.cpu.iew.exec_refs 64294282 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11561887 # Number of branches executed
-system.cpu.iew.exec_stores 12212575 # Number of stores executed
-system.cpu.iew.exec_rate 0.257603 # Inst execution rate
-system.cpu.iew.wb_sent 120387103 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 85977723 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47219839 # num instructions producing a value
-system.cpu.iew.wb_consumers 88163371 # num instructions consuming a value
+system.cpu.iew.exec_nop 220929 # number of nop insts executed
+system.cpu.iew.exec_refs 64302587 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11562998 # Number of branches executed
+system.cpu.iew.exec_stores 12213915 # Number of stores executed
+system.cpu.iew.exec_rate 0.257621 # Inst execution rate
+system.cpu.iew.wb_sent 120394624 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 85985291 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47225460 # num instructions producing a value
+system.cpu.iew.wb_consumers 88174567 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.182221 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.535595 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.182234 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535590 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 21484846 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1482382 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 535483 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 147889914 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.525723 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.514974 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 21490031 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1482385 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 536346 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 147900474 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.525688 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.515007 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 120439692 81.44% 81.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13316642 9.00% 90.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3906186 2.64% 93.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2120970 1.43% 94.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1946250 1.32% 95.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 970441 0.66% 96.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1598227 1.08% 97.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 701359 0.47% 98.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2890147 1.95% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 120451739 81.44% 81.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13317188 9.00% 90.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3905098 2.64% 93.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2119368 1.43% 94.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1946193 1.32% 95.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 968094 0.65% 96.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1600636 1.08% 97.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 702304 0.47% 98.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2889854 1.95% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 147889914 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60457696 # Number of instructions committed
-system.cpu.commit.committedOps 77749180 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 147900474 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60457960 # Number of instructions committed
+system.cpu.commit.committedOps 77749506 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27386450 # Number of memory references committed
-system.cpu.commit.loads 15654440 # Number of loads committed
-system.cpu.commit.membars 403595 # Number of memory barriers committed
-system.cpu.commit.branches 9961299 # Number of branches committed
+system.cpu.commit.refs 27386605 # Number of memory references committed
+system.cpu.commit.loads 15654525 # Number of loads committed
+system.cpu.commit.membars 403599 # Number of memory barriers committed
+system.cpu.commit.branches 9961316 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 68854449 # Number of committed integer instructions.
-system.cpu.commit.function_calls 991256 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2890147 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 68854760 # Number of committed integer instructions.
+system.cpu.commit.function_calls 991257 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2889854 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 242385214 # The number of ROB reads
-system.cpu.rob.rob_writes 202032533 # The number of ROB writes
-system.cpu.timesIdled 1770643 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 320475997 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4594378908 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60307315 # Number of Instructions Simulated
-system.cpu.committedOps 77598799 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 60307315 # Number of Instructions Simulated
-system.cpu.cpi 7.823816 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.823816 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.127815 # IPC: Instructions Per Cycle
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system.cpu.dcache.warmup_cycle 42249000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy
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-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13263.546377 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13263.546377 # average ReadReq miss latency
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-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13336.257310 # average LoadLockedReq miss latency
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1229589046447 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1229589046447 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1229610747140 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1229610747140 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 83042 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 2.401342 # Number of seconds simulated
+sim_ticks 2401342466000 # Number of ticks simulated
+final_tick 2401342466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 244723 # Simulator instruction rate (inst/s)
+host_op_rate 314293 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9740625246 # Simulator tick rate (ticks/s)
+host_mem_usage 401684 # Number of bytes of host memory used
+host_seconds 246.53 # Real time elapsed on the host
+sim_insts 60331304 # Number of instructions simulated
+sim_ops 77482270 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 501920 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 7085968 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 85312 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 678144 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 640 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 178368 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 1313020 # Number of bytes read from this memory
+system.physmem.bytes_read::total 124662764 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 501920 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 85312 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 178368 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 765600 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3747328 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 1490908 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 199452 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2.data 1325456 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6763144 # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 14045 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 110752 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 1333 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 10596 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker 10 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 2787 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 20530 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 14512442 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 58552 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 372727 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 49863 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2.data 331364 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47814534 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 209016 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 2950836 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 35527 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 282402 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker 267 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 74278 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 546786 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51913780 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 209016 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 35527 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 74278 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 318822 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1560514 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 620864 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 83059 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2.data 551965 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2816401 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1560514 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47814534 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 209016 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 3571700 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 35527 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 365461 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker 267 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 74278 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 1098750 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 54730181 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 12618170 # Total number of read requests seen
+system.physmem.writeReqs 398699 # Total number of write requests seen
+system.physmem.cpureqs 55066 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 807562880 # Total number of bytes read from memory
+system.physmem.bytesWritten 25516736 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 102918908 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 2643116 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 2351 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 789127 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 788778 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 788875 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 789205 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 789031 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 788756 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 788906 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 788958 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 788649 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 788041 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 788042 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 788299 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 788288 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 788136 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 788329 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 788749 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 24964 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 24827 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 24766 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 25058 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 24835 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 24655 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 24742 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 25296 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 25174 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 24837 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 24777 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 24716 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 24968 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 24890 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 24969 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 25225 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 780903 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2400307249500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 15 # Categorize read packet sizes
+system.physmem.readPktSize::3 12582912 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 35243 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 381227 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 17472 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 816053 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 792099 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 797750 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 2998172 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2260822 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2261142 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2249570 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 49283 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 49193 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 91349 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 133522 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 91347 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 6979 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 6966 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 6962 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 6956 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2982 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 2988 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 2997 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 3017 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 3015 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 3012 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 3006 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 3005 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 3001 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 17344 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 17336 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 17332 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 17328 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 17322 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 17319 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 17313 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 17309 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 17306 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 17301 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 17299 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 17293 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 17291 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 17290 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 14407 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 14392 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 14382 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 14357 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 14355 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 14353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 14351 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 14349 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 14347 # What write queue length does an incoming req see
+system.physmem.totQLat 277225501500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 353051170250 # Sum of mem lat for all requests
+system.physmem.totBusLat 63090845000 # Total cycles spent in databus access
+system.physmem.totBankLat 12734823750 # Total cycles spent in bank access
+system.physmem.avgQLat 21970.34 # Average queueing delay per request
+system.physmem.avgBankLat 1009.24 # Average bank access latency per request
+system.physmem.avgBusLat 5000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 27979.59 # Average memory access latency
+system.physmem.avgRdBW 336.30 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 10.63 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 42.86 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 2.71 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.15 # Average read queue length over time
+system.physmem.avgWrQLen 0.39 # Average write queue length over time
+system.physmem.readRowHits 12563520 # Number of row buffer hits during reads
+system.physmem.writeRowHits 392353 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 98.41 # Row buffer hit rate for writes
+system.physmem.avgGap 184399.74 # Average gap between requests
+system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 63278 # number of replacements
+system.l2c.tagsinuse 50361.338948 # Cycle average of tags in use
+system.l2c.total_refs 1750374 # Total number of references to valid blocks.
+system.l2c.sampled_refs 128673 # Sample count of references to valid blocks.
+system.l2c.avg_refs 13.603273 # Average number of references to valid blocks.
+system.l2c.warmup_cycle 2374434052500 # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks 36832.479753 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 5142.503015 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 3774.307963 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 800.237683 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 747.699491 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.dtb.walker 9.796874 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.itb.walker 0.004225 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.inst 1464.578885 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.data 1588.737598 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.562019 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst 0.078468 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.057591 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst 0.012211 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data 0.011409 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.dtb.walker 0.000149 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.inst 0.022348 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.data 0.024242 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.768453 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker 9023 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker 3354 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst 461813 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 169129 # number of ReadReq hits
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+system.cpu0.icache.sampled_refs 892942 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 49.597539 # Average number of references to valid blocks.
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+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146204 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 146204 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 547277 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 547277 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 408 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 408 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data 693481 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 693481 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data 693481 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 693481 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65573 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 137360 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 202933 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29694 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53043 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 82737 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1721 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3467 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5188 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data 95267 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data 190403 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 285670 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data 95267 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data 190403 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 285670 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 782830500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1785427500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2568258000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 670558000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1431904990 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2102462990 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19087500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40642000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59729500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1453388500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3217332490 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 4670720990 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1453388500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3217332490 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 4670720990 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27581235500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28989086000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56570321500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1280021500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14116548125 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15396569625 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28861257000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43105634125 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71966891125 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033424 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028942 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014679 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021517 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019471 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008098 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047893 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.045147 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020732 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028507 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025488 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.011882 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028507 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025488 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.011882 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11938.305400 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12998.161765 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12655.694244 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22582.272513 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26995.173538 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25411.399857 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.935503 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11722.526680 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11513.010794 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15255.949069 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16897.488432 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16350.057724 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15255.949069 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16897.488432 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16350.057724 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dtb.inst_hits 0 # ITB inst hits
+system.cpu1.dtb.inst_misses 0 # ITB inst misses
+system.cpu1.dtb.read_hits 2177390 # DTB read hits
+system.cpu1.dtb.read_misses 2104 # DTB read misses
+system.cpu1.dtb.write_hits 1466734 # DTB write hits
+system.cpu1.dtb.write_misses 391 # DTB write misses
+system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 40 # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults 80 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 2179494 # DTB read accesses
+system.cpu1.dtb.write_accesses 1467125 # DTB write accesses
+system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dtb.hits 3644124 # DTB hits
+system.cpu1.dtb.misses 2495 # DTB misses
+system.cpu1.dtb.accesses 3646619 # DTB accesses
+system.cpu1.itb.inst_hits 8441472 # ITB inst hits
+system.cpu1.itb.inst_misses 1131 # ITB inst misses
+system.cpu1.itb.read_hits 0 # DTB read hits
+system.cpu1.itb.read_misses 0 # DTB read misses
+system.cpu1.itb.write_hits 0 # DTB write hits
+system.cpu1.itb.write_misses 0 # DTB write misses
+system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 829 # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses 0 # DTB read accesses
+system.cpu1.itb.write_accesses 0 # DTB write accesses
+system.cpu1.itb.inst_accesses 8442603 # ITB inst accesses
+system.cpu1.itb.hits 8441472 # DTB hits
+system.cpu1.itb.misses 1131 # DTB misses
+system.cpu1.itb.accesses 8442603 # DTB accesses
+system.cpu1.numCycles 574629535 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.committedInsts 8231527 # Number of instructions committed
+system.cpu1.committedOps 10483049 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 9384758 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 1998 # Number of float alu accesses
+system.cpu1.num_func_calls 317840 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 1148947 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 9384758 # number of integer instructions
+system.cpu1.num_fp_insts 1998 # number of float instructions
+system.cpu1.num_int_register_reads 54113079 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 10168310 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 1549 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written
+system.cpu1.num_mem_refs 3817736 # number of memory refs
+system.cpu1.num_load_insts 2273251 # Number of load instructions
+system.cpu1.num_store_insts 1544485 # Number of store instructions
+system.cpu1.num_idle_cycles 533738024.963358 # Number of idle cycles
+system.cpu1.num_busy_cycles 40891510.036642 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.071162 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.928838 # Percentage of idle cycles
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.cpu2.branchPred.lookups 4718167 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 3836083 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 222496 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 3137475 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 2530778 # Number of BTB hits
+system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu2.branchPred.BTBHitPct 80.662890 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 410861 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 21436 # Number of incorrect RAS predictions.
+system.cpu2.dtb.inst_hits 0 # ITB inst hits
+system.cpu2.dtb.inst_misses 0 # ITB inst misses
+system.cpu2.dtb.read_hits 10866526 # DTB read hits
+system.cpu2.dtb.read_misses 22717 # DTB read misses
+system.cpu2.dtb.write_hits 3271799 # DTB write hits
+system.cpu2.dtb.write_misses 5746 # DTB write misses
+system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed
+system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu2.dtb.flush_tlb_mva_asid 504 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID
+system.cpu2.dtb.flush_entries 2317 # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults 908 # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults 162 # Number of TLB faults due to prefetch
+system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu2.dtb.perms_faults 438 # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses 10889243 # DTB read accesses
+system.cpu2.dtb.write_accesses 3277545 # DTB write accesses
+system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu2.dtb.hits 14138325 # DTB hits
+system.cpu2.dtb.misses 28463 # DTB misses
+system.cpu2.dtb.accesses 14166788 # DTB accesses
+system.cpu2.itb.inst_hits 4062010 # ITB inst hits
+system.cpu2.itb.inst_misses 4544 # ITB inst misses
+system.cpu2.itb.read_hits 0 # DTB read hits
+system.cpu2.itb.read_misses 0 # DTB read misses
+system.cpu2.itb.write_hits 0 # DTB write hits
+system.cpu2.itb.write_misses 0 # DTB write misses
+system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu2.itb.flush_tlb_mva_asid 504 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID
+system.cpu2.itb.flush_entries 1576 # Number of entries that have been flushed from TLB
+system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu2.itb.perms_faults 990 # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.read_accesses 0 # DTB read accesses
+system.cpu2.itb.write_accesses 0 # DTB write accesses
+system.cpu2.itb.inst_accesses 4066554 # ITB inst accesses
+system.cpu2.itb.hits 4062010 # DTB hits
+system.cpu2.itb.misses 4544 # DTB misses
+system.cpu2.itb.accesses 4066554 # DTB accesses
+system.cpu2.numCycles 88259424 # number of cpu cycles simulated
+system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu2.fetch.icacheStallCycles 9446644 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 32376030 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 4718167 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 2941639 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 6823560 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 1815993 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles 51150 # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.BlockedCycles 19328654 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles 814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 980 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 33196 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 57154 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 380 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 4060600 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 310025 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes 2087 # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples 36989038 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.050362 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.436921 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 30170666 81.57% 81.57% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 382975 1.04% 82.60% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 509806 1.38% 83.98% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 812610 2.20% 86.18% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 650446 1.76% 87.94% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 344174 0.93% 88.87% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 1009971 2.73% 91.60% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 238143 0.64% 92.24% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 2870247 7.76% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::total 36989038 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.053458 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 0.366828 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 10060365 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 19264823 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 6175765 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 293250 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 1193736 # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved 611236 # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred 54016 # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts 36687044 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 183513 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 1193736 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 10634106 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 6560148 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 11167231 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 5875066 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 1557700 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 34442910 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 2428 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 416233 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents 878364 # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.FullRegisterEvents 86 # Number of times there has been no free registers
+system.cpu2.rename.RenamedOperands 36942900 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 157448988 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 157420907 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 28081 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 25732227 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 11210672 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 231165 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 207502 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 3338949 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 6517311 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 3844285 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 533485 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 782358 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 31699556 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 512260 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 34239526 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 54408 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 7411685 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 19905699 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 155950 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 36989038 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 0.925667 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.579936 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 24424083 66.03% 66.03% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 3914413 10.58% 76.61% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 2344925 6.34% 82.95% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 1979398 5.35% 88.30% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 2782245 7.52% 95.83% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 897303 2.43% 98.25% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 479565 1.30% 99.55% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 132664 0.36% 99.91% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 34442 0.09% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 36989038 # Number of insts issued each cycle
+system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 16741 1.09% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 1406719 91.75% 92.84% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 109821 7.16% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu2.iq.FU_type_0::No_OpClass 61341 0.18% 0.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 19346638 56.50% 56.68% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 25970 0.08% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 8 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 382 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 11366450 33.20% 89.96% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 3438720 10.04% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::total 34239526 # Type of FU issued
+system.cpu2.iq.rate 0.387942 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 1533281 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.044781 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 107077115 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 39628603 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 27373114 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 7012 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 3867 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 3171 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 35707743 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 3723 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 207144 # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu2.iew.lsq.thread0.squashedLoads 1578939 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 1781 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 9287 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 581487 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu2.iew.lsq.thread0.rescheduledLoads 5366547 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 352710 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu2.iew.iewSquashCycles 1193736 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 4865575 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 91265 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 32289220 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 60072 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 6517311 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 3844285 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 370110 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 31382 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 2364 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 9287 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 105801 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 88656 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 194457 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 33253955 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 11078248 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 985571 # Number of squashed instructions skipped in execute
+system.cpu2.iew.exec_swp 0 # number of swp insts executed
+system.cpu2.iew.exec_nop 77404 # number of nop insts executed
+system.cpu2.iew.exec_refs 14484069 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 3693959 # Number of branches executed
+system.cpu2.iew.exec_stores 3405821 # Number of stores executed
+system.cpu2.iew.exec_rate 0.376775 # Inst execution rate
+system.cpu2.iew.wb_sent 32835376 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 27376285 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 15639881 # num instructions producing a value
+system.cpu2.iew.wb_consumers 28443914 # num instructions consuming a value
+system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu2.iew.wb_rate 0.310180 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.549850 # average fanout of values written-back
+system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu2.commit.commitSquashedInsts 7353370 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 356310 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 169242 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 35795177 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 0.689030 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.716377 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 27161144 75.88% 75.88% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 4182796 11.69% 87.56% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1257934 3.51% 91.08% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 650072 1.82% 92.90% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 572405 1.60% 94.49% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 318145 0.89% 95.38% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 398611 1.11% 96.50% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 289517 0.81% 97.31% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 964553 2.69% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::total 35795177 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 19948032 # Number of instructions committed
+system.cpu2.commit.committedOps 24663934 # Number of ops (including micro ops) committed
+system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu2.commit.refs 8201170 # Number of memory references committed
+system.cpu2.commit.loads 4938372 # Number of loads committed
+system.cpu2.commit.membars 94284 # Number of memory barriers committed
+system.cpu2.commit.branches 3159330 # Number of branches committed
+system.cpu2.commit.fp_insts 3119 # Number of committed floating point instructions.
+system.cpu2.commit.int_insts 21896584 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 294432 # Number of function calls committed.
+system.cpu2.commit.bw_lim_events 964553 # number cycles where commit BW limit reached
+system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu2.rob.rob_reads 66322359 # The number of ROB reads
+system.cpu2.rob.rob_writes 65269716 # The number of ROB writes
+system.cpu2.timesIdled 360610 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 51270386 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 3567282777 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 19896304 # Number of Instructions Simulated
+system.cpu2.committedOps 24612206 # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total 19896304 # Number of Instructions Simulated
+system.cpu2.cpi 4.435971 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 4.435971 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.225430 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.225430 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 153619479 # number of integer regfile reads
+system.cpu2.int_regfile_writes 29201382 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 22411 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 20842 # number of floating regfile writes
+system.cpu2.misc_regfile_reads 9012056 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 240747 # number of misc regfile writes
+system.iocache.replacements 0 # number of replacements
+system.iocache.tagsinuse 0 # Cycle average of tags in use
+system.iocache.total_refs 0 # Total number of references to valid blocks.
+system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
+system.iocache.avg_refs nan # Average number of references to valid blocks.
+system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981147786186 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 981147786186 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981147786186 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 981147786186 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu2.kern.inst.arm 0 # number of arm instructions executed
+system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
+
+---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.542296 # Number of seconds simulated
-sim_ticks 2542295570500 # Number of ticks simulated
-final_tick 2542295570500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.541289 # Number of seconds simulated
+sim_ticks 2541288973500 # Number of ticks simulated
+final_tick 2541288973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 70655 # Simulator instruction rate (inst/s)
-host_op_rate 90914 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2978397497 # Simulator tick rate (ticks/s)
-host_mem_usage 409668 # Number of bytes of host memory used
-host_seconds 853.58 # Real time elapsed on the host
-sim_insts 60309877 # Number of instructions simulated
-sim_ops 77602149 # Number of ops (including micro ops) simulated
+host_inst_rate 61532 # Simulator instruction rate (inst/s)
+host_op_rate 79175 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2592785663 # Simulator tick rate (ticks/s)
+host_mem_usage 411940 # Number of bytes of host memory used
+host_seconds 980.14 # Real time elapsed on the host
+sim_insts 60309889 # Number of instructions simulated
+sim_ops 77602313 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 1280 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 504448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4169680 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 296128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4925148 # Number of bytes read from this memory
-system.physmem.bytes_read::total 131008300 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 504448 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 296128 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3787072 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1346312 # Number of bytes written to this memory
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system.physmem.perBankWrReqs::15 51233 # Track writes on a per bank basis
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 43 # Categorize read packet sizes
system.physmem.readPktSize::3 15138816 # Categorize read packet sizes
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+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40212.673043 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37786.741539 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 39283.448356 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40212.673043 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37786.741539 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 39283.448356 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 7620138 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 6076880 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 380507 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 4965064 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 4053585 # Number of BTB hits
+system.cpu0.branchPred.lookups 7614306 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 6072650 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 380012 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 4955572 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 4051897 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 81.642150 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 731859 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 39538 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 81.764466 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 730604 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 39458 # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 26058653 # DTB read hits
-system.cpu0.dtb.read_misses 40101 # DTB read misses
-system.cpu0.dtb.write_hits 5895373 # DTB write hits
-system.cpu0.dtb.write_misses 9447 # DTB write misses
+system.cpu0.dtb.read_hits 26054511 # DTB read hits
+system.cpu0.dtb.read_misses 40169 # DTB read misses
+system.cpu0.dtb.write_hits 5887052 # DTB write hits
+system.cpu0.dtb.write_misses 9355 # DTB write misses
system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 5619 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1431 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 273 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 5627 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1395 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 274 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 647 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 26098754 # DTB read accesses
-system.cpu0.dtb.write_accesses 5904820 # DTB write accesses
+system.cpu0.dtb.perms_faults 638 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 26094680 # DTB read accesses
+system.cpu0.dtb.write_accesses 5896407 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 31954026 # DTB hits
-system.cpu0.dtb.misses 49548 # DTB misses
-system.cpu0.dtb.accesses 32003574 # DTB accesses
-system.cpu0.itb.inst_hits 6112115 # ITB inst hits
-system.cpu0.itb.inst_misses 7637 # ITB inst misses
+system.cpu0.dtb.hits 31941563 # DTB hits
+system.cpu0.dtb.misses 49524 # DTB misses
+system.cpu0.dtb.accesses 31991087 # DTB accesses
+system.cpu0.itb.inst_hits 6108612 # ITB inst hits
+system.cpu0.itb.inst_misses 7590 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2623 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1579 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1574 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 6119752 # ITB inst accesses
-system.cpu0.itb.hits 6112115 # DTB hits
-system.cpu0.itb.misses 7637 # DTB misses
-system.cpu0.itb.accesses 6119752 # DTB accesses
-system.cpu0.numCycles 239063312 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 6116202 # ITB inst accesses
+system.cpu0.itb.hits 6108612 # DTB hits
+system.cpu0.itb.misses 7590 # DTB misses
+system.cpu0.itb.accesses 6116202 # DTB accesses
+system.cpu0.numCycles 239083473 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 15490963 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 47835555 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 7620138 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 4785444 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 10608217 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 2561094 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 89115 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 49527666 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 1654 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles 1892 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles 49952 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 101088 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 226 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 6110008 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 396628 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 3581 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 77642580 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.762278 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.119818 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 15485568 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 47808985 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 7614306 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 4782501 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 10601732 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 2558486 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 88790 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 49524477 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 1650 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles 2036 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles 49879 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 101149 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 238 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 6106475 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 397023 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 3536 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 77625046 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.761902 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.119269 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 67041875 86.35% 86.35% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 689016 0.89% 87.23% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 885560 1.14% 88.37% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 1228014 1.58% 89.96% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 1141359 1.47% 91.43% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 577108 0.74% 92.17% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 1324549 1.71% 93.88% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 398041 0.51% 94.39% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4357058 5.61% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 67030834 86.35% 86.35% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 688188 0.89% 87.24% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 885369 1.14% 88.38% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 1227712 1.58% 89.96% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 1142460 1.47% 91.43% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 576598 0.74% 92.18% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 1323002 1.70% 93.88% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 397300 0.51% 94.39% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4353583 5.61% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 77642580 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.031875 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.200096 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 16540886 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 49255967 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 9607571 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 552371 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1683667 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 1024811 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 90579 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 56316085 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 302289 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1683667 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 17475063 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 18984775 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 27019953 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 9154130 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 3322955 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 53494037 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 13484 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 621738 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 2157353 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 548 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 55660367 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 243519467 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 243471355 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 48112 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 40417937 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 15242430 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 429833 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 381699 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 6758508 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 10355148 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 6782314 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1058612 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1316675 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 49644359 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1043369 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 63195717 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 96260 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 10515144 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 26542188 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 266673 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 77642580 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.813931 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.519230 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 77625046 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.031848 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.199968 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 16533020 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 49254882 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 9604301 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 549145 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1681530 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 1023916 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 90477 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 56278023 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 301850 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1681530 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 17466172 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 18987810 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 27019642 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 9149380 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 3318436 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 53462165 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 13485 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 622165 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 2153440 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents 547 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 55626962 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 243359254 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 243311426 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 47828 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 40393377 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 15233585 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 429285 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 381212 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 6745205 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 10341737 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 6773194 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1063883 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1311451 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 49606690 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1043899 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 63171257 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 95885 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 10502922 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 26495317 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 267486 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 77625046 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.813800 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.519198 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 54792876 70.57% 70.57% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 7218069 9.30% 79.87% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 3694351 4.76% 84.63% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 3145323 4.05% 88.68% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 6277418 8.09% 96.76% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1407401 1.81% 98.57% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 809465 1.04% 99.62% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 231906 0.30% 99.92% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 65771 0.08% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 54791410 70.58% 70.58% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 7205110 9.28% 79.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3690427 4.75% 84.62% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 3148985 4.06% 88.68% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 6276259 8.09% 96.76% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1405987 1.81% 98.57% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 810578 1.04% 99.62% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 230421 0.30% 99.92% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 65869 0.08% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 77642580 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 77625046 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 29563 0.66% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 4229523 94.72% 95.38% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 206294 4.62% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 29841 0.67% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 2 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 4229016 94.75% 95.42% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 204408 4.58% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 195578 0.31% 0.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 29951554 47.39% 47.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 46938 0.07% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 195533 0.31% 0.31% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 29939610 47.39% 47.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 46892 0.07% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 1212 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 1207 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 26776565 42.37% 90.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 6223855 9.85% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 26772486 42.38% 90.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 6215505 9.84% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 63195717 # Type of FU issued
-system.cpu0.iq.rate 0.264347 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 4465384 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.070660 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 208632682 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 61211746 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 44166006 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 12339 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 6563 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 5520 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 67458994 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 6529 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 322005 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 63171257 # Type of FU issued
+system.cpu0.iq.rate 0.264223 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 4463267 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.070653 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 208563844 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 61162491 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 44139446 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 12207 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 6555 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 5480 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 67432539 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 6452 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 322060 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2276398 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 3543 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 16033 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 889328 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2267012 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 3473 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 16117 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 886206 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 17163737 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 367898 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 17168110 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 367587 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1683667 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 14223209 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 234272 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 50804503 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 105344 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 10355148 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 6782314 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 742198 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 56887 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 3242 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 16033 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 187141 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 147345 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 334486 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 62025172 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 26418520 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 1170545 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1681530 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 14225625 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 233605 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 50767973 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 106118 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 10341737 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 6773194 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 742853 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 56514 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 3354 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 16117 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 186814 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 146956 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 333770 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 62000418 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 26414197 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 1170839 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 116775 # number of nop insts executed
-system.cpu0.iew.exec_refs 32585401 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 6028949 # Number of branches executed
-system.cpu0.iew.exec_stores 6166881 # Number of stores executed
-system.cpu0.iew.exec_rate 0.259451 # Inst execution rate
-system.cpu0.iew.wb_sent 61495183 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 44171526 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 24314220 # num instructions producing a value
-system.cpu0.iew.wb_consumers 44686636 # num instructions consuming a value
+system.cpu0.iew.exec_nop 117384 # number of nop insts executed
+system.cpu0.iew.exec_refs 32572588 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 6026978 # Number of branches executed
+system.cpu0.iew.exec_stores 6158391 # Number of stores executed
+system.cpu0.iew.exec_rate 0.259325 # Inst execution rate
+system.cpu0.iew.wb_sent 61472286 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 44144926 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 24307807 # num instructions producing a value
+system.cpu0.iew.wb_consumers 44674584 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.184769 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.544105 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.184642 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.544108 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 10365934 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 776696 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 291216 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 75958913 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.525792 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.508136 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 10350620 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 776413 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 290797 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 75943516 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.525572 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.508217 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 61730922 81.27% 81.27% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 6914068 9.10% 90.37% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 2040925 2.69% 93.06% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 1133695 1.49% 94.55% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 1039727 1.37% 95.92% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 547660 0.72% 96.64% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 699909 0.92% 97.56% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 371161 0.49% 98.05% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1480846 1.95% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 61731521 81.29% 81.29% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 6903711 9.09% 90.38% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 2039504 2.69% 93.06% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 1132941 1.49% 94.55% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 1032773 1.36% 95.91% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 549051 0.72% 96.64% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 702703 0.93% 97.56% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 370837 0.49% 98.05% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1480475 1.95% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 75958913 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 31284581 # Number of instructions committed
-system.cpu0.commit.committedOps 39938560 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 75943516 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 31268406 # Number of instructions committed
+system.cpu0.commit.committedOps 39913766 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 13971736 # Number of memory references committed
-system.cpu0.commit.loads 8078750 # Number of loads committed
-system.cpu0.commit.membars 212403 # Number of memory barriers committed
-system.cpu0.commit.branches 5205711 # Number of branches committed
-system.cpu0.commit.fp_insts 5497 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 35286774 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 514203 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 1480846 # number cycles where commit BW limit reached
+system.cpu0.commit.refs 13961713 # Number of memory references committed
+system.cpu0.commit.loads 8074725 # Number of loads committed
+system.cpu0.commit.membars 212370 # Number of memory barriers committed
+system.cpu0.commit.branches 5203416 # Number of branches committed
+system.cpu0.commit.fp_insts 5433 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 35263906 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 513958 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 1480475 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 123805555 # The number of ROB reads
-system.cpu0.rob.rob_writes 102335061 # The number of ROB writes
-system.cpu0.timesIdled 884089 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 161420732 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 2289699870 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 31205252 # Number of Instructions Simulated
-system.cpu0.committedOps 39859231 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 31205252 # Number of Instructions Simulated
-system.cpu0.cpi 7.660996 # CPI: Cycles Per Instruction
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+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20630.078246 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22543.402175 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21540.561806 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20630.078246 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22543.402175 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21540.561806 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 7047379 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 5653088 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 345044 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 4644809 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 3819502 # Number of BTB hits
+system.cpu1.branchPred.lookups 7038093 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 5643597 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 344397 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 4629014 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 3810883 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 82.231627 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 672042 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 34964 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 82.326020 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 671158 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 34749 # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 25308350 # DTB read hits
-system.cpu1.dtb.read_misses 36279 # DTB read misses
-system.cpu1.dtb.write_hits 5820677 # DTB write hits
-system.cpu1.dtb.write_misses 9386 # DTB write misses
+system.cpu1.dtb.read_hits 25308103 # DTB read hits
+system.cpu1.dtb.read_misses 36468 # DTB read misses
+system.cpu1.dtb.write_hits 5825949 # DTB write hits
+system.cpu1.dtb.write_misses 9352 # DTB write misses
system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 5518 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 1305 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 250 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 5514 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 1257 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 236 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 636 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 25344629 # DTB read accesses
-system.cpu1.dtb.write_accesses 5830063 # DTB write accesses
+system.cpu1.dtb.perms_faults 652 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 25344571 # DTB read accesses
+system.cpu1.dtb.write_accesses 5835301 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 31129027 # DTB hits
-system.cpu1.dtb.misses 45665 # DTB misses
-system.cpu1.dtb.accesses 31174692 # DTB accesses
-system.cpu1.itb.inst_hits 5997294 # ITB inst hits
-system.cpu1.itb.inst_misses 6928 # ITB inst misses
+system.cpu1.dtb.hits 31134052 # DTB hits
+system.cpu1.dtb.misses 45820 # DTB misses
+system.cpu1.dtb.accesses 31179872 # DTB accesses
+system.cpu1.itb.inst_hits 5997509 # ITB inst hits
+system.cpu1.itb.inst_misses 6989 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 2607 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 2597 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1462 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1435 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 6004222 # ITB inst accesses
-system.cpu1.itb.hits 5997294 # DTB hits
-system.cpu1.itb.misses 6928 # DTB misses
-system.cpu1.itb.accesses 6004222 # DTB accesses
-system.cpu1.numCycles 234192897 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 6004498 # ITB inst accesses
+system.cpu1.itb.hits 5997509 # DTB hits
+system.cpu1.itb.misses 6989 # DTB misses
+system.cpu1.itb.accesses 6004498 # DTB accesses
+system.cpu1.numCycles 234155519 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 15145693 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 46615728 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 7047379 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 4491544 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 10277592 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 2615595 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 81100 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 47506260 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 991 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles 2050 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles 43629 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 94802 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 132 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 5995185 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 443145 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 3161 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 74942742 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.773391 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.139188 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 15142136 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 46597306 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 7038093 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 4482041 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 10279188 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 2613913 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 81086 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 47501023 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 1008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles 2061 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles 42896 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 94668 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 141 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 5995399 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 442650 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 3270 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 74933804 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.773237 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.138568 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 64672921 86.30% 86.30% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 620255 0.83% 87.12% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 831184 1.11% 88.23% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 1205105 1.61% 89.84% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1036791 1.38% 91.22% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 535666 0.71% 91.94% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1369144 1.83% 93.77% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 351637 0.47% 94.24% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 4320039 5.76% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 64662280 86.29% 86.29% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 620375 0.83% 87.12% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 831799 1.11% 88.23% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 1204715 1.61% 89.84% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1045196 1.39% 91.23% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 534648 0.71% 91.95% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1368616 1.83% 93.77% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 351624 0.47% 94.24% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 4314551 5.76% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 74942742 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.030092 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.199048 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 16159158 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 47296340 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 9320957 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 457304 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 1706877 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 946060 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 86144 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 54858013 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 286862 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 1706877 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 17095317 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 18544880 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 25731919 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 8763106 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 3098607 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 51692102 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 7152 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 482288 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 2118635 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 58 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 53768769 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 237295359 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 237252975 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 42384 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 37974901 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 15793867 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 403461 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 357400 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 6244351 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 9843526 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 6693253 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 891235 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1110531 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 47673025 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 943085 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 60813772 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 81704 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 10584682 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 28040387 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 237278 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 74942742 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.811470 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.521589 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 74933804 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.030057 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.199002 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 16155094 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 47289878 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 9321974 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 458622 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 1706108 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 946431 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 86032 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 54867135 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 286067 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 1706108 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 17091509 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 18549403 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 25716073 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 8765190 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 3103459 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 51703267 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 7138 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 482463 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 2122538 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents 91 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 53752733 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 237374868 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 237332026 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 42842 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 37999603 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 15753129 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 403463 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 357307 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 6254395 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 9847442 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 6700780 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 890369 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1126759 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 47663057 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 942444 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 60816475 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 81421 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 10551432 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 27971257 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 236318 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 74933804 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.811603 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.521433 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 53203952 70.99% 70.99% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 6663470 8.89% 79.88% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 3519082 4.70% 84.58% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 2892768 3.86% 88.44% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 6218608 8.30% 96.74% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1439258 1.92% 98.66% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 735883 0.98% 99.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 209954 0.28% 99.92% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 59767 0.08% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 53188932 70.98% 70.98% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 6663266 8.89% 79.87% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 3530113 4.71% 84.58% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 2889463 3.86% 88.44% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 6218055 8.30% 96.74% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1440706 1.92% 98.66% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 733706 0.98% 99.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 209896 0.28% 99.92% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 59667 0.08% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 74942742 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 74933804 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 24319 0.56% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 4142702 94.84% 95.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 201068 4.60% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 24001 0.55% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 1 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.55% # attempts to use FU when none available
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+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 4142238 94.88% 95.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 199692 4.57% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 168088 0.28% 0.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 28444166 46.77% 47.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 46611 0.08% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 900 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 26040619 42.82% 89.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 6113365 10.05% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 168133 0.28% 0.28% # Type of FU issued
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+system.cpu1.iq.FU_type_0::IntMult 46730 0.08% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 904 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 26040768 42.82% 89.94% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 6119264 10.06% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 60813772 # Type of FU issued
-system.cpu1.iq.rate 0.259674 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 4368089 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.071827 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 201054983 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 59209073 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 41787342 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 10574 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 5911 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 4752 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 65008196 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 5577 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 302847 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 60816475 # Type of FU issued
+system.cpu1.iq.rate 0.259727 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 4365932 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.071789 # FU busy rate (busy events/executed inst)
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+system.cpu1.iq.int_inst_queue_writes 59165079 # Number of integer instruction queue writes
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+system.cpu1.iq.fp_inst_queue_reads 10680 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 5951 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 4814 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 65008639 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 5635 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 303573 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2267035 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 3168 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 14674 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 853664 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2266828 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 3041 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 14605 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 855166 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 16940133 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 457083 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 16935844 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 457097 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 1706877 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 13961840 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 229523 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 48721689 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 98782 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 9843526 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 6693253 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 669936 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 49642 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 3791 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 14674 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 166878 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 133542 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 300420 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 59454145 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 25635874 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1359627 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 1706108 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 13962333 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 229984 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 48711452 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 98533 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 9847442 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 6700780 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 669329 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 49837 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 3707 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 14605 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 166001 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 133612 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 299613 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 59448141 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 25635797 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1368334 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 105579 # number of nop insts executed
-system.cpu1.iew.exec_refs 31697240 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 5530994 # Number of branches executed
-system.cpu1.iew.exec_stores 6061366 # Number of stores executed
-system.cpu1.iew.exec_rate 0.253868 # Inst execution rate
-system.cpu1.iew.wb_sent 58875000 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 41792094 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 22753184 # num instructions producing a value
-system.cpu1.iew.wb_consumers 41716740 # num instructions consuming a value
+system.cpu1.iew.exec_nop 105951 # number of nop insts executed
+system.cpu1.iew.exec_refs 31702689 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 5524822 # Number of branches executed
+system.cpu1.iew.exec_stores 6066892 # Number of stores executed
+system.cpu1.iew.exec_rate 0.253883 # Inst execution rate
+system.cpu1.iew.wb_sent 58868959 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 41790607 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 22765083 # num instructions producing a value
+system.cpu1.iew.wb_consumers 41748877 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.178452 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.545421 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.178474 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.545286 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 10509796 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 705807 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 260176 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 73235865 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.516331 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.496791 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 10475750 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 706126 # The number of times commit has been forced to stall to communicate backwards
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+system.cpu1.commit.committed_per_cycle::mean 0.516730 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.497193 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 59723279 81.55% 81.55% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 6657456 9.09% 90.64% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 1906988 2.60% 93.24% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1010218 1.38% 94.62% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 959564 1.31% 95.93% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 524950 0.72% 96.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 702340 0.96% 97.61% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 373722 0.51% 98.12% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1377348 1.88% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 59700930 81.53% 81.53% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 6668134 9.11% 90.63% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 1908648 2.61% 93.24% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1011673 1.38% 94.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 958934 1.31% 95.93% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 524760 0.72% 96.65% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 701730 0.96% 97.61% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 374533 0.51% 98.12% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1378354 1.88% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 73235865 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 29175677 # Number of instructions committed
-system.cpu1.commit.committedOps 37813970 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 73227696 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 29191864 # Number of instructions committed
+system.cpu1.commit.committedOps 37838928 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 13416080 # Number of memory references committed
-system.cpu1.commit.loads 7576491 # Number of loads committed
-system.cpu1.commit.membars 191234 # Number of memory barriers committed
-system.cpu1.commit.branches 4755917 # Number of branches committed
-system.cpu1.commit.fp_insts 4715 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 33570741 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 477112 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 1377348 # number cycles where commit BW limit reached
+system.cpu1.commit.refs 13426228 # Number of memory references committed
+system.cpu1.commit.loads 7580614 # Number of loads committed
+system.cpu1.commit.membars 191280 # Number of memory barriers committed
+system.cpu1.commit.branches 4758264 # Number of branches committed
+system.cpu1.commit.fp_insts 4779 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 33593707 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 477362 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 1378354 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 119309924 # The number of ROB reads
-system.cpu1.rob.rob_writes 98406667 # The number of ROB writes
-system.cpu1.timesIdled 873323 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 159250155 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 2285809379 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 29104625 # Number of Instructions Simulated
-system.cpu1.committedOps 37742918 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 29104625 # Number of Instructions Simulated
-system.cpu1.cpi 8.046587 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 8.046587 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.124276 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.124276 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 269354983 # number of integer regfile reads
-system.cpu1.int_regfile_writes 42881539 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 22070 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 19722 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 14807942 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 402452 # number of misc regfile writes
+system.cpu1.rob.rob_reads 119292034 # The number of ROB reads
+system.cpu1.rob.rob_writes 98387822 # The number of ROB writes
+system.cpu1.timesIdled 873010 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 159221715 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 2285865988 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 29120710 # Number of Instructions Simulated
+system.cpu1.committedOps 37767774 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 29120710 # Number of Instructions Simulated
+system.cpu1.cpi 8.040859 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 8.040859 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.124365 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.124365 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 269346342 # number of integer regfile reads
+system.cpu1.int_regfile_writes 42878504 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 22102 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 19714 # number of floating regfile writes
+system.cpu1.misc_regfile_reads 14810651 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 402789 # number of misc regfile writes
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192818443837 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1192818443837 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192818443837 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1192818443837 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192717579972 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1192717579972 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192717579972 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1192717579972 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 83054 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 83049 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
sim_ticks 2608778789000 # Number of ticks simulated
final_tick 2608778789000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 458042 # Simulator instruction rate (inst/s)
-host_op_rate 582855 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 19847185908 # Simulator tick rate (ticks/s)
-host_mem_usage 403628 # Number of bytes of host memory used
-host_seconds 131.44 # Real time elapsed on the host
+host_inst_rate 616577 # Simulator instruction rate (inst/s)
+host_op_rate 784589 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 26716567066 # Simulator tick rate (ticks/s)
+host_mem_usage 403640 # Number of bytes of host memory used
+host_seconds 97.65 # Real time elapsed on the host
sim_insts 60206536 # Number of instructions simulated
sim_ops 76612339 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 419296 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4486284 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4486348 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 285888 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4557412 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 4557348 # Number of bytes read from this memory
system.physmem.bytes_read::total 132432464 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 419296 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 285888 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 705184 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3671168 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1520308 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 1495832 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 1520260 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 1495880 # Number of bytes written to this memory
system.physmem.bytes_written::total 6687308 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 12754 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 70131 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 70132 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 4467 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 71233 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 71232 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15494012 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57362 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 380077 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 373958 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 380065 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 373970 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811397 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47027135 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 25 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 160725 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1719687 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1719712 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 109587 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1746952 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 1746928 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 50764160 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 160725 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 109587 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 270312 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1407236 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 582766 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 573384 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 582748 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 573402 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2563386 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1407236 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47027135 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 160725 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 2302454 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 2302460 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 109587 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 2320336 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 2320330 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53327546 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15494012 # Total number of read requests seen
system.physmem.writeReqs 811397 # Total number of write requests seen
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 151912 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 754035 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 57362 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 4515 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1116413 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 960010 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 974367 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3651904 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2754719 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2759720 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2733933 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 61766 # What read queue length does an incoming req see
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 754035 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 57362 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 1116374 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 60421 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 111612 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 162702 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::21 35124 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35107 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 13 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 338341857800 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 433208122800 # Sum of mem lat for all requests
+system.physmem.wrQLenPdf::23 26 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
+system.physmem.totQLat 338360116500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 433225996500 # Sum of mem lat for all requests
system.physmem.totBusLat 77469930000 # Total cycles spent in databus access
-system.physmem.totBankLat 17396335000 # Total cycles spent in bank access
-system.physmem.avgQLat 21836.98 # Average queueing delay per request
-system.physmem.avgBankLat 1122.78 # Average bank access latency per request
+system.physmem.totBankLat 17395950000 # Total cycles spent in bank access
+system.physmem.avgQLat 21838.16 # Average queueing delay per request
+system.physmem.avgBankLat 1122.75 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 27959.76 # Average memory access latency
+system.physmem.avgMemAccLat 27960.91 # Average memory access latency
system.physmem.avgRdBW 380.11 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 19.91 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 50.76 # Average consumed read bandwidth in MB/s
system.physmem.busUtil 3.13 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.17 # Average read queue length over time
system.physmem.avgWrQLen 1.24 # Average write queue length over time
-system.physmem.readRowHits 15419486 # Number of row buffer hits during reads
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+system.cpu0.dcache.overall_mshr_misses::cpu1.data 307004 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 619577 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2308266500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2198368500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4506635000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3684595000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3854585000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7539180000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66669000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 65974000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 132643000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5992861500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6052953500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 12045815000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5992861500 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6052953500 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 12045815000 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91377449500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90718593500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182096043000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 9611433000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 9088267500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 18699700500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2308020000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2198619500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4506639500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3684716000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3854071000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7538787000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66680000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 65950000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 132630000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5992736000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6052690500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 12045426500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5992736000 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6052690500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 12045426500 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91377755000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90718296000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182096051000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 9611257000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 9088544500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 18699801500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 117500 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 117500 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 100988882500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 99806861000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200795743500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027677 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026722 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 100989012000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 99806840500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200795852500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027678 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026720 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027200 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024605 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024407 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024606 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024406 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048841 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043685 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048849 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043678 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046074 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026367 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025719 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026368 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025718 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.026042 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026367 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025719 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026368 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025718 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.026042 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12267.246831 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12155.890582 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12212.672724 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29619.883276 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30551.209498 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30088.839578 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11890.315677 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11359.159780 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11620.061323 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19173.414150 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19715.433398 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19441.998331 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19173.414150 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19715.433398 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19441.998331 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12265.219794 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12158.017994 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12212.684919 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29620.617861 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30547.377682 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30087.271116 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11890.156919 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11356.982952 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11618.922470 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19172.276556 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19715.347357 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19441.371290 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19172.276556 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19715.347357 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19441.371290 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 7490923 # DTB read hits
-system.cpu1.dtb.read_misses 7080 # DTB read misses
-system.cpu1.dtb.write_hits 5680189 # DTB write hits
-system.cpu1.dtb.write_misses 1780 # DTB write misses
+system.cpu1.dtb.read_hits 7490951 # DTB read hits
+system.cpu1.dtb.read_misses 7083 # DTB read misses
+system.cpu1.dtb.write_hits 5680260 # DTB write hits
+system.cpu1.dtb.write_misses 1778 # DTB write misses
system.cpu1.dtb.flush_tlb 1275 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 6451 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 6452 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 157 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 207 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 7498003 # DTB read accesses
-system.cpu1.dtb.write_accesses 5681969 # DTB write accesses
+system.cpu1.dtb.read_accesses 7498034 # DTB read accesses
+system.cpu1.dtb.write_accesses 5682038 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 13171112 # DTB hits
-system.cpu1.dtb.misses 8860 # DTB misses
-system.cpu1.dtb.accesses 13179972 # DTB accesses
-system.cpu1.itb.inst_hits 30733895 # ITB inst hits
+system.cpu1.dtb.hits 13171211 # DTB hits
+system.cpu1.dtb.misses 8861 # DTB misses
+system.cpu1.dtb.accesses 13180072 # DTB accesses
+system.cpu1.itb.inst_hits 30733845 # ITB inst hits
system.cpu1.itb.inst_misses 3661 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 30737556 # ITB inst accesses
-system.cpu1.itb.hits 30733895 # DTB hits
+system.cpu1.itb.inst_accesses 30737506 # ITB inst accesses
+system.cpu1.itb.hits 30733845 # DTB hits
system.cpu1.itb.misses 3661 # DTB misses
-system.cpu1.itb.accesses 30737556 # DTB accesses
-system.cpu1.numCycles 2664665536 # number of cpu cycles simulated
+system.cpu1.itb.accesses 30737506 # DTB accesses
+system.cpu1.numCycles 2664661810 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 30062453 # Number of instructions committed
-system.cpu1.committedOps 38319221 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 34454483 # Number of integer alu accesses
+system.cpu1.committedInsts 30062381 # Number of instructions committed
+system.cpu1.committedOps 38319191 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 34454554 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 4993 # Number of float alu accesses
-system.cpu1.num_func_calls 1098871 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3931518 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 34454483 # number of integer instructions
+system.cpu1.num_func_calls 1098878 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 3931539 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 34454554 # number of integer instructions
system.cpu1.num_fp_insts 4993 # number of float instructions
-system.cpu1.num_int_register_reads 197476279 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 37039984 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 197476132 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 37039734 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 3571 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1424 # number of times the floating registers were written
-system.cpu1.num_mem_refs 13738954 # number of memory refs
-system.cpu1.num_load_insts 7815473 # Number of load instructions
-system.cpu1.num_store_insts 5923481 # Number of store instructions
-system.cpu1.num_idle_cycles 1359992851.787481 # Number of idle cycles
-system.cpu1.num_busy_cycles 1304672684.212520 # Number of busy cycles
+system.cpu1.num_mem_refs 13739046 # number of memory refs
+system.cpu1.num_load_insts 7815505 # Number of load instructions
+system.cpu1.num_store_insts 5923541 # Number of store instructions
+system.cpu1.num_idle_cycles 1359990951.127739 # Number of idle cycles
+system.cpu1.num_busy_cycles 1304670858.872261 # Number of busy cycles
system.cpu1.not_idle_fraction 0.489620 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.510380 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1196180344448 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1196180344448 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1196180344448 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1196180344448 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1196198690564 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1196198690564 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1196198690564 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1196198690564 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 5.140861 # Number of seconds simulated
-sim_ticks 5140860798000 # Number of ticks simulated
-final_tick 5140860798000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.136865 # Number of seconds simulated
+sim_ticks 5136864535500 # Number of ticks simulated
+final_tick 5136864535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 170494 # Simulator instruction rate (inst/s)
-host_op_rate 337025 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2148706625 # Simulator tick rate (ticks/s)
-host_mem_usage 754648 # Number of bytes of host memory used
-host_seconds 2392.54 # Real time elapsed on the host
-sim_insts 407913764 # Number of instructions simulated
-sim_ops 806343994 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 2474560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory
+host_inst_rate 199949 # Simulator instruction rate (inst/s)
+host_op_rate 395248 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2517891877 # Simulator tick rate (ticks/s)
+host_mem_usage 755196 # Number of bytes of host memory used
+host_seconds 2040.15 # Real time elapsed on the host
+sim_insts 407925588 # Number of instructions simulated
+sim_ops 806363480 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide 2498048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 3136 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1078400 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10800768 # Number of bytes read from this memory
-system.physmem.bytes_read::total 14357184 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1078400 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1078400 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9566720 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9566720 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 38665 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst 1077760 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10804608 # Number of bytes read from this memory
+system.physmem.bytes_read::total 14383936 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1077760 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1077760 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9566528 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9566528 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 39032 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 49 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 16850 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 168762 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 224331 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 149480 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 149480 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 481351 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 598 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst 16840 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 168822 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 224749 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 149477 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 149477 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 486298 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 610 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 209770 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2100965 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2792759 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 209770 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 209770 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1860918 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1860918 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1860918 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 481351 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 598 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 209809 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2103347 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2800139 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 209809 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 209809 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1862328 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1862328 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1862328 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 486298 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 610 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 209770 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2100965 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4653677 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 224331 # Total number of read requests seen
-system.physmem.writeReqs 149480 # Total number of write requests seen
-system.physmem.cpureqs 389156 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 14357184 # Total number of bytes read from memory
-system.physmem.bytesWritten 9566720 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 14357184 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 9566720 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 64 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4099 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 14350 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 13262 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 13450 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 16479 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 13640 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 13135 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 13368 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 16367 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 13625 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 12973 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 13147 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 15567 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 13297 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 12659 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 13305 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 15643 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 9342 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 8759 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 8814 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 11838 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 8747 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 8497 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 8701 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 11708 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 8726 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 8403 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 8587 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 10999 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 8504 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 8205 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 8619 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 11031 # Track writes on a per bank basis
+system.physmem.bw_total::cpu.inst 209809 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2103347 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4662468 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 224749 # Total number of read requests seen
+system.physmem.writeReqs 149477 # Total number of write requests seen
+system.physmem.cpureqs 378758 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 14383936 # Total number of bytes read from memory
+system.physmem.bytesWritten 9566528 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 14383936 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 9566528 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 97 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 3970 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 14108 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 13038 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 13174 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 16315 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 13707 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 13158 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 13525 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 16255 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 13935 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 13285 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 13290 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 15648 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 13203 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 12660 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 13428 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 15923 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 9005 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 8432 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 8529 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 11625 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 8800 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 8560 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 8903 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 11692 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 9007 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 8684 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 8693 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 11170 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 8382 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 8108 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 8695 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 11192 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1147 # Number of times wr buffer was full causing retry
-system.physmem.totGap 5140860745500 # Total gap between requests
+system.physmem.numWrRetry 562 # Number of times wr buffer was full causing retry
+system.physmem.totGap 5136864483000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 224331 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 150627 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 4099 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 173172 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 19537 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 7348 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3492 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::8 1784 # What read queue length does an incoming req see
+system.physmem.readPktSize::6 224749 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 149477 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 173174 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 5364 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6499 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::24 782 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 172 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 98 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 56 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 30 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 4794174501 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 9303317001 # Sum of mem lat for all requests
-system.physmem.totBusLat 1121335000 # Total cycles spent in databus access
-system.physmem.totBankLat 3387807500 # Total cycles spent in bank access
-system.physmem.avgQLat 21377.08 # Average queueing delay per request
-system.physmem.avgBankLat 15106.13 # Average bank access latency per request
+system.physmem.wrQLenPdf::23 1140 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 786 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 183 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 101 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 61 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 13 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see
+system.physmem.totQLat 4764271250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 9277483750 # Sum of mem lat for all requests
+system.physmem.totBusLat 1123260000 # Total cycles spent in databus access
+system.physmem.totBankLat 3389952500 # Total cycles spent in bank access
+system.physmem.avgQLat 21207.34 # Average queueing delay per request
+system.physmem.avgBankLat 15089.79 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 41483.22 # Average memory access latency
-system.physmem.avgRdBW 2.79 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 41297.13 # Average memory access latency
+system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 2.79 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 8.88 # Average write queue length over time
-system.physmem.readRowHits 193356 # Number of row buffer hits during reads
-system.physmem.writeRowHits 105797 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 86.22 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 70.78 # Row buffer hit rate for writes
-system.physmem.avgGap 13752566.79 # Average gap between requests
-system.iocache.replacements 47574 # number of replacements
-system.iocache.tagsinuse 0.128668 # Cycle average of tags in use
+system.physmem.avgWrQLen 11.02 # Average write queue length over time
+system.physmem.readRowHits 193727 # Number of row buffer hits during reads
+system.physmem.writeRowHits 105780 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 86.23 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 70.77 # Row buffer hit rate for writes
+system.physmem.avgGap 13726637.07 # Average gap between requests
+system.iocache.replacements 47576 # number of replacements
+system.iocache.tagsinuse 0.116322 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 47590 # Sample count of references to valid blocks.
+system.iocache.sampled_refs 47592 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 4991908358000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide 0.128668 # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide 0.008042 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.008042 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 909 # number of ReadReq misses
+system.iocache.warmup_cycle 4991909238000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::pc.south_bridge.ide 0.116322 # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide 0.007270 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.007270 # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 911 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47629 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses
-system.iocache.overall_misses::total 47629 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143200932 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 143200932 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10097082160 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10097082160 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 10240283092 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10240283092 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 10240283092 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10240283092 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses
+system.iocache.demand_misses::total 47631 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses
+system.iocache.overall_misses::total 47631 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151593932 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 151593932 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10023192160 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10023192160 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 10174786092 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10174786092 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 10174786092 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 10174786092 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 157536.778878 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 157536.778878 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 216119.053082 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 216119.053082 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 215001.009721 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 215001.009721 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 215001.009721 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 215001.009721 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 136887 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166403.877058 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 166403.877058 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214537.503425 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 214537.503425 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 213616.890093 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 213616.890093 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 213616.890093 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 213616.890093 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 136470 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 12650 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 12410 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 10.821107 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10.996777 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 47629 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 47629 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 47629 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 47629 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95911989 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 95911989 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7666293817 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 7666293817 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7762205806 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 7762205806 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7762205806 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 7762205806 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104200712 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 104200712 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7592410619 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 7592410619 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7696611331 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 7696611331 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7696611331 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 7696611331 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105513.739274 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 105513.739274 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 164090.193001 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 164090.193001 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162972.260724 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 162972.260724 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162972.260724 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 162972.260724 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114380.583974 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 114380.583974 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162508.788934 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 162508.788934 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 161588.279293 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 161588.279293 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 161588.279293 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 161588.279293 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 86195570 # Number of BP lookups
-system.cpu.branchPred.condPredicted 86195570 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1107298 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 81287324 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 79211919 # Number of BTB hits
+system.cpu.branchPred.lookups 86198193 # Number of BP lookups
+system.cpu.branchPred.condPredicted 86198193 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1106234 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 81290548 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 79213904 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.446828 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 97.445405 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.numCycles 448232203 # number of cpu cycles simulated
+system.cpu.numCycles 448153841 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 27444393 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 425935714 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 86195570 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 79211919 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 163577459 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4703661 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 120329 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 63100618 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 36734 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 50393 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 9010824 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 484273 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 3255 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 257888489 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.260624 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.418001 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 27415171 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 425937394 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 86198193 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 79213904 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 163576958 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4698498 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 117961 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 63103393 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 36350 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 51299 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 436 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 9010068 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 483485 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 3126 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 257855511 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 3.261045 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.418033 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 94737944 36.74% 36.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1567529 0.61% 37.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 71915391 27.89% 65.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 936422 0.36% 65.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1600476 0.62% 66.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2419747 0.94% 67.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1072144 0.42% 67.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1374255 0.53% 68.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 82264581 31.90% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 94705411 36.73% 36.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1566235 0.61% 37.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 71918028 27.89% 65.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 935930 0.36% 65.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1598963 0.62% 66.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2419267 0.94% 67.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1070398 0.42% 67.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1376464 0.53% 68.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 82264815 31.90% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 257888489 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.192301 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.950257 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 31158433 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 60539785 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 159369860 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3262201 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3558210 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 837747525 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 908 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3558210 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 33896779 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 37429027 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 10979367 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 159568616 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 12456490 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 834117350 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 19334 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 5870357 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4754276 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 7741 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 995632267 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1810669462 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1810668566 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 896 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 964317189 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 31315071 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 459232 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 466806 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 28815526 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 17065121 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 10125717 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1247966 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 991465 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 828007231 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1251140 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 823065161 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 148512 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 22000890 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 33478625 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 198442 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 257888489 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 3.191554 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.384086 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 257855511 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.192341 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.950427 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31132857 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 60536501 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 159370274 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3261936 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3553943 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 837748670 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 951 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3553943 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 33869883 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 37385632 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 11021591 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 159568277 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 12456185 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 834115262 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 19668 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 5867494 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4754545 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 8312 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 995635482 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1810665967 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1810665163 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 804 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 964341342 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 31294133 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 459159 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 467055 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 28798095 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 17056943 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 10123506 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1248285 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 987203 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 827998215 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1251183 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 823066756 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 148002 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 21984557 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 33441202 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 198541 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 257855511 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 3.191969 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.384014 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 71416188 27.69% 27.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 15522620 6.02% 33.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 10297220 3.99% 37.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7470539 2.90% 40.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 75900478 29.43% 70.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3837629 1.49% 71.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72511548 28.12% 99.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 780997 0.30% 99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 151270 0.06% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 71390186 27.69% 27.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 15517919 6.02% 33.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 10294138 3.99% 37.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7464826 2.89% 40.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 75904474 29.44% 70.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3838948 1.49% 71.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 72513480 28.12% 99.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 779753 0.30% 99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 151787 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 257888489 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 257855511 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 362608 34.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 553228 51.88% 85.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 150521 14.12% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 363612 34.06% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 553162 51.82% 85.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 150741 14.12% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 311367 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 795535215 96.66% 96.69% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 311137 0.04% 0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 795540449 96.66% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 17840146 2.17% 98.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9378433 1.14% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 17836742 2.17% 98.86% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 9378428 1.14% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 823065161 # Type of FU issued
-system.cpu.iq.rate 1.836247 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1066357 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001296 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1905364388 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 851269170 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 818594497 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 333 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 414 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 81 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 823820002 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 149 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1640065 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 823066756 # Type of FU issued
+system.cpu.iq.rate 1.836572 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1067515 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1905334904 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 851243829 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 818598323 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 260 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 368 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 63 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 823823020 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 114 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1639481 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 3087216 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 23041 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 11568 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1713876 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 3079539 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 22701 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 11520 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1710580 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1932419 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 12043 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 1932434 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 12204 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3558210 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 26163339 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2115746 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 829258371 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 321958 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 17065121 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 10125717 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 719121 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1615790 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 11387 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 11568 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 649229 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 593828 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1243057 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 821192043 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 17430508 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1873117 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3553943 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 26124965 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 2116869 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 829249398 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 321104 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 17056943 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 10123506 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 718931 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1615774 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 10404 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 11520 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 649169 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 592997 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1242166 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 821195112 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 17426068 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1871643 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 26576754 # number of memory reference insts executed
-system.cpu.iew.exec_branches 83195358 # Number of branches executed
-system.cpu.iew.exec_stores 9146246 # Number of stores executed
-system.cpu.iew.exec_rate 1.832068 # Inst execution rate
-system.cpu.iew.wb_sent 820730031 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 818594578 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 639788924 # num instructions producing a value
-system.cpu.iew.wb_consumers 1045548924 # num instructions consuming a value
+system.cpu.iew.exec_refs 26572625 # number of memory reference insts executed
+system.cpu.iew.exec_branches 83197450 # Number of branches executed
+system.cpu.iew.exec_stores 9146557 # Number of stores executed
+system.cpu.iew.exec_rate 1.832396 # Inst execution rate
+system.cpu.iew.wb_sent 820733466 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 818598386 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 639795417 # num instructions producing a value
+system.cpu.iew.wb_consumers 1045555736 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.826273 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.611917 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.826601 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 22806507 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1052696 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1111685 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 254330279 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 3.170460 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.853927 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 22777543 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1052640 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 1110740 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 254301568 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 3.170895 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.853974 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 82551524 32.46% 32.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11813015 4.64% 37.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3912372 1.54% 38.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 74944552 29.47% 68.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2436279 0.96% 69.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1482727 0.58% 69.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 942941 0.37% 70.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 70918770 27.88% 97.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5328099 2.09% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 82529406 32.45% 32.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11802979 4.64% 37.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3912644 1.54% 38.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 74944166 29.47% 68.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2437687 0.96% 69.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1481720 0.58% 69.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 940520 0.37% 70.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 70919321 27.89% 97.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5333125 2.10% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 254330279 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 407913764 # Number of instructions committed
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system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
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-system.cpu.itb_walker_cache.demand_accesses::total 36445 # number of demand (read+write) accesses
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-system.cpu.itb_walker_cache.overall_miss_rate::total 0.291288 # miss rate for overall accesses
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-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11213.592690 # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11213.592690 # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11213.592690 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11213.592690 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11213.592690 # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36179 # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total 36179 # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36179 # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total 36179 # number of overall (read+write) accesses
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+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11122.663997 # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11122.663997 # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11122.663997 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11122.663997 # average overall miss latency
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system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks 2031 # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total 2031 # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10616 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10616 # number of ReadReq MSHR misses
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-system.cpu.itb_walker_cache.demand_mshr_misses::total 10616 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10616 # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total 10616 # number of overall MSHR misses
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-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 97811500 # number of ReadReq MSHR miss cycles
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-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 97811500 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 97811500 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.291304 # mshr miss rate for ReadReq accesses
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-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9213.592690 # average ReadReq mshr miss latency
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-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9213.592690 # average overall mshr miss latency
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-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9213.592690 # average overall mshr miss latency
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+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9122.663997 # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average overall mshr miss latency
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+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9122.663997 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements 109067 # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse 12.961436 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs 135080 # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs 109080 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs 1.238357 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5099784110000 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.961436 # Average occupied blocks per requestor
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-system.cpu.dtb_walker_cache.occ_percent::total 0.810090 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 135158 # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total 135158 # number of ReadReq hits
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-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.448940 # miss rate for overall accesses
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-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12577.598968 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12577.598968 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12577.598968 # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12577.598968 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12577.598968 # average overall miss latency
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+system.cpu.dtb_walker_cache.sampled_refs 108196 # Sample count of references to valid blocks.
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+system.cpu.dtb_walker_cache.ReadReq_hits::total 134886 # number of ReadReq hits
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+system.cpu.dtb_walker_cache.ReadReq_accesses::total 244104 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 244104 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total 244104 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 244104 # number of overall (read+write) accesses
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+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.447424 # miss rate for demand accesses
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+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.447424 # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total 0.447424 # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12590.561995 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12590.561995 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12590.561995 # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12590.561995 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12590.561995 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12590.561995 # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
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-system.cpu.dtb_walker_cache.writebacks::total 36570 # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110111 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110111 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110111 # number of demand (read+write) MSHR misses
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-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110111 # number of overall MSHR misses
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-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1164710000 # number of overall MSHR miss cycles
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-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.448940 # mshr miss rate for demand accesses
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-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.448940 # mshr miss rate for overall accesses
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-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10577.598968 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10577.598968 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10577.598968 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10577.598968 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10577.598968 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10577.598968 # average overall mshr miss latency
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sim_ticks 5204982530500 # Number of ticks simulated
final_tick 5204982530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_ops 207160582 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 35152 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 512 # Categorize read packet sizes
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system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see
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system.physmem.totBusLat 4050000 # Total cycles spent in databus access
system.physmem.totBankLat 7548750 # Total cycles spent in bank access
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system.physmem.avgBankLat 9319.44 # Average bank access latency per request
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system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s
sim_ticks 269671683500 # Number of ticks simulated
final_tick 269671683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
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system.physmem.totBusLat 131400000 # Total cycles spent in databus access
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system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114099.393939 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses
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-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3783295500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3783295500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426949500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6426949500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426949500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6426949500 # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3782424000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3782424000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426078000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6426078000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426078000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6426078000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.343961 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.343961 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14885.311788 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14885.311788 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14881.882886 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14881.882886 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14110.998144 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 14110.998144 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14110.998144 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 14110.998144 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.133806 # Number of seconds simulated
-sim_ticks 133806308500 # Number of ticks simulated
-final_tick 133806308500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.133774 # Number of seconds simulated
+sim_ticks 133773851500 # Number of ticks simulated
+final_tick 133773851500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 271409 # Simulator instruction rate (inst/s)
-host_op_rate 271409 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 64213833 # Simulator tick rate (ticks/s)
-host_mem_usage 226532 # Number of bytes of host memory used
-host_seconds 2083.76 # Real time elapsed on the host
+host_inst_rate 262576 # Simulator instruction rate (inst/s)
+host_op_rate 262576 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 62108832 # Simulator tick rate (ticks/s)
+host_mem_usage 226536 # Number of bytes of host memory used
+host_seconds 2153.86 # Real time elapsed on the host
sim_insts 565552443 # Number of instructions simulated
sim_ops 565552443 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1636352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1697856 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 67200 # Number of bytes written to this memory
-system.physmem.bytes_written::total 67200 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 25568 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 26529 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1050 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1050 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 459649 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 12229259 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 12688908 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 459649 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 459649 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 502218 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 502218 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 502218 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 459649 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 12229259 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 13191127 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 26529 # Total number of read requests seen
-system.physmem.writeReqs 1050 # Total number of write requests seen
-system.physmem.cpureqs 27579 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 1697856 # Total number of bytes read from memory
-system.physmem.bytesWritten 67200 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 1697856 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 67200 # bytesWritten derated as per pkt->getSize()
+system.physmem.bytes_read::cpu.inst 60992 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1636544 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1697536 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 60992 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 60992 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 67072 # Number of bytes written to this memory
+system.physmem.bytes_written::total 67072 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 953 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 25571 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 26524 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1048 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1048 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 455934 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 12233661 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 12689595 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 455934 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 455934 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 501383 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 501383 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 501383 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 455934 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 12233661 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 13190979 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 26524 # Total number of read requests seen
+system.physmem.writeReqs 1048 # Total number of write requests seen
+system.physmem.cpureqs 27572 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1697536 # Total number of bytes read from memory
+system.physmem.bytesWritten 67072 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 1697536 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 67072 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 1632 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 1631 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 1662 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 1679 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1680 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1686 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 1626 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1603 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1584 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 1608 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 1668 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1666 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 1722 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 1650 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 1645 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 1723 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 1666 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 1676 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 1684 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 61 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::10 1648 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 1647 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1724 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1665 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1675 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 1682 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 60 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 68 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 65 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 61 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 74 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 73 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 81 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 133806263000 # Total gap between requests
+system.physmem.totGap 133773818000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 26529 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 1050 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 8850 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 11428 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 5136 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1089 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see
+system.physmem.readPktSize::6 26524 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 1048 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 8806 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 11451 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 5143 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1096 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 46 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 46 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 648232398 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 1339932398 # Sum of mem lat for all requests
-system.physmem.totBusLat 132570000 # Total cycles spent in databus access
-system.physmem.totBankLat 559130000 # Total cycles spent in bank access
-system.physmem.avgQLat 24448.68 # Average queueing delay per request
-system.physmem.avgBankLat 21088.10 # Average bank access latency per request
+system.physmem.totQLat 654284750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 1345973500 # Sum of mem lat for all requests
+system.physmem.totBusLat 132545000 # Total cycles spent in databus access
+system.physmem.totBankLat 559143750 # Total cycles spent in bank access
+system.physmem.avgQLat 24681.61 # Average queueing delay per request
+system.physmem.avgBankLat 21092.60 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 50536.79 # Average memory access latency
+system.physmem.avgMemAccLat 50774.21 # Average memory access latency
system.physmem.avgRdBW 12.69 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 12.69 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.10 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 10.03 # Average write queue length over time
-system.physmem.readRowHits 16972 # Number of row buffer hits during reads
-system.physmem.writeRowHits 273 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 64.01 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 26.00 # Row buffer hit rate for writes
-system.physmem.avgGap 4851744.55 # Average gap between requests
-system.cpu.branchPred.lookups 76500721 # Number of BP lookups
-system.cpu.branchPred.condPredicted 70919742 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 2718676 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 43116993 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 41952631 # Number of BTB hits
+system.physmem.avgWrQLen 9.24 # Average write queue length over time
+system.physmem.readRowHits 16966 # Number of row buffer hits during reads
+system.physmem.writeRowHits 271 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 64.00 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes
+system.physmem.avgGap 4851799.58 # Average gap between requests
+system.cpu.branchPred.lookups 76502410 # Number of BP lookups
+system.cpu.branchPred.condPredicted 70922676 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2717282 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 43095322 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 41949760 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.299529 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1606312 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 238 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 97.341795 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1606512 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 241 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 122623794 # DTB read hits
-system.cpu.dtb.read_misses 28860 # DTB read misses
+system.cpu.dtb.read_hits 122629608 # DTB read hits
+system.cpu.dtb.read_misses 28810 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 122652654 # DTB read accesses
-system.cpu.dtb.write_hits 40761180 # DTB write hits
-system.cpu.dtb.write_misses 25673 # DTB write misses
+system.cpu.dtb.read_accesses 122658418 # DTB read accesses
+system.cpu.dtb.write_hits 40760367 # DTB write hits
+system.cpu.dtb.write_misses 25602 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 40786853 # DTB write accesses
-system.cpu.dtb.data_hits 163384974 # DTB hits
-system.cpu.dtb.data_misses 54533 # DTB misses
+system.cpu.dtb.write_accesses 40785969 # DTB write accesses
+system.cpu.dtb.data_hits 163389975 # DTB hits
+system.cpu.dtb.data_misses 54412 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 163439507 # DTB accesses
-system.cpu.itb.fetch_hits 65534932 # ITB hits
+system.cpu.dtb.data_accesses 163444387 # DTB accesses
+system.cpu.itb.fetch_hits 65529846 # ITB hits
system.cpu.itb.fetch_misses 41 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 65534973 # ITB accesses
+system.cpu.itb.fetch_accesses 65529887 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 267612618 # number of cpu cycles simulated
+system.cpu.numCycles 267547704 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 67186400 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 699453099 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 76500721 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 43558943 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 117852914 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 11666249 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 73358963 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 67181660 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 699454641 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 76502410 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 43556272 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 117851527 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 11664601 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 73301689 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1199 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 10 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 65534932 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 934826 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 267314333 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.616594 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.444810 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles 21 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 65529846 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 933458 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 267250540 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.617224 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.444995 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 149461419 55.91% 55.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 10349982 3.87% 59.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 11850266 4.43% 64.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 10577716 3.96% 68.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 7012506 2.62% 70.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2870690 1.07% 71.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 3579816 1.34% 73.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 3108437 1.16% 74.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 68503501 25.63% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 149399013 55.90% 55.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 10348526 3.87% 59.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 11849388 4.43% 64.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 10578020 3.96% 68.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 7012807 2.62% 70.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2871984 1.07% 71.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 3578789 1.34% 73.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 3106707 1.16% 74.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 68505306 25.63% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 267314333 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.285864 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.613678 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 84322022 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 57655855 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 102751859 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 13670665 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 8913932 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3876852 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 942 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 691462372 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 3197 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 8913932 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 92304341 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 12773232 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1346 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 103106270 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 50215212 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 681285072 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 434 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 38522944 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 5472741 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 520920645 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 897379043 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 897376453 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 2590 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 267250540 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.285939 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.614317 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 84320129 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 57595253 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 102753479 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 13668133 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 8913546 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3876280 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 932 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 691464517 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 3449 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 8913546 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 92299678 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 12776720 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 1189 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 103108433 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 50150974 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 681302234 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 431 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 38477727 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 5455282 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 520934901 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 897390123 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 897387366 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 2757 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 57065756 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 66 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 71 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 112077327 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 127005785 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 42387861 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 14833107 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 10089887 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 621266103 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 59 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 604722021 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 299730 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 55073821 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 30009810 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 42 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 267314333 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.262213 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.825151 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 57080012 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 63 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 67 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 112027328 # count of insts added to the skid buffer
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+system.cpu.memDep0.conflictingStores 10088023 # Number of conflicting stores.
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+system.cpu.iq.iqSquashedInstsExamined 55080788 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 30005964 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 38 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::1 55954300 20.93% 40.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 53424383 19.99% 60.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 36299246 13.58% 74.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 31212895 11.68% 85.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 23807225 8.91% 94.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 10138155 3.79% 98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3408674 1.28% 99.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 555483 0.21% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 52429829 19.62% 19.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 55852855 20.90% 40.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 53444845 20.00% 60.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 36460113 13.64% 74.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 31255141 11.70% 85.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 23773948 8.90% 94.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 10075913 3.77% 98.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3406027 1.27% 99.79% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 267314333 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 267250540 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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-system.cpu.iq.fu_full::IntMult 39 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 727516 18.56% 89.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 394572 10.06% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 2756472 71.14% 71.14% # attempts to use FU when none available
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+system.cpu.iq.fu_full::IntDiv 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 728591 18.80% 89.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 389871 10.06% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 439175234 72.62% 72.62% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 7035 0.00% 72.63% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 439176954 72.62% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 7066 0.00% 72.63% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 124352577 20.56% 93.19% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 41187127 6.81% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 124356224 20.56% 93.19% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 41185515 6.81% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 604722021 # Type of FU issued
-system.cpu.iq.rate 2.259692 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 3920679 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006483 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1480975025 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 676343136 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 596595322 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 3759 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 2270 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 1723 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 608640802 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 1898 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 12279325 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 604725807 # Type of FU issued
+system.cpu.iq.rate 2.260254 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 3874974 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006408 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1480873086 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 676355161 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 596602519 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 3840 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 2402 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 1730 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 608598846 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 1935 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 12280408 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 12491743 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 36092 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 5478 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2936540 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 12494396 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 35705 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 5495 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 2933389 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 6432 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 54776 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 6442 # Number of loads that were rescheduled
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 8913932 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1438086 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 192048 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 664143136 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1694587 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 127005785 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 42387861 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 59 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 143884 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 7497 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 5478 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1342912 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1811100 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 3154012 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 599591446 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 122652830 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 5130575 # Number of squashed instructions skipped in execute
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+system.cpu.iew.iewBlockCycles 1440408 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 191911 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 664145675 # Number of instructions dispatched to IQ
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+system.cpu.iew.iewIQFullEvents 143753 # Number of times the IQ has become full, causing a stall
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+system.cpu.iew.predictedTakenIncorrect 1342563 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1811283 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 3153846 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 599598114 # Number of executed instructions
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system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 42876974 # number of nop insts executed
-system.cpu.iew.exec_refs 163458157 # number of memory reference insts executed
-system.cpu.iew.exec_branches 66641389 # Number of branches executed
-system.cpu.iew.exec_stores 40805327 # Number of stores executed
-system.cpu.iew.exec_rate 2.240520 # Inst execution rate
-system.cpu.iew.wb_sent 597536756 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 596597045 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 415962909 # num instructions producing a value
-system.cpu.iew.wb_consumers 530370743 # num instructions consuming a value
+system.cpu.iew.exec_nop 42874327 # number of nop insts executed
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+system.cpu.iew.exec_rate 2.241089 # Inst execution rate
+system.cpu.iew.wb_sent 597543507 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 596604249 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 415969736 # num instructions producing a value
+system.cpu.iew.wb_consumers 530347418 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.229331 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.784287 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.229899 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.784334 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 62162261 # The number of squashed insts skipped by commit
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system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 2717793 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 258400401 # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::mean 2.329736 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 79574518 30.80% 30.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 72566023 28.08% 58.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 25599330 9.91% 68.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 9197400 3.56% 72.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 10258446 3.97% 76.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 20921268 8.10% 84.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 6836400 2.65% 87.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3734572 1.45% 88.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 29712444 11.50% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 79521079 30.78% 30.78% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::3 9136101 3.54% 72.33% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::5 20967757 8.12% 84.41% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::7 3711202 1.44% 88.48% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.committedInsts 601856963 # Number of instructions committed
system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions.
system.cpu.commit.int_insts 563954763 # Number of committed integer instructions.
system.cpu.commit.function_calls 1197610 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 29712444 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 29749591 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 892642792 # The number of ROB reads
-system.cpu.rob.rob_writes 1336966756 # The number of ROB writes
-system.cpu.timesIdled 34291 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 298285 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 892544623 # The number of ROB reads
+system.cpu.rob.rob_writes 1336970755 # The number of ROB writes
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+system.cpu.idleCycles 297164 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
-system.cpu.cpi 0.473188 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.473188 # CPI: Total CPI of All Threads
-system.cpu.ipc 2.113325 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 2.113325 # IPC: Total IPC of All Threads
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+system.cpu.cpi 0.473073 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.473073 # CPI: Total CPI of All Threads
+system.cpu.ipc 2.113838 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 2.113838 # IPC: Total IPC of All Threads
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system.cpu.fp_regfile_writes 54 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.icache.replacements 41 # number of replacements
-system.cpu.icache.tagsinuse 825.582407 # Cycle average of tags in use
-system.cpu.icache.total_refs 65533545 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 979 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 66939.269663 # Average number of references to valid blocks.
+system.cpu.icache.replacements 39 # number of replacements
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+system.cpu.icache.avg_refs 67485.542739 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 825.582407 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.403116 # Average percentage of cache occupancy
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-system.cpu.icache.overall_misses::total 1386 # number of overall misses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::total 53782.106782 # average ReadReq miss latency
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-system.cpu.icache.overall_avg_miss_latency::total 53782.106782 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 93 # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52494.938539 # average ReadReq miss latency
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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+system.cpu.icache.overall_mshr_miss_latency::total 54205000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses
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+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006452 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.003105 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.003105 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12816.443331 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12816.443331 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16121.301810 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16121.301810 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14625.897456 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 14625.897456 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14625.897456 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 14625.897456 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 164572262000 # Number of ticks simulated
final_tick 164572262000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 164809 # Simulator instruction rate (inst/s)
-host_op_rate 174150 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47579904 # Simulator tick rate (ticks/s)
-host_mem_usage 241928 # Number of bytes of host memory used
-host_seconds 3458.86 # Real time elapsed on the host
+host_inst_rate 185108 # Simulator instruction rate (inst/s)
+host_op_rate 195599 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 53440170 # Simulator tick rate (ticks/s)
+host_mem_usage 241944 # Number of bytes of host memory used
+host_seconds 3079.56 # Real time elapsed on the host
sim_insts 570051585 # Number of instructions simulated
sim_ops 602359791 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 47424 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 27336 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 2538 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 2538 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 14742 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 3442 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 8340 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 71 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 921366434 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 1672075184 # Sum of mem lat for all requests
+system.physmem.totQLat 921339250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 1672034250 # Sum of mem lat for all requests
system.physmem.totBusLat 136675000 # Total cycles spent in databus access
-system.physmem.totBankLat 614033750 # Total cycles spent in bank access
-system.physmem.avgQLat 33705.24 # Average queueing delay per request
-system.physmem.avgBankLat 22462.46 # Average bank access latency per request
+system.physmem.totBankLat 614020000 # Total cycles spent in bank access
+system.physmem.avgQLat 33704.25 # Average queueing delay per request
+system.physmem.avgBankLat 22461.95 # Average bank access latency per request
system.physmem.avgBusLat 4999.82 # Average bus latency per request
-system.physmem.avgMemAccLat 61167.51 # Average memory access latency
+system.physmem.avgMemAccLat 61166.02 # Average memory access latency
system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s
system.cpu.iq.issued_per_cycle::stdev 1.722204 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 68107234 20.75% 20.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 85141417 25.94% 46.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 76162034 23.21% 69.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 40819071 12.44% 82.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 85141419 25.94% 46.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 76162032 23.21% 69.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 40819070 12.44% 82.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 28853170 8.79% 91.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 14914630 4.54% 95.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 14914631 4.54% 95.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 5559324 1.69% 97.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 6732498 2.05% 99.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1901914 0.58% 100.00% # Number of insts issued each cycle
system.cpu.l2cache.overall_misses::cpu.data 26602 # number of overall misses
system.cpu.l2cache.overall_misses::total 27345 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 40442500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 687360500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 727803000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1581776500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1581776500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 40442500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 2269137000 # number of demand (read+write) miss cycles
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-system.cpu.l2cache.overall_miss_latency::total 2309579500 # number of overall miss cycles
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 831 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 197598 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 198429 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.data 0.059811 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.061367 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54431.359354 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 142872.687591 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 131041.231545 # average ReadReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72588.522785 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72588.522785 # average ReadExReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85299.488760 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 741 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 26595 # number of overall MSHR misses
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024312 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027945 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059795 # mshr miss rate for overall accesses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42037.353576 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 130705.969192 # average ReadReq mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72868.683850 # average overall mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 440669 # number of replacements
system.cpu.dcache.tagsinuse 4091.484070 # Cycle average of tags in use
system.cpu.dcache.demand_misses::total 3718210 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3718210 # number of overall misses
system.cpu.dcache.overall_misses::total 3718210 # number of overall misses
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 40705228766 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 40705228766 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 337500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 337500 # number of LoadLockedReq miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 131865640 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 131865640 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_miss_rate::total 0.018473 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::total 0.018473 # miss rate for overall accesses
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12056.196805 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 12056.196805 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15340.909091 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15340.909091 # average LoadLockedReq miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 148065 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 30 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 4947 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 444768 # number of demand (read+write) MSHR misses
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system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096422821 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096422821 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6932840321 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6932840321 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6932840321 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6932840321 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6932827321 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6932827321 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6932827321 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6932827321 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003561 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14354.412219 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14354.412219 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14354.346429 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14354.346429 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16573.368104 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16573.368104 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15587.542991 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 15587.542991 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15587.542991 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 15587.542991 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15587.513762 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 15587.513762 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15587.513762 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 15587.513762 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.387316 # Number of seconds simulated
-sim_ticks 387315507500 # Number of ticks simulated
-final_tick 387315507500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.387321 # Number of seconds simulated
+sim_ticks 387320726500 # Number of ticks simulated
+final_tick 387320726500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 183094 # Simulator instruction rate (inst/s)
-host_op_rate 183671 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 50610731 # Simulator tick rate (ticks/s)
-host_mem_usage 233664 # Number of bytes of host memory used
-host_seconds 7652.83 # Real time elapsed on the host
+host_inst_rate 176162 # Simulator instruction rate (inst/s)
+host_op_rate 176717 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 48695201 # Simulator tick rate (ticks/s)
+host_mem_usage 235496 # Number of bytes of host memory used
+host_seconds 7953.98 # Real time elapsed on the host
sim_insts 1401188945 # Number of instructions simulated
sim_ops 1405604139 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 76544 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1678528 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1755072 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 76544 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 76544 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 76480 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1678784 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1755264 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 76480 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 76480 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory
system.physmem.bytes_written::total 162112 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1196 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 26227 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 27423 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 1195 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 26231 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 27426 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 197627 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 4333749 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4531375 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 197627 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 197627 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 418553 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 418553 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 418553 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 197627 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4333749 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4949928 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 27424 # Total number of read requests seen
+system.physmem.bw_read::cpu.inst 197459 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 4334351 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4531810 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 197459 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 197459 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 418547 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 418547 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 418547 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 197459 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4334351 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4950357 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 27427 # Total number of read requests seen
system.physmem.writeReqs 2533 # Total number of write requests seen
-system.physmem.cpureqs 29957 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 1755072 # Total number of bytes read from memory
+system.physmem.cpureqs 29960 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1755264 # Total number of bytes read from memory
system.physmem.bytesWritten 162112 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 1755072 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 1755264 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 1660 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 1716 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 1723 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 1744 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 1743 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 1702 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1707 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1721 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 1697 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 1767 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1768 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 1765 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 1769 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1770 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1755 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 1736 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 1673 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 1661 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1676 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1660 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 1628 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 157 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 155 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 153 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 387315479500 # Total gap between requests
+system.physmem.totGap 387320698500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 27424 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 2533 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 7981 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 13392 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 5076 # What read queue length does an incoming req see
+system.physmem.readPktSize::6 27427 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 2533 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 7983 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 13387 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 5082 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 974 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 88 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 713274952 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 1439334952 # Sum of mem lat for all requests
-system.physmem.totBusLat 137120000 # Total cycles spent in databus access
-system.physmem.totBankLat 588940000 # Total cycles spent in bank access
-system.physmem.avgQLat 26009.15 # Average queueing delay per request
-system.physmem.avgBankLat 21475.35 # Average bank access latency per request
+system.physmem.totQLat 712904000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 1439226500 # Sum of mem lat for all requests
+system.physmem.totBusLat 137135000 # Total cycles spent in databus access
+system.physmem.totBankLat 589187500 # Total cycles spent in bank access
+system.physmem.avgQLat 25992.78 # Average queueing delay per request
+system.physmem.avgBankLat 21482.03 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 52484.50 # Average memory access latency
+system.physmem.avgMemAccLat 52474.81 # Average memory access latency
system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 16.51 # Average write queue length over time
-system.physmem.readRowHits 17585 # Number of row buffer hits during reads
+system.physmem.avgWrQLen 16.63 # Average write queue length over time
+system.physmem.readRowHits 17586 # Number of row buffer hits during reads
system.physmem.writeRowHits 1048 # Number of row buffer hits during writes
system.physmem.readRowHitRate 64.12 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 41.37 # Row buffer hit rate for writes
-system.physmem.avgGap 12929047.62 # Average gap between requests
-system.cpu.branchPred.lookups 97759655 # Number of BP lookups
-system.cpu.branchPred.condPredicted 88050231 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 3614520 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 65786552 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 65492883 # Number of BTB hits
+system.physmem.avgGap 12927927.19 # Average gap between requests
+system.cpu.branchPred.lookups 97754812 # Number of BP lookups
+system.cpu.branchPred.condPredicted 88045070 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 3614513 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 65790839 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 65487235 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.553603 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1341 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 221 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 99.538531 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1327 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 219 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 49 # Number of system calls
-system.cpu.numCycles 774631016 # number of cpu cycles simulated
+system.cpu.numCycles 774641454 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 164855721 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1642251558 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 97759655 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 65494224 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 329204399 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 20834739 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 263342259 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 64 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 2502 # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles 164855086 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1642226882 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 97754812 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 65488562 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 329193327 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 20835132 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 263364086 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 66 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 2508 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 161937023 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 736247 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 774398184 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.126696 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.146676 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 161933823 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 733897 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 774407665 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.126639 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.146663 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 445193785 57.49% 57.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 74062525 9.56% 67.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 37899229 4.89% 71.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 9077552 1.17% 73.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 28106227 3.63% 76.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 18772117 2.42% 79.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 11485912 1.48% 80.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 3791430 0.49% 81.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 146009407 18.85% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 445214338 57.49% 57.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 74055584 9.56% 67.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 37896707 4.89% 71.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 9077649 1.17% 73.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 28106182 3.63% 76.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 18772378 2.42% 79.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 11485240 1.48% 80.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 3791473 0.49% 81.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 146008114 18.85% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 774398184 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.126202 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.120044 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 215922553 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 214452390 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 284209898 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 42820116 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 16993227 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 1636550752 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 16993227 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 239771948 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36701097 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 52424917 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 302039391 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 126467604 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 1625687860 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 146 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 30927407 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 73464560 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 3152152 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 1356365192 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 2746429093 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 2712307786 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 34121307 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 774407665 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.126194 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.119983 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 215996576 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 214396476 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 284196048 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 42825985 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 16992580 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 1636523781 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 16992580 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 239852916 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36748965 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 52423247 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 302028125 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 126361832 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 1625670094 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 144 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 30926636 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 73309992 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 3198488 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 1356344294 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 2746400105 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 2712277962 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 34122143 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 111594753 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2643851 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2663506 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 271777312 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 436941235 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 179754378 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 254555015 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 82904621 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1512542697 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2609193 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1459339312 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 53583 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 109245499 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 130204517 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 365522 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 774398184 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.884482 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.431065 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 111573855 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2642593 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2663144 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 271720784 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 436941817 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 179749373 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 254480906 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 83188791 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1512511277 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2608080 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1459319933 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 52996 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 109213691 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 130186216 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 364409 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 774407665 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.884434 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.431122 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 145558409 18.80% 18.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 184658706 23.85% 42.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 209828049 27.10% 69.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 131187469 16.94% 86.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 70686123 9.13% 95.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 20416273 2.64% 98.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 7987184 1.03% 99.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3894628 0.50% 99.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 181343 0.02% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 145648239 18.81% 18.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 184522685 23.83% 42.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 209864984 27.10% 69.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 131209019 16.94% 86.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 70693972 9.13% 95.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 20392101 2.63% 98.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8014841 1.03% 99.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3879808 0.50% 99.98% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 774398184 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 774407665 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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-system.cpu.iq.fu_full::IntMult 0 0.00% 7.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 7.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 95273 5.64% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1158517 68.57% 81.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 316903 18.76% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 140362 8.20% 8.20% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1159729 67.79% 81.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 315506 18.44% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 866474644 59.37% 59.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 866449380 59.37% 59.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2644797 0.18% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 419098125 28.72% 88.27% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 171121746 11.73% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2644870 0.18% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 419102646 28.72% 88.27% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 171123037 11.73% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1459339312 # Type of FU issued
-system.cpu.iq.rate 1.883915 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1689639 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001158 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 3676979008 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 1615425319 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1443226704 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 17841022 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 9210458 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 8545776 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1451900530 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 9128421 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 215265115 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1459319933 # Type of FU issued
+system.cpu.iq.rate 1.883865 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1710827 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001172 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 3676966203 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 1615362108 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1443197913 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 17845151 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 9210352 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 8546882 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1451899562 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 9131198 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 215327027 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 34428392 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 58884 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 245184 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 12906236 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 34428974 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 58580 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 245871 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 12901231 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 3305 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 101102 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 3337 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 100836 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 16993227 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 3018866 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 247688 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1608835504 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 4126277 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 436941235 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 179754378 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2526244 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 149012 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1899 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 245184 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 2269311 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1473063 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 3742374 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1454021381 # Number of executed instructions
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+system.cpu.iew.iewUnblockCycles 247748 # Number of cycles IEW is unblocking
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system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 93683614 # number of nop insts executed
-system.cpu.iew.exec_refs 586997386 # number of memory reference insts executed
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-system.cpu.iew.exec_rate 1.877050 # Inst execution rate
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-system.cpu.iew.wb_consumers 1204682131 # num instructions consuming a value
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.874147 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.957454 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.874086 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.957459 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
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-system.cpu.commit.committed_per_cycle::0 239974569 31.68% 31.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 275852046 36.42% 68.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 42571811 5.62% 73.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 54691782 7.22% 80.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 19624283 2.59% 83.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 13282059 1.75% 85.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 30580381 4.04% 89.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 10561653 1.39% 90.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 70266373 9.28% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 240000251 31.69% 31.69% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::3 54725654 7.23% 80.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 19677570 2.60% 83.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 13283245 1.75% 85.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 30556171 4.03% 89.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 10517669 1.39% 90.72% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.committedInsts 1485108088 # Number of instructions committed
system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions.
system.cpu.commit.function_calls 1206914 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 70266373 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 70291137 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2295813886 # The number of ROB reads
-system.cpu.rob.rob_writes 3234496299 # The number of ROB writes
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-system.cpu.idleCycles 232832 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 2295766308 # The number of ROB reads
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+system.cpu.idleCycles 233789 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1401188945 # Number of Instructions Simulated
system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated
-system.cpu.cpi 0.552838 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.552838 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.808847 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.808847 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1979103244 # number of integer regfile reads
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system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses
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system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses
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+system.cpu.l2cache.overall_mshr_miss_rate::total 0.059026 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37460.907191 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 87749.861898 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77089.530486 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60519.824007 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60519.824007 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37460.907191 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65135.155046 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63928.373391 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37460.907191 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65135.155046 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63928.373391 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 459190 # number of replacements
-system.cpu.dcache.tagsinuse 4093.797590 # Cycle average of tags in use
-system.cpu.dcache.total_refs 365198263 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 463286 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 788.278219 # Average number of references to valid blocks.
+system.cpu.dcache.replacements 459222 # number of replacements
+system.cpu.dcache.tagsinuse 4093.797620 # Cycle average of tags in use
+system.cpu.dcache.total_refs 365142346 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 463318 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 788.103087 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 340173000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4093.797590 # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data 4093.797620 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999462 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999462 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 200241495 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 200241495 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 164955449 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 164955449 # number of WriteReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data 200185442 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 200185442 # number of ReadReq hits
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system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data 365196944 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 365196944 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 365196944 # number of overall hits
-system.cpu.dcache.overall_hits::total 365196944 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 923055 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 923055 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1891367 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1891367 # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data 365141027 # number of demand (read+write) hits
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+system.cpu.dcache.overall_hits::total 365141027 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 923072 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 923072 # number of ReadReq misses
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system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses
system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses
-system.cpu.dcache.demand_misses::cpu.data 2814422 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2814422 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2814422 # number of overall misses
-system.cpu.dcache.overall_misses::total 2814422 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 14739603500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 14739603500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 31907348686 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 31907348686 # number of WriteReq miss cycles
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+system.cpu.dcache.demand_misses::total 2814303 # number of demand (read+write) misses
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+system.cpu.dcache.overall_misses::total 2814303 # number of overall misses
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+system.cpu.dcache.ReadReq_miss_latency::total 14740246000 # number of ReadReq miss cycles
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+system.cpu.dcache.WriteReq_miss_latency::total 31916028682 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 150000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 150000 # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 46646952186 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 46646952186 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 46646952186 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 46646952186 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 201164550 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 201164550 # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.demand_miss_latency::total 46656274682 # number of demand (read+write) miss cycles
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+system.cpu.dcache.overall_miss_latency::total 46656274682 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 201108514 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 368011366 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 368011366 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 368011366 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 368011366 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004589 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.004589 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011336 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.011336 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 367955330 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 367955330 # number of demand (read+write) accesses
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+system.cpu.dcache.overall_accesses::total 367955330 # number of overall (read+write) accesses
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+system.cpu.dcache.ReadReq_miss_rate::total 0.004590 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011335 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.011335 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.007648 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.007648 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.007648 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.007648 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15968.283038 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15968.283038 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16869.993336 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 16869.993336 # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15968.685000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15968.685000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16875.796073 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 16875.796073 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 21428.571429 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 21428.571429 # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16574.256521 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 16574.256521 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16574.256521 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16574.256521 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 590116 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 5 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 35661 # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 16578.269888 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 16578.269888 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16578.269888 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16578.269888 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 588860 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 17 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 35662 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.547938 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 5 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.512254 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 443933 # number of writebacks
-system.cpu.dcache.writebacks::total 443933 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722205 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 722205 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628938 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1628938 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 2351143 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 2351143 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 2351143 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 2351143 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200850 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 200850 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262429 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 262429 # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks 443982 # number of writebacks
+system.cpu.dcache.writebacks::total 443982 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722195 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 722195 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628797 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1628797 # number of WriteReq MSHR hits
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+system.cpu.dcache.demand_mshr_hits::total 2350992 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2350992 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2350992 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200877 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 200877 # number of ReadReq MSHR misses
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+system.cpu.dcache.WriteReq_mshr_misses::total 262434 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 463279 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 463279 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 463279 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 463279 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2612152000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2612152000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4357934500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4357934500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data 463311 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 463311 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 463311 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 463311 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2613052500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2613052500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4357141500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4357141500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 136000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 136000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6970086500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6970086500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6970086500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6970086500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000998 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6970194000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6970194000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6970194000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6970194000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000999 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001573 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13005.486682 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13005.486682 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16606.146805 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16606.146805 # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13008.221449 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13008.221449 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16602.808706 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16602.808706 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 19428.571429 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 19428.571429 # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15045.116442 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 15045.116442 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15045.116442 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 15045.116442 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15044.309330 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 15044.309330 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15044.309330 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 15044.309330 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 607292111000 # Number of ticks simulated
final_tick 607292111000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 91190 # Simulator instruction rate (inst/s)
-host_op_rate 168022 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 62928697 # Simulator tick rate (ticks/s)
-host_mem_usage 248736 # Number of bytes of host memory used
-host_seconds 9650.48 # Real time elapsed on the host
+host_inst_rate 88731 # Simulator instruction rate (inst/s)
+host_op_rate 163492 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 61232046 # Simulator tick rate (ticks/s)
+host_mem_usage 248756 # Number of bytes of host memory used
+host_seconds 9917.88 # Real time elapsed on the host
sim_insts 880025277 # Number of instructions simulated
sim_ops 1621493926 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 57664 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 27359 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 2534 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 2534 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 26892 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 100 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 90448613 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 895548613 # Sum of mem lat for all requests
+system.physmem.totQLat 90421500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 895535250 # Sum of mem lat for all requests
system.physmem.totBusLat 136795000 # Total cycles spent in databus access
-system.physmem.totBankLat 668305000 # Total cycles spent in bank access
-system.physmem.avgQLat 3305.99 # Average queueing delay per request
-system.physmem.avgBankLat 24427.25 # Average bank access latency per request
+system.physmem.totBankLat 668318750 # Total cycles spent in bank access
+system.physmem.avgQLat 3305.00 # Average queueing delay per request
+system.physmem.avgBankLat 24427.75 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 32733.24 # Average memory access latency
+system.physmem.avgMemAccLat 32732.75 # Average memory access latency
system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s
system.cpu.fetch.rateDist::total 1214221440 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.130483 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.200203 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 288175293 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 497913619 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 274106217 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 92482436 # Number of cycles decode is unblocking
+system.cpu.decode.IdleCycles 288175297 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 497913615 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 274106209 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 92482444 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 61543875 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2343534245 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 61543875 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 336850045 # Number of cycles rename is idle
+system.cpu.rename.IdleCycles 336850046 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 124204658 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 2567 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 303948664 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 387671631 # Number of cycles rename is unblocking
+system.cpu.rename.RunCycles 303948666 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 387671628 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2247678746 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 360 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 242705543 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 120202916 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.IQFullEvents 242705531 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 120202926 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2618040036 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 5722358621 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 5722353197 # Number of integer rename lookups
system.cpu.rename.UndoneMaps 731144778 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 87 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 731406447 # count of insts added to the skid buffer
+system.cpu.rename.skidInsts 731406444 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 531670409 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 219217246 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 342048419 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 144614488 # Number of conflicting stores.
+system.cpu.memDep0.conflictingStores 144614487 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1993488562 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 286 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1783952231 # Number of instructions issued
system.cpu.iq.issued_per_cycle::mean 1.469215 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.421905 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 360233763 29.67% 29.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 364161192 29.99% 59.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 234288879 19.30% 78.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 141409866 11.65% 90.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 60623194 4.99% 95.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 39782569 3.28% 98.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 360233765 29.67% 29.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 364161190 29.99% 59.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 234288875 19.30% 78.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 141409873 11.65% 90.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 60623190 4.99% 95.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 39782570 3.28% 98.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 11078669 0.91% 99.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 2040416 0.17% 99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 602892 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.fp_inst_queue_wakeup_accesses 123 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1740037802 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 245 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 210029942 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 210029946 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 112628288 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 39424 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.exec_rate 1.454114 # Inst execution rate
system.cpu.iew.wb_sent 1725748007 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1724635217 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1267063012 # num instructions producing a value
-system.cpu.iew.wb_consumers 1828799696 # num instructions consuming a value
+system.cpu.iew.wb_producers 1267063011 # num instructions producing a value
+system.cpu.iew.wb_consumers 1828799692 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.419939 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.692839 # average fanout of values written-back
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46268500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 330234500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 376503000 # number of ReadReq miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.inst 46268500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 1465205500 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.inst 46268500 # number of overall miss cycles
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-system.cpu.l2cache.overall_miss_latency::total 1511474000 # number of overall miss cycles
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 918 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 203811 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 204729 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51352.386238 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72403.968428 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68931.343830 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51832.260127 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51832.260127 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51832.853816 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51832.853816 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51352.386238 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55378.543352 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51352.386238 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55378.543352 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 901 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 26458 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 27359 # number of overall MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 273211469 # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.demand_mshr_miss_latency::total 1170893240 # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1135810025 # number of overall MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.981481 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022379 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026679 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981481 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058772 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.060649 # mshr miss rate for overall accesses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59901.659504 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56443.552545 # average ReadReq mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42928.793749 # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42928.793749 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42797.369787 # average overall mshr miss latency
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59900.683184 # average ReadReq mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 446086 # number of replacements
system.cpu.dcache.tagsinuse 4092.713768 # Cycle average of tags in use
-system.cpu.dcache.total_refs 452307982 # Total number of references to valid blocks.
+system.cpu.dcache.total_refs 452307978 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 450182 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 1004.722494 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 1004.722486 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 861652000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4092.713768 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999198 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999198 # Average percentage of cache occupancy
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system.cpu.dcache.WriteReq_hits::total 187939603 # number of WriteReq hits
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system.cpu.dcache.ReadReq_misses::total 211281 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 246455 # number of WriteReq misses
system.cpu.dcache.overall_misses::total 457736 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3022618500 # number of ReadReq miss cycles
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-system.cpu.dcache.overall_accesses::cpu.data 452765711 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 452765711 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 452765707 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 452765707 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 452765707 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 452765707 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000799 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000799 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001310 # miss rate for WriteReq accesses
system.cpu.dcache.overall_miss_rate::total 0.001011 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14306.153890 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14306.153890 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16716.055669 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 16716.055669 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 15603.697328 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 15603.697328 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15603.697328 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15603.697328 # average overall miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16716.108417 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 16716.108417 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15603.725728 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 15603.725728 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15603.725728 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15603.725728 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 365 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 40 # number of cycles access was blocked
system.cpu.dcache.overall_mshr_misses::total 450191 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2528414500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2528414500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3626209000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3626209000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6154623500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6154623500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6154623500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6154623500 # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3626222000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3626222000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6154636500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6154636500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6154636500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6154636500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12405.317025 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12405.317025 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14718.310374 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14718.310374 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13671.138472 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13671.138472 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13671.138472 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13671.138472 # average overall mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14718.363139 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14718.363139 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13671.167349 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13671.167349 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13671.167349 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13671.167349 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.026779 # Number of seconds simulated
-sim_ticks 26779468500 # Number of ticks simulated
-final_tick 26779468500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.026786 # Number of seconds simulated
+sim_ticks 26785824500 # Number of ticks simulated
+final_tick 26785824500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 196675 # Simulator instruction rate (inst/s)
-host_op_rate 198087 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 58139571 # Simulator tick rate (ticks/s)
-host_mem_usage 373976 # Number of bytes of host memory used
-host_seconds 460.61 # Real time elapsed on the host
+host_inst_rate 121944 # Simulator instruction rate (inst/s)
+host_op_rate 122819 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 36056613 # Simulator tick rate (ticks/s)
+host_mem_usage 374016 # Number of bytes of host memory used
+host_seconds 742.88 # Real time elapsed on the host
sim_insts 90589798 # Number of instructions simulated
sim_ops 91240351 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 947840 # Number of bytes read from this memory
-system.physmem.bytes_read::total 993088 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 992832 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 44992 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 44992 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 703 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14810 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15517 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1689653 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 35394280 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 37083932 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1689653 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1689653 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1689653 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 35394280 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 37083932 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15517 # Total number of read requests seen
+system.physmem.num_reads::total 15513 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1679694 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 35385881 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 37065575 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1679694 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1679694 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1679694 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 35385881 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 37065575 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15513 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 15520 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 993088 # Total number of bytes read from memory
+system.physmem.cpureqs 15516 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 992832 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 993088 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 992832 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 997 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 996 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 960 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 997 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1012 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 996 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1013 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 926 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 925 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 882 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 885 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 951 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 993 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 992 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1001 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 966 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 968 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 968 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 1002 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 1001 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 26779289500 # Total gap between requests
+system.physmem.totGap 26785652500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 15517 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 0 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 3 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 10168 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 5067 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 252 # What read queue length does an incoming req see
+system.physmem.readPktSize::6 15513 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 0 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 10163 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 5065 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 255 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 52084984 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 311719984 # Sum of mem lat for all requests
-system.physmem.totBusLat 77585000 # Total cycles spent in databus access
-system.physmem.totBankLat 182050000 # Total cycles spent in bank access
-system.physmem.avgQLat 3356.64 # Average queueing delay per request
-system.physmem.avgBankLat 11732.29 # Average bank access latency per request
+system.physmem.totQLat 55611750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 315006750 # Sum of mem lat for all requests
+system.physmem.totBusLat 77565000 # Total cycles spent in databus access
+system.physmem.totBankLat 181830000 # Total cycles spent in bank access
+system.physmem.avgQLat 3584.85 # Average queueing delay per request
+system.physmem.avgBankLat 11721.14 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 20088.93 # Average memory access latency
-system.physmem.avgRdBW 37.08 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 20305.99 # Average memory access latency
+system.physmem.avgRdBW 37.07 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 37.08 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 37.07 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.29 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 14783 # Number of row buffer hits during reads
+system.physmem.readRowHits 14781 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 95.27 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 95.28 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 1725803.28 # Average gap between requests
-system.cpu.branchPred.lookups 26678818 # Number of BP lookups
-system.cpu.branchPred.condPredicted 21998913 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 842318 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 11366409 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 11281153 # Number of BTB hits
+system.physmem.avgGap 1726658.45 # Average gap between requests
+system.cpu.branchPred.lookups 26682480 # Number of BP lookups
+system.cpu.branchPred.condPredicted 22002618 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 841998 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 11368270 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 11282813 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.249930 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 69723 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 201 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 99.248285 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 69658 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 194 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
-system.cpu.numCycles 53558938 # number of cpu cycles simulated
+system.cpu.numCycles 53571650 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 14172731 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 127871641 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 26678818 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 11350876 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 24033181 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4760167 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 11226793 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 14170612 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 127882618 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 26682480 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 11352471 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 24034762 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4762849 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 11235788 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13844867 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 331224 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 53334396 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.414044 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.215935 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 13843090 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 329835 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 53345786 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.413719 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.215837 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 29339451 55.01% 55.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3389540 6.36% 61.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2028066 3.80% 65.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1555662 2.92% 68.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1667100 3.13% 71.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2918330 5.47% 76.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1510510 2.83% 79.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1090066 2.04% 81.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9835671 18.44% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 29349323 55.02% 55.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 3389433 6.35% 61.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2028287 3.80% 65.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1555177 2.92% 68.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1667492 3.13% 71.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2918592 5.47% 76.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1510888 2.83% 79.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1090794 2.04% 81.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 9835800 18.44% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 53334396 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.498121 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.387494 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 16935376 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 9075535 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 22432463 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 998016 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3893006 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4442432 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 8659 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 126044255 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 42607 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3893006 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 18714710 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 3545279 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 156066 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 21549370 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5475965 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 123134352 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 422701 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4592939 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 1259 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 143588919 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 536358187 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 536353466 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 4721 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 53345786 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.498071 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.387132 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 16933018 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 9083258 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 22434897 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 998703 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3895910 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 4442085 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 8696 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 126062223 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 42630 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3895910 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 18712984 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 3548131 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 156179 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 21551652 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 5480930 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 123149853 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 423091 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4597179 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 1286 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 143608098 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 536423645 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 536418417 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 5228 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 36174733 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 4601 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 4599 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12509318 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29470006 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 5522308 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2104178 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1264650 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 118149095 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 8470 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 105144375 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 78107 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 26722736 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 65554797 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 252 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 53334396 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.971418 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.910922 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 36193912 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 4607 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 4605 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12518412 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 29475899 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 5522776 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 2125822 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1253238 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 118167784 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 8472 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 105151160 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 77497 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 26739027 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 65605268 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 254 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 53345786 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.971124 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.910487 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 15312252 28.71% 28.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 11634281 21.81% 50.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 8274633 15.51% 66.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6753758 12.66% 78.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4949297 9.28% 87.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2972831 5.57% 93.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2466224 4.62% 98.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 528093 0.99% 99.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 443027 0.83% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 15316861 28.71% 28.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 11639595 21.82% 50.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 8263506 15.49% 66.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 6760248 12.67% 78.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4974624 9.33% 88.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2955128 5.54% 93.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 2464546 4.62% 98.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 527827 0.99% 99.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 443451 0.83% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 53334396 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 53345786 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 44474 6.73% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 27 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 340155 51.46% 58.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 276363 41.81% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 44563 6.73% 6.73% # attempts to use FU when none available
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+system.cpu.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 340033 51.38% 58.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 277229 41.89% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 74414194 70.77% 70.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 10982 0.01% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 3 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 143 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 186 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 25601639 24.35% 95.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 5117225 4.87% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 74420309 70.77% 70.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 10977 0.01% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 155 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 201 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 25602989 24.35% 95.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 5116524 4.87% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 105144375 # Type of FU issued
-system.cpu.iq.rate 1.963153 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 661019 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006287 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 264361545 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 144884747 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 102673470 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 727 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1011 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 322 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 105805031 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 363 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 444404 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 105151160 # Type of FU issued
+system.cpu.iq.rate 1.962814 # Inst issue rate
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+system.cpu.iq.fu_busy_rate 0.006294 # FU busy rate (busy events/executed inst)
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+system.cpu.iq.int_inst_queue_writes 144919691 # Number of integer instruction queue writes
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+system.cpu.iq.fp_inst_queue_writes 1077 # Number of floating instruction queue writes
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+system.cpu.iq.int_alu_accesses 105812622 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 390 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 6896040 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6651 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 6197 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 777464 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 6901933 # Number of loads squashed
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+system.cpu.iew.lsq.thread0.squashedStores 777932 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 31327 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 31373 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3893006 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 929576 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 127351 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 118170277 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 309597 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29470006 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 5522308 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 4582 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 66448 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 6858 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 6197 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 446675 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 445546 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 892221 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 104166430 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25281924 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 977945 # Number of squashed instructions skipped in execute
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+system.cpu.iew.iewUnblockCycles 127070 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 118188976 # Number of instructions dispatched to IQ
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+system.cpu.iew.iewIQFullEvents 66075 # Number of times the IQ has become full, causing a stall
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+system.cpu.iew.predictedTakenIncorrect 446439 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 445443 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 891882 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 104175676 # Number of executed instructions
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system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 12712 # number of nop insts executed
-system.cpu.iew.exec_refs 30342174 # number of memory reference insts executed
-system.cpu.iew.exec_branches 21323986 # Number of branches executed
-system.cpu.iew.exec_stores 5060250 # Number of stores executed
-system.cpu.iew.exec_rate 1.944893 # Inst execution rate
-system.cpu.iew.wb_sent 102951824 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 102673792 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 62219945 # num instructions producing a value
-system.cpu.iew.wb_consumers 104261628 # num instructions consuming a value
+system.cpu.iew.exec_nop 12720 # number of nop insts executed
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+system.cpu.iew.wb_sent 102960011 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 102682964 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 62233069 # num instructions producing a value
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.917024 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.596767 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.916741 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.596772 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 26920302 # The number of squashed insts skipped by commit
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system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 833747 # The number of times a branch was mispredicted
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-system.cpu.commit.committed_per_cycle::mean 1.845680 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.541256 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 19945415 40.34% 40.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13149428 26.60% 66.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4162611 8.42% 75.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 3435070 6.95% 82.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1540295 3.12% 85.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 748484 1.51% 86.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 932633 1.89% 88.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 245930 0.50% 89.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5281524 10.68% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 19967148 40.38% 40.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13135707 26.56% 66.94% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::3 3434332 6.95% 82.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1535763 3.11% 85.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 744463 1.51% 86.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 942034 1.91% 88.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 246412 0.50% 89.32% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.committedInsts 90602407 # Number of instructions committed
system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
system.cpu.commit.int_insts 72525674 # Number of committed integer instructions.
system.cpu.commit.function_calls 56148 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5281524 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5280628 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 162327394 # The number of ROB reads
-system.cpu.rob.rob_writes 240259263 # The number of ROB writes
-system.cpu.timesIdled 43763 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 224542 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 162355527 # The number of ROB reads
+system.cpu.rob.rob_writes 240299704 # The number of ROB writes
+system.cpu.timesIdled 43654 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 225864 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 90589798 # Number of Instructions Simulated
system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated
-system.cpu.cpi 0.591225 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.591225 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.691404 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.691404 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 495495273 # number of integer regfile reads
-system.cpu.int_regfile_writes 120530797 # number of integer regfile writes
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-system.cpu.misc_regfile_reads 29088840 # number of misc regfile reads
+system.cpu.cpi 0.591365 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.591365 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.691003 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.691003 # IPC: Total IPC of All Threads
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system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
system.cpu.icache.replacements 3 # number of replacements
-system.cpu.icache.tagsinuse 630.551988 # Cycle average of tags in use
-system.cpu.icache.total_refs 13843878 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 733 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 18886.600273 # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 630.397373 # Cycle average of tags in use
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+system.cpu.icache.avg_refs 19013.881868 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50237.347166 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 50237.347166 # average ReadReq miss latency
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-system.cpu.icache.overall_avg_miss_latency::cpu.inst 50237.347166 # average overall miss latency
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50287.384537 # average ReadReq miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 50287.384537 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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-system.cpu.icache.ReadReq_mshr_misses::total 737 # number of ReadReq MSHR misses
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-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032124 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.032124 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032124 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.032124 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.656042 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.656042 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22505.368666 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22505.368666 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11577.389525 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11577.389525 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11577.389525 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11577.389525 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032120 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.032120 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032120 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.032120 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.590241 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.590241 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22582.615238 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22582.615238 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11580.878438 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11580.878438 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11580.878438 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11580.878438 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.066005 # Number of seconds simulated
-sim_ticks 66004575000 # Number of ticks simulated
-final_tick 66004575000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.066022 # Number of seconds simulated
+sim_ticks 66021796500 # Number of ticks simulated
+final_tick 66021796500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 124260 # Simulator instruction rate (inst/s)
-host_op_rate 218802 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 51913433 # Simulator tick rate (ticks/s)
-host_mem_usage 384868 # Number of bytes of host memory used
-host_seconds 1271.44 # Real time elapsed on the host
+host_inst_rate 92381 # Simulator instruction rate (inst/s)
+host_op_rate 162668 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 38604948 # Simulator tick rate (ticks/s)
+host_mem_usage 384888 # Number of bytes of host memory used
+host_seconds 1710.19 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
sim_ops 278192463 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 65088 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1882560 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1947648 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 65088 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 65088 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 10816 # Number of bytes written to this memory
-system.physmem.bytes_written::total 10816 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1017 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 29415 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 30432 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 169 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 169 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 986113 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 28521659 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 29507773 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 986113 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 986113 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 163867 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 163867 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 163867 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 986113 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 28521659 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 29671640 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 30434 # Total number of read requests seen
-system.physmem.writeReqs 169 # Total number of write requests seen
-system.physmem.cpureqs 30604 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 1947648 # Total number of bytes read from memory
-system.physmem.bytesWritten 10816 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 1947648 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 10816 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q
+system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1881664 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1946496 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9856 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9856 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 29401 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 30414 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 154 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 154 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 981979 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 28500648 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 29482627 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 981979 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 981979 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 149284 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 149284 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 149284 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 981979 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 28500648 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 29631911 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 30416 # Total number of read requests seen
+system.physmem.writeReqs 154 # Total number of write requests seen
+system.physmem.cpureqs 30571 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1946496 # Total number of bytes read from memory
+system.physmem.bytesWritten 9856 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 1946496 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 9856 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 46 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 1928 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 1909 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 1972 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 1959 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 1883 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 1865 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 1906 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1973 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 1961 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1879 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 1864 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1928 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 1952 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 1932 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 1937 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 1870 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 1874 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 1846 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 1891 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1931 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1939 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1872 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 1873 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1845 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1890 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 1830 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 1798 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 1799 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 6 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 61 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 46 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 14 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 39 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 2 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 7 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 3 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 1 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 5 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 6 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 9 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 9 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 8 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 6 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 5 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 3 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 13 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 66004558000 # Total gap between requests
+system.physmem.totGap 66021783500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 30434 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 169 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 1 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 29835 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 405 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see
+system.physmem.readPktSize::6 30416 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 154 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 29836 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 402 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 97 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 12335337 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 610214087 # Sum of mem lat for all requests
-system.physmem.totBusLat 151870000 # Total cycles spent in databus access
-system.physmem.totBankLat 446008750 # Total cycles spent in bank access
-system.physmem.avgQLat 406.11 # Average queueing delay per request
-system.physmem.avgBankLat 14683.90 # Average bank access latency per request
+system.physmem.totQLat 12785750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 610218250 # Sum of mem lat for all requests
+system.physmem.totBusLat 151850000 # Total cycles spent in databus access
+system.physmem.totBankLat 445582500 # Total cycles spent in bank access
+system.physmem.avgQLat 421.00 # Average queueing delay per request
+system.physmem.avgBankLat 14671.80 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 20090.01 # Average memory access latency
-system.physmem.avgRdBW 29.51 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 29.51 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 0.16 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 20092.80 # Average memory access latency
+system.physmem.avgRdBW 29.48 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 29.48 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.15 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.23 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 1.18 # Average write queue length over time
-system.physmem.readRowHits 29113 # Number of row buffer hits during reads
-system.physmem.writeRowHits 87 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 95.85 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 51.48 # Row buffer hit rate for writes
-system.physmem.avgGap 2156800.25 # Average gap between requests
-system.cpu.branchPred.lookups 34551755 # Number of BP lookups
-system.cpu.branchPred.condPredicted 34551755 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 910403 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 24766802 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 24665055 # Number of BTB hits
+system.physmem.avgWrQLen 1.30 # Average write queue length over time
+system.physmem.readRowHits 29116 # Number of row buffer hits during reads
+system.physmem.writeRowHits 69 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 95.87 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 44.81 # Row buffer hit rate for writes
+system.physmem.avgGap 2159691.97 # Average gap between requests
+system.cpu.branchPred.lookups 34555739 # Number of BP lookups
+system.cpu.branchPred.condPredicted 34555739 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 911751 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 24769004 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 24665056 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.589180 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 99.580330 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 444 # Number of system calls
-system.cpu.numCycles 132009151 # number of cpu cycles simulated
+system.cpu.numCycles 132043594 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 26590977 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 185543024 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 34551755 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 24665055 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 56499392 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6118358 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 43667810 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 138 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 25944504 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 189453 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 131930197 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.484743 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.326414 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 26598616 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 185589305 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 34555739 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 24665056 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 56508781 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6124933 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 43680261 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 134 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 25951098 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 190273 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 131964855 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.484572 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.326415 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 77978275 59.11% 59.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1995894 1.51% 60.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2955143 2.24% 62.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 3921314 2.97% 65.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 7795304 5.91% 71.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 4757842 3.61% 75.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2730359 2.07% 77.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1578596 1.20% 78.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 28217470 21.39% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 78003722 59.11% 59.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1996961 1.51% 60.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2955104 2.24% 62.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 3922098 2.97% 65.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 7793741 5.91% 71.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 4759235 3.61% 75.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2730671 2.07% 77.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1579089 1.20% 78.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 28224234 21.39% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 131930197 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.261738 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.405532 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 37427999 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 35920173 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 44744893 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 8665277 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 5171855 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 324565548 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 5171855 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 42969195 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 8593654 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 9092 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 47590664 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 27595737 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 320190802 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 211 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 56984 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 25724332 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 365 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 322194206 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 849198017 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 849196232 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1785 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 131964855 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.261699 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.405515 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 37438024 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 35931161 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 44761152 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 8657481 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 5177037 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 324625052 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 5177037 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 42998776 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 8560534 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 9611 # count of cycles rename stalled for serializing inst
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+system.cpu.rename.UnblockCycles 27625324 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 320243292 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 235 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 57194 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 25761475 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 370 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 322250586 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 849328812 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 849326947 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1865 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 279212745 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 42981461 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 43037841 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 469 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 463 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 62356862 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 102568377 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 35231338 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 39589479 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 6005074 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 315870239 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1674 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 302163622 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 115310 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 37046058 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 54286160 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1229 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 131930197 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.290329 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.700150 # Number of insts issued each cycle
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+system.cpu.iq.iqSquashedInstsExamined 37077809 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 54333314 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::2 25896464 19.63% 55.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 25797972 19.55% 75.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 18916380 14.34% 89.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 8292938 6.29% 96.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 4139203 3.14% 99.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 915627 0.69% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 163709 0.12% 100.00% # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::3 25803819 19.55% 75.42% # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::5 8297062 6.29% 96.05% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::total 131964855 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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-system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1820587 93.51% 95.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 87813 4.51% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 38351 1.96% 1.96% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1834339 93.53% 95.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 88449 4.51% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 31282 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 171146899 56.64% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 171161474 56.64% 56.65% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.65% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 35 0.00% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 56.65% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.65% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.65% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 97755630 32.35% 89.00% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 33229776 11.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 97761295 32.35% 89.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 33236158 11.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 302163622 # Type of FU issued
-system.cpu.iq.rate 2.288960 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1946893 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006443 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 738319072 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 352950108 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 299522625 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 572 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 867 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 162 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 304078975 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 258 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 53992768 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 302190238 # Type of FU issued
+system.cpu.iq.rate 2.288564 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1961139 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006490 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 738420696 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 353016005 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 299545946 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 543 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 861 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 304119846 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 249 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 53994204 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 11788993 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 26852 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 33996 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 3791586 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 11795289 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 26124 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 34117 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 3800744 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
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-system.cpu.iew.lsq.thread0.rescheduledLoads 3239 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 8506 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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-system.cpu.iew.iewBlockCycles 1763635 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 159728 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 315871913 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 195728 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 102568377 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 35231338 # Number of dispatched store instructions
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system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committedInsts 157988547 # Number of instructions committed
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system.cpu.commit.int_insts 278186172 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.committedInsts 157988547 # Number of Instructions Simulated
system.cpu.committedOps 278192463 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated
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-system.cpu.cpi_total 0.835562 # CPI: Total CPI of All Threads
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-system.cpu.ipc_total 1.196800 # IPC: Total IPC of All Threads
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system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38619.019802 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37873.248412 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 29727.315034 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 29727.315034 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37376.468043 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29845.396471 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30097.059079 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37376.468043 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29845.396471 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30097.059079 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 29729.903100 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 29729.903100 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37575.823297 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29852.040404 # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37575.823297 # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30109.279754 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 2072095 # number of replacements
-system.cpu.dcache.tagsinuse 4072.471954 # Cycle average of tags in use
-system.cpu.dcache.total_refs 71964033 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 2076191 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 34.661567 # Average number of references to valid blocks.
+system.cpu.dcache.replacements 2072027 # number of replacements
+system.cpu.dcache.tagsinuse 4072.478091 # Cycle average of tags in use
+system.cpu.dcache.total_refs 71969321 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 2076123 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 34.665249 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 21154875000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4072.471954 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.994256 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.994256 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 40622570 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 40622570 # number of ReadReq hits
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-system.cpu.dcache.WriteReq_hits::total 31341456 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 71964026 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 71964026 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 71964026 # number of overall hits
-system.cpu.dcache.overall_hits::total 71964026 # number of overall hits
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-system.cpu.dcache.ReadReq_misses::total 2625435 # number of ReadReq misses
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-system.cpu.dcache.demand_misses::total 2723731 # number of demand (read+write) misses
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-system.cpu.dcache.overall_misses::total 2723731 # number of overall misses
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-system.cpu.dcache.ReadReq_miss_latency::total 31317831000 # number of ReadReq miss cycles
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-system.cpu.dcache.WriteReq_miss_latency::total 2109058498 # number of WriteReq miss cycles
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-system.cpu.dcache.overall_miss_latency::total 33426889498 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 43248005 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 43248005 # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.occ_percent::total 0.994257 # Average percentage of cache occupancy
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system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses
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-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11928.625542 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11928.625542 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21456.198604 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 21456.198604 # average WriteReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 12272.463580 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12272.463580 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12272.463580 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 32211 # number of cycles access was blocked
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+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12272.867425 # average overall miss latency
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+system.cpu.dcache.blocked_cycles::no_mshrs 31969 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 9475 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.399578 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2066104 # number of writebacks
-system.cpu.dcache.writebacks::total 2066104 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631384 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 631384 # number of ReadReq MSHR hits
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-system.cpu.dcache.demand_mshr_hits::total 647536 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 647536 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 647536 # number of overall MSHR hits
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-system.cpu.dcache.WriteReq_mshr_misses::total 82144 # number of WriteReq MSHR misses
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-system.cpu.dcache.demand_mshr_misses::total 2076195 # number of demand (read+write) MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total 2076195 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21987856500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 21987856500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1833812998 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1833812998 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23821669498 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 23821669498 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23821669498 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 23821669498 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046107 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046107 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks 2066038 # number of writebacks
+system.cpu.dcache.writebacks::total 2066038 # number of writebacks
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+system.cpu.dcache.overall_mshr_miss_latency::total 23816149999 # number of overall MSHR miss cycles
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+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046100 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses
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-system.cpu.dcache.demand_mshr_miss_rate::total 0.027798 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027798 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.027798 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11026.727250 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11026.727250 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22324.369376 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22324.369376 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11473.714896 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11473.714896 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11473.714896 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11473.714896 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027795 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.027795 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027795 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.027795 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.295379 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.295379 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22324.923600 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22324.923600 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11471.432142 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11471.432142 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11471.432142 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11471.432142 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.434532 # Number of seconds simulated
-sim_ticks 434531908500 # Number of ticks simulated
-final_tick 434531908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.434431 # Number of seconds simulated
+sim_ticks 434430920500 # Number of ticks simulated
+final_tick 434430920500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 91853 # Simulator instruction rate (inst/s)
-host_op_rate 169847 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 48269802 # Simulator tick rate (ticks/s)
-host_mem_usage 425632 # Number of bytes of host memory used
-host_seconds 9002.15 # Real time elapsed on the host
+host_inst_rate 103951 # Simulator instruction rate (inst/s)
+host_op_rate 192218 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 54614710 # Simulator tick rate (ticks/s)
+host_mem_usage 421552 # Number of bytes of host memory used
+host_seconds 7954.47 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
sim_ops 1528988700 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 206656 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24475072 # Number of bytes read from this memory
-system.physmem.bytes_read::total 24681728 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24473856 # Number of bytes read from this memory
+system.physmem.bytes_read::total 24680512 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 206656 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 206656 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18793472 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18793472 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 18792192 # Number of bytes written to this memory
+system.physmem.bytes_written::total 18792192 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3229 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 382423 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 385652 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 293648 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 293648 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 475583 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 56325143 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 56800726 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 475583 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 475583 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 43249924 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 43249924 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 43249924 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 475583 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 56325143 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 100050650 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 385654 # Total number of read requests seen
-system.physmem.writeReqs 293648 # Total number of write requests seen
-system.physmem.cpureqs 897087 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 24681728 # Total number of bytes read from memory
-system.physmem.bytesWritten 18793472 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 24681728 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 18793472 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 151 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 214401 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 23129 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 24463 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 23958 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 22626 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 23437 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 24746 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 24520 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 24217 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 24346 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 24649 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 24306 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 24351 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 24467 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 23427 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 24871 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 23990 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 17780 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 18806 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 18330 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 17563 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 18009 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 18654 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 18318 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 18307 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 18738 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 18746 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 18443 # Track writes on a per bank basis
+system.physmem.num_reads::cpu.data 382404 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 385633 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 293628 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 293628 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 475694 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 56335438 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 56811131 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 475694 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 475694 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 43257031 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 43257031 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 43257031 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 475694 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 56335438 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 100068163 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 385635 # Total number of read requests seen
+system.physmem.writeReqs 293628 # Total number of write requests seen
+system.physmem.cpureqs 897306 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 24680512 # Total number of bytes read from memory
+system.physmem.bytesWritten 18792192 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 24680512 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 18792192 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 135 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 215167 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 23200 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 24440 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 23926 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 22603 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 23455 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 24726 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 24470 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 24228 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 24367 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 24672 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 24294 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 24362 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 24487 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 23459 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 24852 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 23959 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 17796 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 18805 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 18324 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 17566 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 18019 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 18653 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 18315 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 18311 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 18728 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 18743 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 18429 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 18564 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 18554 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 17877 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 18850 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 18109 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 18552 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 17863 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 18856 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 18104 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 3384 # Number of times wr buffer was full causing retry
-system.physmem.totGap 434531891500 # Total gap between requests
+system.physmem.numWrRetry 2876 # Number of times wr buffer was full causing retry
+system.physmem.totGap 434430903500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 385654 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 297032 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 214401 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 380704 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4364 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 366 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
+system.physmem.readPktSize::6 385635 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 293628 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 380797 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4262 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 378 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 58 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 12706 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 12717 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 12721 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 12709 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 12719 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 12720 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 12722 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 12726 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 12730 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 12725 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 12729 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 12733 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 12733 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 12737 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 12739 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 12741 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 62 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 51 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 12766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 58 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 48 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 47 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 46 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 42 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 38 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 35 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 30 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3414434563 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 12002683313 # Sum of mem lat for all requests
-system.physmem.totBusLat 1927515000 # Total cycles spent in databus access
-system.physmem.totBankLat 6660733750 # Total cycles spent in bank access
-system.physmem.avgQLat 8857.09 # Average queueing delay per request
-system.physmem.avgBankLat 17278.03 # Average bank access latency per request
+system.physmem.wrQLenPdf::29 34 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 28 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 26 # What write queue length does an incoming req see
+system.physmem.totQLat 3409479750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11997177250 # Sum of mem lat for all requests
+system.physmem.totBusLat 1927500000 # Total cycles spent in databus access
+system.physmem.totBankLat 6660197500 # Total cycles spent in bank access
+system.physmem.avgQLat 8844.31 # Average queueing delay per request
+system.physmem.avgBankLat 17276.78 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 31135.12 # Average memory access latency
-system.physmem.avgRdBW 56.80 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 43.25 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 56.80 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 43.25 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 31121.08 # Average memory access latency
+system.physmem.avgRdBW 56.81 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 43.26 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 56.81 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 43.26 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.78 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.03 # Average read queue length over time
-system.physmem.avgWrQLen 9.81 # Average write queue length over time
-system.physmem.readRowHits 331850 # Number of row buffer hits during reads
-system.physmem.writeRowHits 191739 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 86.08 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 65.30 # Row buffer hit rate for writes
-system.physmem.avgGap 639674.09 # Average gap between requests
-system.cpu.branchPred.lookups 214985170 # Number of BP lookups
-system.cpu.branchPred.condPredicted 214985170 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 13134974 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 150557498 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 147831953 # Number of BTB hits
+system.physmem.avgWrQLen 9.17 # Average write queue length over time
+system.physmem.readRowHits 331860 # Number of row buffer hits during reads
+system.physmem.writeRowHits 191798 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 86.09 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 65.32 # Row buffer hit rate for writes
+system.physmem.avgGap 639562.15 # Average gap between requests
+system.cpu.branchPred.lookups 214905339 # Number of BP lookups
+system.cpu.branchPred.condPredicted 214905339 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 13127433 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 150477516 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 147823689 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 98.189698 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 98.236396 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 869063818 # number of cpu cycles simulated
+system.cpu.numCycles 868861842 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 180571756 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1193203975 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 214985170 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 147831953 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 371215101 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 83387755 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 231673075 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 33185 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 322843 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 173439567 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 3823649 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 853812868 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.595051 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.389323 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 180577504 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1192973241 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 214905339 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 147823689 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 371150852 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 83341611 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 231393952 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 33171 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 324598 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 87 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 173446874 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 3818726 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 853436670 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.595518 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.389389 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 486992667 57.04% 57.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 24704335 2.89% 59.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 27327411 3.20% 63.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 28832283 3.38% 66.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 18475468 2.16% 68.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 24603692 2.88% 71.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 30623589 3.59% 75.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 28857730 3.38% 78.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 183395693 21.48% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 486691437 57.03% 57.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 24707790 2.90% 59.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 27346098 3.20% 63.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 28808795 3.38% 66.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 18459850 2.16% 68.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 24598509 2.88% 71.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 30642263 3.59% 75.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 28856964 3.38% 78.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 183324964 21.48% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 853812868 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.247376 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.372976 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 237064473 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 188186572 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 313399146 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 45165837 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 69996840 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2166788008 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 69996840 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 270473923 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 53975472 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 17892 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 322682449 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 136666292 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2119871980 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 32012 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 21236600 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 101165935 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 102 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2216234467 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5355317387 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 5355179179 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 138208 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 853436670 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.247341 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.373030 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 237036597 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 187932241 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 313348177 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 45163149 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 69956506 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2166370172 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 6 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 69956506 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 270406129 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 53950609 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 16000 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 322641702 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 136465724 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2119600897 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 32452 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 20939189 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 101244294 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 109 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 2216054849 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5354933162 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 5354796739 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 136423 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1614040852 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 602193615 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1385 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1348 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 330022122 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 512693840 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 204894369 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 196280742 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 55580246 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2033860002 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 23240 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1808188122 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 845695 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 499369913 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 817987835 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 22688 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 853812868 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.117780 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.887735 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 602013997 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1381 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1341 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 329887917 # count of insts added to the skid buffer
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+system.cpu.memDep0.insertedStores 204871608 # Number of stores inserted to the mem dependence unit.
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+system.cpu.memDep0.conflictingStores 55366102 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2033547368 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 23672 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1807958991 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 824800 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 499056334 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 817700270 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 23120 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::2 138299025 16.20% 60.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 133036648 15.58% 76.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 95993641 11.24% 87.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 58825628 6.89% 94.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 34908775 4.09% 98.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 12073867 1.41% 99.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1895297 0.22% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 233342895 27.34% 27.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 145008680 16.99% 44.33% # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::3 133057886 15.59% 76.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 96025914 11.25% 87.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 58740201 6.88% 94.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 34984970 4.10% 98.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 12023870 1.41% 99.78% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 853812868 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 853436670 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 4968961 32.44% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 7761394 50.67% 83.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2587769 16.89% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 4945296 32.31% 32.31% # attempts to use FU when none available
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+system.cpu.iq.fu_full::IntDiv 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 7774785 50.79% 83.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2587375 16.90% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2719358 0.15% 0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1190817504 65.86% 66.01% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 2719757 0.15% 0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1190688442 65.86% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 438925166 24.27% 90.28% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 175726094 9.72% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 438864121 24.27% 90.28% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 175686671 9.72% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1808188122 # Type of FU issued
-system.cpu.iq.rate 2.080616 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 15318124 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.008472 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4486330411 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2533466617 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1768665835 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 22520 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 43644 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 4990 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1820776414 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 10474 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 170620885 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1807958991 # Type of FU issued
+system.cpu.iq.rate 2.080836 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 15307456 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.008467 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4485463564 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2532842226 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1768511816 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23344 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 44056 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 5298 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1820535825 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 10865 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 170531860 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 128591684 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 469733 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 268884 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 55734548 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 128467465 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 477996 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 270600 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 55711763 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 12443 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 683 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 12158 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 637 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 69996840 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 16364844 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2884009 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2033883242 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 2403682 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 512693840 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 204894734 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 6182 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1820537 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 77063 # Number of times the LSQ has become full, causing a stall
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-system.cpu.iew.predictedTakenIncorrect 9113160 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4488782 # Number of branches that were predicted not taken incorrectly
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+system.cpu.iew.iewUnblockCycles 2882420 # Number of cycles IEW is unblocking
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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-system.cpu.commit.committed_per_cycle::1 195507197 24.94% 62.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 61957017 7.90% 69.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 92299201 11.78% 81.70% # Number of insts commited each cycle
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-system.cpu.commit.committed_per_cycle::5 28287004 3.61% 88.51% # Number of insts commited each cycle
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-system.cpu.commit.committed_per_cycle::8 69870405 8.91% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committedInsts 826877109 # Number of instructions committed
system.cpu.commit.committedOps 1528988700 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1528317559 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 69870405 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu.rob.rob_writes 4138016116 # The number of ROB writes
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+system.cpu.rob.rob_reads 2747203850 # The number of ROB reads
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+system.cpu.idleCycles 15425172 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 826877109 # Number of Instructions Simulated
system.cpu.committedOps 1528988700 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated
-system.cpu.cpi 1.051019 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.051019 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.951457 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.951457 # IPC: Total IPC of All Threads
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49481746000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 49481746000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49481746000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 49481746000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006793 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006793 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006622 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006622 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006731 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.006731 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006731 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.006731 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15768.183513 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15768.183513 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21959.097361 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21959.097361 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17991.628443 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17991.628443 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17991.628443 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 17991.628443 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 139855372500 # Number of ticks simulated
final_tick 139855372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 164436 # Simulator instruction rate (inst/s)
-host_op_rate 164436 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 57685897 # Simulator tick rate (ticks/s)
-host_mem_usage 230388 # Number of bytes of host memory used
-host_seconds 2424.43 # Real time elapsed on the host
+host_inst_rate 118034 # Simulator instruction rate (inst/s)
+host_op_rate 118034 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 41407532 # Simulator tick rate (ticks/s)
+host_mem_usage 230404 # Number of bytes of host memory used
+host_seconds 3377.53 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 7328 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 0 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 0 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 4560 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1887 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 585 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 47661305 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 197340055 # Sum of mem lat for all requests
+system.physmem.totQLat 47654000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 197332750 # Sum of mem lat for all requests
system.physmem.totBusLat 36640000 # Total cycles spent in databus access
system.physmem.totBankLat 113038750 # Total cycles spent in bank access
-system.physmem.avgQLat 6504.00 # Average queueing delay per request
+system.physmem.avgQLat 6503.00 # Average queueing delay per request
system.physmem.avgBankLat 15425.59 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26929.59 # Average memory access latency
+system.physmem.avgMemAccLat 26928.60 # Average memory access latency
system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128897344 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35549956 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 164447300 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120759327 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120759327 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128897344 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156309283 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 285206627 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128897344 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156309283 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 285206627 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128894552 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35549355 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 164443907 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120757665 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120757665 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128894552 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156307020 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 285201572 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128894552 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156307020 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 285201572 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38373.725514 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43143.150485 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39313.244083 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38397.242289 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38397.242289 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38373.725514 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39382.535399 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38920.118313 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38373.725514 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39382.535399 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38920.118313 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38372.894314 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43142.421117 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39312.432943 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38396.713831 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38396.713831 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38372.894314 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39381.965231 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38919.428493 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38372.894314 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39381.965231 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38919.428493 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 764 # number of replacements
system.cpu.dcache.tagsinuse 3285.521075 # Cycle average of tags in use
sim_ticks 77333663500 # Number of ticks simulated
final_tick 77333663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 196388 # Simulator instruction rate (inst/s)
-host_op_rate 196388 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 40437661 # Simulator tick rate (ticks/s)
-host_mem_usage 232448 # Number of bytes of host memory used
-host_seconds 1912.42 # Real time elapsed on the host
+host_inst_rate 154881 # Simulator instruction rate (inst/s)
+host_op_rate 154881 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 31891174 # Simulator tick rate (ticks/s)
+host_mem_usage 232452 # Number of bytes of host memory used
+host_seconds 2424.92 # Real time elapsed on the host
sim_insts 375574808 # Number of instructions simulated
sim_ops 375574808 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 221120 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 7448 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 0 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 4136 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 2085 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 804 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 307 # What read queue length does an incoming req see
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 0 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 4137 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 2083 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 806 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 306 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 111 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 53873160 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 207011910 # Sum of mem lat for all requests
+system.physmem.totQLat 53845750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 206984500 # Sum of mem lat for all requests
system.physmem.totBusLat 37240000 # Total cycles spent in databus access
system.physmem.totBankLat 115898750 # Total cycles spent in bank access
-system.physmem.avgQLat 7233.24 # Average queueing delay per request
+system.physmem.avgQLat 7229.56 # Average queueing delay per request
system.physmem.avgBankLat 15561.06 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 27794.30 # Average memory access latency
+system.physmem.avgMemAccLat 27790.61 # Average memory access latency
system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 101791406 # DTB read hits
+system.cpu.dtb.read_hits 101791407 # DTB read hits
system.cpu.dtb.read_misses 78057 # DTB read misses
system.cpu.dtb.read_acv 48605 # DTB read access violations
-system.cpu.dtb.read_accesses 101869463 # DTB read accesses
+system.cpu.dtb.read_accesses 101869464 # DTB read accesses
system.cpu.dtb.write_hits 78427886 # DTB write hits
system.cpu.dtb.write_misses 1487 # DTB write misses
system.cpu.dtb.write_acv 4 # DTB write access violations
system.cpu.dtb.write_accesses 78429373 # DTB write accesses
-system.cpu.dtb.data_hits 180219292 # DTB hits
+system.cpu.dtb.data_hits 180219293 # DTB hits
system.cpu.dtb.data_misses 79544 # DTB misses
system.cpu.dtb.data_acv 48609 # DTB access violations
-system.cpu.dtb.data_accesses 180298836 # DTB accesses
+system.cpu.dtb.data_accesses 180298837 # DTB accesses
system.cpu.itb.fetch_hits 50219857 # ITB hits
system.cpu.itb.fetch_misses 371 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.numCycles 154667329 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 51106120 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 51106123 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 448669005 # Number of instructions fetch has processed
system.cpu.fetch.Branches 50250166 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 32239639 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 78764977 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 6110488 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 19721587 # Number of cycles fetch has spent blocked
+system.cpu.fetch.BlockedCycles 19721562 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 9420 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 50219857 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 408750 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 154473509 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 154473487 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.904505 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.325354 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 75708532 49.01% 49.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 75708510 49.01% 49.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4277779 2.77% 51.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 6877340 4.45% 56.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 5358744 3.47% 59.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 154473509 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 154473487 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.324892 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.900865 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 56459553 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 15066363 # Number of cycles decode is blocked
+system.cpu.decode.IdleCycles 56459555 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 15066339 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 74129391 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3951215 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 4866987 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 444763327 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 12199 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 4866987 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 59590768 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 4877628 # Number of cycles rename is blocking
+system.cpu.rename.IdleCycles 59590769 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 4877606 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 403370 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 75043534 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 9691222 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 440325296 # Number of instructions processed by rename
+system.cpu.rename.UnblockCycles 9691221 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 440325297 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 81 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 19775 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 8008636 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.LSQFullEvents 8008634 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 287258509 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 578891151 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 306269628 # Number of integer rename lookups
system.cpu.rename.UndoneMaps 27726180 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 36829 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 293 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 27858963 # count of insts added to the skid buffer
+system.cpu.rename.skidInsts 27858970 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 104659356 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 80576509 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 8905764 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 6378561 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 408090088 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 408090089 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 285 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 401700569 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 966818 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 32383170 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 966819 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 32383171 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 15203599 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 70 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 154473509 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 154473487 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.600450 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.995226 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 28241568 18.28% 18.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 25850506 16.73% 35.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 25557985 16.55% 51.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 24263587 15.71% 67.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 21289313 13.78% 81.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15479662 10.02% 91.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8473783 5.49% 96.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 28241547 18.28% 18.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 25850500 16.73% 35.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 25557992 16.55% 51.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 24263583 15.71% 67.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 21289316 13.78% 81.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 15479664 10.02% 91.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8473780 5.49% 96.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 3991768 2.58% 99.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1325337 0.86% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 154473509 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 154473487 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 34109 0.29% 0.29% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 5072339 42.83% 74.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 5072338 42.83% 74.92% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 2970257 25.08% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 155713729 38.76% 38.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 155713730 38.76% 38.77% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2126194 0.53% 39.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 32798014 8.16% 47.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 103367731 25.73% 80.27% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 103367730 25.73% 80.27% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 79244441 19.73% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 401700569 # Type of FU issued
system.cpu.iq.rate 2.597191 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 11841746 # FU busy when requested
+system.cpu.iq.fu_busy_cnt 11841745 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.029479 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 633918884 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 260111127 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 234694704 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_reads 633918862 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 260111129 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 234694703 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 336764327 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 180411325 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 161341889 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 241419354 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 241419353 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 172089380 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 15066516 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.cacheBlocked 2892 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 4866987 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2513908 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 367539 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 432875837 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 130046 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewBlockCycles 2513893 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 367538 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 432875839 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 130047 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 104659356 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 80576509 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 285 # Number of dispatched non-speculative instructions
system.cpu.iew.predictedNotTakenIncorrect 405299 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1350807 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 398189954 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 101918110 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts 101918111 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3510615 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 24785464 # number of nop insts executed
-system.cpu.iew.exec_refs 180347520 # number of memory reference insts executed
+system.cpu.iew.exec_nop 24785465 # number of nop insts executed
+system.cpu.iew.exec_refs 180347521 # number of memory reference insts executed
system.cpu.iew.exec_branches 46544583 # Number of branches executed
system.cpu.iew.exec_stores 78429410 # Number of stores executed
system.cpu.iew.exec_rate 2.574493 # Inst execution rate
-system.cpu.iew.wb_sent 396666494 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 396036593 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 193534236 # num instructions producing a value
+system.cpu.iew.wb_sent 396666493 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 396036592 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 193534237 # num instructions producing a value
system.cpu.iew.wb_consumers 271064264 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.560570 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.713979 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 34241397 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 34241399 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1196652 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 149606522 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 149606500 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.664754 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.996488 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 55299818 36.96% 36.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 55299795 36.96% 36.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 22506360 15.04% 52.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 13038976 8.72% 60.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 11456394 7.66% 68.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 8182427 5.47% 73.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 5460458 3.65% 77.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 13038980 8.72% 60.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 11456393 7.66% 68.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 8182424 5.47% 73.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 5460459 3.65% 77.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 5170598 3.46% 80.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3276425 2.19% 83.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 25215066 16.85% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3276423 2.19% 83.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 25215068 16.85% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 149606522 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 149606500 # Number of insts commited each cycle
system.cpu.commit.committedInsts 398664583 # Number of instructions committed
system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions.
system.cpu.commit.int_insts 316365839 # Number of committed integer instructions.
system.cpu.commit.function_calls 8007752 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 25215066 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 25215068 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 557294459 # The number of ROB reads
-system.cpu.rob.rob_writes 870687579 # The number of ROB writes
-system.cpu.timesIdled 3435 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 193820 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 557294437 # The number of ROB reads
+system.cpu.rob.rob_writes 870687583 # The number of ROB writes
+system.cpu.timesIdled 3434 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 193842 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 375574808 # Number of Instructions Simulated
system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated
system.cpu.ipc 2.428275 # IPC: Instructions Per Cycle
system.cpu.ipc_total 2.428275 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 398027050 # number of integer regfile reads
-system.cpu.int_regfile_writes 170092718 # number of integer regfile writes
+system.cpu.int_regfile_writes 170092717 # number of integer regfile writes
system.cpu.fp_regfile_reads 156507210 # number of floating regfile reads
system.cpu.fp_regfile_writes 104024348 # number of floating regfile writes
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 2144 # number of replacements
-system.cpu.icache.tagsinuse 1832.992748 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1832.992783 # Cycle average of tags in use
system.cpu.icache.total_refs 50214380 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 4071 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 12334.654876 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1832.992748 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 1832.992783 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.895016 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.895016 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 50214380 # number of ReadReq hits
system.cpu.icache.demand_misses::total 5477 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 5477 # number of overall misses
system.cpu.icache.overall_misses::total 5477 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 242175000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 242175000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 242175000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 242175000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 242175000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 242175000 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 242151500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 242151500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 242151500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 242151500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 242151500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 242151500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 50219857 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 50219857 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 50219857 # number of demand (read+write) accesses
system.cpu.icache.demand_miss_rate::total 0.000109 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000109 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000109 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44216.724484 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 44216.724484 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 44216.724484 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 44216.724484 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 44216.724484 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 44216.724484 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44212.433814 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 44212.433814 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 44212.433814 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 44212.433814 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 44212.433814 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 44212.433814 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 692 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 4071 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 4071 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 4071 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185126500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 185126500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185126500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 185126500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185126500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 185126500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185116500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 185116500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185116500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 185116500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185116500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 185116500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45474.453451 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45474.453451 # average ReadReq mshr miss latency
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+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167257000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 167257000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 221123000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 221123000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221123000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 221123000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54407.070707 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54407.070707 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52398.652882 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52398.652882 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52874.103300 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52874.103300 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52874.103300 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52874.103300 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54410.101010 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54410.101010 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52398.809524 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52398.809524 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52874.940220 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 52874.940220 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52874.940220 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 52874.940220 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 68358106500 # Number of ticks simulated
final_tick 68358106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 148173 # Simulator instruction rate (inst/s)
-host_op_rate 189432 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 37097000 # Simulator tick rate (ticks/s)
-host_mem_usage 250340 # Number of bytes of host memory used
-host_seconds 1842.69 # Real time elapsed on the host
+host_inst_rate 161957 # Simulator instruction rate (inst/s)
+host_op_rate 207054 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 40547923 # Simulator tick rate (ticks/s)
+host_mem_usage 250356 # Number of bytes of host memory used
+host_seconds 1685.86 # Real time elapsed on the host
sim_insts 273036725 # Number of instructions simulated
sim_ops 349064449 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 193152 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 7278 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 0 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 2 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 0 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 4253 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 2167 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 597 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 46727256 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 192182256 # Sum of mem lat for all requests
+system.physmem.totQLat 46720000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 192175000 # Sum of mem lat for all requests
system.physmem.totBusLat 36390000 # Total cycles spent in databus access
system.physmem.totBankLat 109065000 # Total cycles spent in bank access
-system.physmem.avgQLat 6420.34 # Average queueing delay per request
+system.physmem.avgQLat 6419.35 # Average queueing delay per request
system.physmem.avgBankLat 14985.57 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26405.92 # Average memory access latency
+system.physmem.avgMemAccLat 26404.92 # Average memory access latency
system.physmem.avgRdBW 6.81 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 6.81 # Average consumed read bandwidth in MB/s
system.cpu.icache.overall_avg_mshr_miss_latency::total 18773.979853 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 3956.608159 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 3956.608160 # Cycle average of tags in use
system.cpu.l2cache.total_refs 13151 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 5398 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.436273 # Average number of references to valid blocks.
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3019 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 4259 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7278 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115050359 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 62984754 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 178035113 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115047807 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 62983881 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 178031688 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100922692 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100922692 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115050359 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 163907446 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 278957805 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115050359 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163907446 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 278957805 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100921221 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100921221 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115047807 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 163905102 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 278952909 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115047807 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163905102 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 278952909 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.815000 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255176 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923861 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.356940 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38108.764160 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42934.392638 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39686.828578 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38107.918847 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42933.797546 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39686.065091 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36147.095989 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36147.095989 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36146.569126 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36146.569126 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38107.918847 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38484.409955 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38328.237016 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38107.918847 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38484.409955 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38328.237016 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1413 # number of replacements
system.cpu.dcache.tagsinuse 3109.949983 # Cycle average of tags in use
---------- Begin Simulation Statistics ----------
-sim_seconds 0.629815 # Number of seconds simulated
-sim_ticks 629814900000 # Number of ticks simulated
-final_tick 629814900000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.629620 # Number of seconds simulated
+sim_ticks 629619966000 # Number of ticks simulated
+final_tick 629619966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 180734 # Simulator instruction rate (inst/s)
-host_op_rate 180734 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 62438874 # Simulator tick rate (ticks/s)
-host_mem_usage 248904 # Number of bytes of host memory used
-host_seconds 10086.90 # Real time elapsed on the host
+host_inst_rate 178339 # Simulator instruction rate (inst/s)
+host_op_rate 178339 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 61592425 # Simulator tick rate (ticks/s)
+host_mem_usage 247872 # Number of bytes of host memory used
+host_seconds 10222.36 # Real time elapsed on the host
sim_insts 1823043370 # Number of instructions simulated
sim_ops 1823043370 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 176256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 30295232 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30471488 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 176256 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 176256 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 176384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 30295936 # Number of bytes read from this memory
+system.physmem.bytes_read::total 30472320 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 176384 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 176384 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory
system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2754 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 473363 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 476117 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 2756 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 473374 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 476130 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 279854 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 48101803 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 48381656 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 279854 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 279854 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 6799001 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6799001 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 6799001 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 279854 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 48101803 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 55180657 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 476117 # Total number of read requests seen
+system.physmem.bw_read::cpu.inst 280144 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 48117813 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 48397957 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 280144 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 280144 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 6801106 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6801106 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 6801106 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 280144 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 48117813 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 55199063 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 476130 # Total number of read requests seen
system.physmem.writeReqs 66908 # Total number of write requests seen
-system.physmem.cpureqs 543025 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 30471488 # Total number of bytes read from memory
+system.physmem.cpureqs 543038 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 30472320 # Total number of bytes read from memory
system.physmem.bytesWritten 4282112 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 30471488 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 30472320 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 84 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 29663 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 29736 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 29645 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 29664 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 29737 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 29644 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 29657 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 29698 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 29699 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 29716 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 29817 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 29814 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 29793 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 29817 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 29794 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 29811 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 29701 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 29703 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 29776 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 29780 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 29752 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 29783 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 29754 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 29855 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 29819 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 4150 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 4210 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 629814837500 # Total gap between requests
+system.physmem.totGap 629619903500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 476117 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 66908 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 406568 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 66991 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 2282 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 165 # What read queue length does an incoming req see
+system.physmem.readPktSize::6 476130 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 66908 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 406575 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 66997 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 2280 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 167 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 2899 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 2909 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 2909 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2509077325 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 20518523575 # Sum of mem lat for all requests
-system.physmem.totBusLat 2380165000 # Total cycles spent in databus access
-system.physmem.totBankLat 15629281250 # Total cycles spent in bank access
-system.physmem.avgQLat 5270.81 # Average queueing delay per request
-system.physmem.avgBankLat 32832.35 # Average bank access latency per request
+system.physmem.totQLat 2394780250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 20405886500 # Sum of mem lat for all requests
+system.physmem.totBusLat 2380230000 # Total cycles spent in databus access
+system.physmem.totBankLat 15630876250 # Total cycles spent in bank access
+system.physmem.avgQLat 5030.56 # Average queueing delay per request
+system.physmem.avgBankLat 32834.80 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 43103.15 # Average memory access latency
-system.physmem.avgRdBW 48.38 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 42865.37 # Average memory access latency
+system.physmem.avgRdBW 48.40 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 6.80 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 48.38 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 48.40 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 6.80 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.43 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.03 # Average read queue length over time
system.physmem.avgWrQLen 11.00 # Average write queue length over time
-system.physmem.readRowHits 143855 # Number of row buffer hits during reads
+system.physmem.readRowHits 143857 # Number of row buffer hits during reads
system.physmem.writeRowHits 46184 # Number of row buffer hits during writes
system.physmem.readRowHitRate 30.22 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 69.03 # Row buffer hit rate for writes
-system.physmem.avgGap 1159826.60 # Average gap between requests
-system.cpu.branchPred.lookups 389306486 # Number of BP lookups
-system.cpu.branchPred.condPredicted 255918117 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 25837227 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 318716729 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 258426851 # Number of BTB hits
+system.physmem.avgGap 1159439.86 # Average gap between requests
+system.cpu.branchPred.lookups 389447649 # Number of BP lookups
+system.cpu.branchPred.condPredicted 255913711 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 25827412 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 318653162 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 258406685 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 81.083554 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 57314223 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 6830 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 81.093401 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 57304748 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 7060 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 523161150 # DTB read hits
-system.cpu.dtb.read_misses 589917 # DTB read misses
+system.cpu.dtb.read_hits 523436365 # DTB read hits
+system.cpu.dtb.read_misses 589877 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 523751067 # DTB read accesses
-system.cpu.dtb.write_hits 283054328 # DTB write hits
-system.cpu.dtb.write_misses 50219 # DTB write misses
+system.cpu.dtb.read_accesses 524026242 # DTB read accesses
+system.cpu.dtb.write_hits 283043527 # DTB write hits
+system.cpu.dtb.write_misses 50254 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 283104547 # DTB write accesses
-system.cpu.dtb.data_hits 806215478 # DTB hits
-system.cpu.dtb.data_misses 640136 # DTB misses
+system.cpu.dtb.write_accesses 283093781 # DTB write accesses
+system.cpu.dtb.data_hits 806479892 # DTB hits
+system.cpu.dtb.data_misses 640131 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 806855614 # DTB accesses
-system.cpu.itb.fetch_hits 394785394 # ITB hits
-system.cpu.itb.fetch_misses 699 # ITB misses
+system.cpu.dtb.data_accesses 807120023 # DTB accesses
+system.cpu.itb.fetch_hits 394546295 # ITB hits
+system.cpu.itb.fetch_misses 717 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 394786093 # ITB accesses
+system.cpu.itb.fetch_accesses 394547012 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 39 # Number of system calls
-system.cpu.numCycles 1259629801 # number of cpu cycles simulated
+system.cpu.numCycles 1259239933 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 410360591 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 3276218906 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 389306486 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 315741074 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 630494032 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 158021665 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 72839727 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 148 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 7225 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 64 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 394785394 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 10887979 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1245397368 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.630661 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.141486 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 410282333 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 3275811622 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 389447649 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 315711433 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 630410102 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 157985911 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 72865288 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 149 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 7390 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 394546295 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 10716533 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1245235231 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.630677 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.141977 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 614903336 49.37% 49.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 57906135 4.65% 54.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 43369742 3.48% 57.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 71861713 5.77% 63.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 128784934 10.34% 73.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 45918421 3.69% 77.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 41219044 3.31% 80.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 7530301 0.60% 81.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 233903742 18.78% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 614825129 49.37% 49.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 58056687 4.66% 54.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 43354375 3.48% 57.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 71856761 5.77% 63.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 128610709 10.33% 73.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 45745044 3.67% 77.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 41218746 3.31% 80.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 7546870 0.61% 81.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 234020910 18.79% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1245397368 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.309064 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.600938 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 438252598 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 59249665 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 607151892 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 9059684 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 131683529 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 32106155 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 12464 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3195982000 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 46456 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 131683529 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 467489876 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 24458626 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 27637 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 586624719 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 35112981 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 3097789893 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 99 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 15390 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 28842141 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2055592035 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3582007579 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3461235411 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 120772168 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1245235231 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.309272 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.601420 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 438008414 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 59262942 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 607236165 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 9069872 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 131657838 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 32266957 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 12470 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3196223031 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 46480 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 131657838 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 467254081 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 24463646 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 27494 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 586711565 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 35120607 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 3098173488 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 98 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 15446 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 28849573 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2055567023 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3582389843 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3461627532 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 120762311 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 670622965 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 4249 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 110 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 109569448 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 744863024 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 351426191 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 68774306 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 8838853 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2625568629 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 106 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2161657606 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 17941272 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 802459111 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 727402983 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 67 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1245397368 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.735717 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.803838 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 670597953 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 4242 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 103 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 109579430 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 745093938 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 351398329 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 68579657 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 8864385 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2626006003 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 100 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2162044617 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 17925122 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 802898808 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 727596475 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1245235231 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.736254 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.804060 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 448194916 35.99% 35.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 197399515 15.85% 51.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 251498314 20.19% 72.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 120129049 9.65% 81.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 104781180 8.41% 90.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 79785428 6.41% 96.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 24208472 1.94% 98.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 17632328 1.42% 99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1768166 0.14% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 447917303 35.97% 35.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 197535103 15.86% 51.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 251432136 20.19% 72.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 120080138 9.64% 81.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 104735346 8.41% 90.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 79904704 6.42% 96.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 24241740 1.95% 98.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 17620604 1.42% 99.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1768157 0.14% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1245397368 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1245235231 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 1146254 3.12% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 1146296 3.12% 3.12% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 25630359 69.68% 72.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 10007683 27.21% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 25620524 69.67% 72.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 10007560 27.21% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1235285403 57.15% 57.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1235570303 57.15% 57.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 17096 0.00% 57.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 27851426 1.29% 58.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 27851417 1.29% 58.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 8254694 0.38% 58.82% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 7204648 0.33% 59.15% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 589902835 27.29% 86.44% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 293138748 13.56% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 590015596 27.29% 86.44% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 293128107 13.56% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2161657606 # Type of FU issued
-system.cpu.iq.rate 1.716105 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 36784296 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.017017 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 5472336078 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3339899399 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1991115322 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 151102070 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 88201964 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 73610146 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2120988960 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 77450190 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 62844771 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2162044617 # Type of FU issued
+system.cpu.iq.rate 1.716944 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 36774380 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.017009 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 5472922147 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3340796044 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1991352678 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 151101820 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 88182161 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 73610057 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2121366202 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 77450043 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 63177927 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 233792998 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 726346 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 76067 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 140631295 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 234023912 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 1058362 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 75850 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 140603433 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 4418 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 2432 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 2424 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 131683529 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 10419712 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 524131 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2988971416 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 730880 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 744863024 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 351426191 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 106 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 195253 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 131657838 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 10420983 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 524239 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2989422700 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 731121 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 745093938 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 351398329 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 100 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 195339 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1467 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 76067 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 25831488 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 28075 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 25859563 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2067932709 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 523751206 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 93724897 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 75850 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 25820235 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 27779 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 25848014 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2068492319 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 524026374 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 93552298 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 363402681 # number of nop insts executed
-system.cpu.iew.exec_refs 806856273 # number of memory reference insts executed
-system.cpu.iew.exec_branches 278042301 # Number of branches executed
-system.cpu.iew.exec_stores 283105067 # Number of stores executed
-system.cpu.iew.exec_rate 1.641699 # Inst execution rate
-system.cpu.iew.wb_sent 2067106315 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2064725468 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1181149065 # num instructions producing a value
-system.cpu.iew.wb_consumers 1753530061 # num instructions consuming a value
+system.cpu.iew.exec_nop 363416597 # number of nop insts executed
+system.cpu.iew.exec_refs 807120680 # number of memory reference insts executed
+system.cpu.iew.exec_branches 278196977 # Number of branches executed
+system.cpu.iew.exec_stores 283094306 # Number of stores executed
+system.cpu.iew.exec_rate 1.642651 # Inst execution rate
+system.cpu.iew.wb_sent 2067333908 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2064962735 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1181126750 # num instructions producing a value
+system.cpu.iew.wb_consumers 1753498514 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.639153 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.673584 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.639849 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.673583 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 963038308 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 963484022 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 25825176 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1113713839 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.803863 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.507965 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 25815357 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1113577393 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.804084 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.508160 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 494406511 44.39% 44.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 228855545 20.55% 64.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 119827890 10.76% 75.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 58850017 5.28% 80.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 50714183 4.55% 85.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 24146625 2.17% 87.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 19124586 1.72% 89.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 16719001 1.50% 90.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 101069481 9.07% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 494309525 44.39% 44.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 228815920 20.55% 64.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 119838693 10.76% 75.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 58859369 5.29% 80.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 50684004 4.55% 85.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 24146580 2.17% 87.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 19115188 1.72% 89.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 16708765 1.50% 90.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 101099349 9.08% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1113713839 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1113577393 # Number of insts commited each cycle
system.cpu.commit.committedInsts 2008987604 # Number of instructions committed
system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions.
system.cpu.commit.function_calls 39955347 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 101069481 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 101099349 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3979033860 # The number of ROB reads
-system.cpu.rob.rob_writes 6075737407 # The number of ROB writes
-system.cpu.timesIdled 331555 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 14232433 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3979313260 # The number of ROB reads
+system.cpu.rob.rob_writes 6076602940 # The number of ROB writes
+system.cpu.timesIdled 331541 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 14004702 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
-system.cpu.cpi 0.690949 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.690949 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.447285 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.447285 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 2629419671 # number of integer regfile reads
-system.cpu.int_regfile_writes 1497304474 # number of integer regfile writes
-system.cpu.fp_regfile_reads 78811610 # number of floating regfile reads
-system.cpu.fp_regfile_writes 52661263 # number of floating regfile writes
+system.cpu.cpi 0.690735 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.690735 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.447733 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.447733 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 2629807592 # number of integer regfile reads
+system.cpu.int_regfile_writes 1497388428 # number of integer regfile writes
+system.cpu.fp_regfile_reads 78811502 # number of floating regfile reads
+system.cpu.fp_regfile_writes 52661191 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.icache.replacements 8336 # number of replacements
-system.cpu.icache.tagsinuse 1655.843165 # Cycle average of tags in use
-system.cpu.icache.total_refs 394772509 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 10048 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 39288.665307 # Average number of references to valid blocks.
+system.cpu.icache.replacements 8338 # number of replacements
+system.cpu.icache.tagsinuse 1655.801182 # Cycle average of tags in use
+system.cpu.icache.total_refs 394533427 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 10050 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 39257.057413 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1655.843165 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.808517 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.808517 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 394772509 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 394772509 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 394772509 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 394772509 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 394772509 # number of overall hits
-system.cpu.icache.overall_hits::total 394772509 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 12885 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 12885 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 12885 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 12885 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 12885 # number of overall misses
-system.cpu.icache.overall_misses::total 12885 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 310466999 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 310466999 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 310466999 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 310466999 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 310466999 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 310466999 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 394785394 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 394785394 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 394785394 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 394785394 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 394785394 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 394785394 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 1655.801182 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.808497 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.808497 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 394533427 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 394533427 # number of ReadReq hits
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+system.cpu.icache.demand_hits::total 394533427 # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total 394533427 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 12868 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 12868 # number of ReadReq misses
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+system.cpu.icache.demand_misses::total 12868 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 12868 # number of overall misses
+system.cpu.icache.overall_misses::total 12868 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 310260499 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 310260499 # number of ReadReq miss cycles
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+system.cpu.icache.overall_miss_latency::cpu.inst 310260499 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 310260499 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 394546295 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total 394546295 # number of demand (read+write) accesses
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+system.cpu.icache.overall_accesses::total 394546295 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24095.226931 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 24095.226931 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 24095.226931 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 24095.226931 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 24095.226931 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 24095.226931 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 1110 # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24111.011735 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 24111.011735 # average ReadReq miss latency
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+system.cpu.dcache.overall_mshr_misses::total 1531882 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39489667000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 39489667000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3899533000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3899533000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 42500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 42500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43389200000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 43389200000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43389200000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 43389200000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003173 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003173 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.034483 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.034483 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.037037 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.037037 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002283 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002283 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27119.544286 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27119.544286 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54423.641160 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54423.641160 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 42000 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 42000 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28396.468438 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28396.468438 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28396.468438 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28396.468438 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27043.290174 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27043.290174 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54430.062951 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54430.062951 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 42500 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 42500 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28324.113737 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28324.113737 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28324.113737 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28324.113737 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 627777658000 # Number of ticks simulated
final_tick 627777658000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 102547 # Simulator instruction rate (inst/s)
-host_op_rate 139655 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 46502403 # Simulator tick rate (ticks/s)
-host_mem_usage 263380 # Number of bytes of host memory used
-host_seconds 13499.90 # Real time elapsed on the host
+host_inst_rate 109787 # Simulator instruction rate (inst/s)
+host_op_rate 149515 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 49785649 # Simulator tick rate (ticks/s)
+host_mem_usage 262368 # Number of bytes of host memory used
+host_seconds 12609.61 # Real time elapsed on the host
sim_insts 1384370590 # Number of instructions simulated
sim_ops 1885325342 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 154944 # Number of bytes read from this memory
system.physmem.bw_total::total 55159809 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 474966 # Total number of read requests seen
system.physmem.writeReqs 66098 # Total number of write requests seen
-system.physmem.cpureqs 545370 # Reqs generatd by CPU via cache - shady
+system.physmem.cpureqs 545372 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 30397824 # Total number of bytes read from memory
system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 30397824 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 160 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4306 # Reqs where no action is needed
+system.physmem.neitherReadNorWrite 4308 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 29710 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 29703 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 29690 # Track reads on a per bank basis
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 474966 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 66098 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 4306 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 66098 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 405913 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 66670 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 2123 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 2873 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3183088396 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 21162955896 # Sum of mem lat for all requests
+system.physmem.totQLat 3182824500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 21162788250 # Sum of mem lat for all requests
system.physmem.totBusLat 2374030000 # Total cycles spent in databus access
-system.physmem.totBankLat 15605837500 # Total cycles spent in bank access
-system.physmem.avgQLat 6703.98 # Average queueing delay per request
-system.physmem.avgBankLat 32867.82 # Average bank access latency per request
+system.physmem.totBankLat 15605933750 # Total cycles spent in bank access
+system.physmem.avgQLat 6703.42 # Average queueing delay per request
+system.physmem.avgBankLat 32868.02 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 44571.80 # Average memory access latency
+system.physmem.avgMemAccLat 44571.44 # Average memory access latency
system.physmem.avgRdBW 48.42 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 6.74 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 48.42 # Average consumed read bandwidth in MB/s
system.physmem.readRowHitRate 30.19 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 68.87 # Row buffer hit rate for writes
system.physmem.avgGap 1160264.94 # Average gap between requests
-system.cpu.branchPred.lookups 438315949 # Number of BP lookups
-system.cpu.branchPred.condPredicted 349727895 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 30635218 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 247833729 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 226959272 # Number of BTB hits
+system.cpu.branchPred.lookups 438315942 # Number of BP lookups
+system.cpu.branchPred.condPredicted 349727890 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 30635219 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 247833723 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 226959266 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 91.577233 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 52304914 # Number of times the RAS was used to get a target.
system.cpu.numCycles 1255555317 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 353470069 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2285596028 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 438315949 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 279264186 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 600835407 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.icacheStallCycles 353470076 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2285596018 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 438315942 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 279264180 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 600835401 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 157814267 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 132516295 # Number of cycles fetch has spent blocked
+system.cpu.fetch.BlockedCycles 132517239 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 11276 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 79 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 333121638 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 10719820 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1213960668 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.592464 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 333121635 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 10719821 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1213961612 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.592462 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.190927 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 613169619 50.51% 50.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 42771995 3.52% 54.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 613170569 50.51% 50.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 42771992 3.52% 54.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 95714848 7.88% 61.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 55497081 4.57% 66.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 71974347 5.93% 72.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 42167025 3.47% 75.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 30997749 2.55% 78.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 71974346 5.93% 72.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 42167023 3.47% 75.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 30997748 2.55% 78.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 31607119 2.60% 81.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 230060885 18.95% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 230060886 18.95% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1213960668 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 1213961612 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.349101 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.820387 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 402973564 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 105163486 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 561876522 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 16833920 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 127113176 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 44705456 # Number of times decode resolved a branch
+system.cpu.decode.IdleCycles 402973570 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 105164432 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 561876513 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 16833922 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 127113175 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 44705454 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 15362 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3047243338 # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts 3047243320 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 28333 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 127113176 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 438520822 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 34436909 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 439020 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 541081767 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 72368974 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2975054938 # Number of instructions processed by rename
+system.cpu.rename.SquashCycles 127113175 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 438520828 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 34437480 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 439400 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 541081761 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 72368968 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2975054899 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 69 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 4810929 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 57090218 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.IQFullEvents 4810930 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 57090211 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2946030157 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 14164065012 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 13593632114 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 570432898 # Number of floating rename lookups
+system.cpu.rename.RenamedOperands 2946030115 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 14164064845 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 13593631976 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 570432869 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 952890067 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 25235 # count of serializing insts renamed
+system.cpu.rename.UndoneMaps 952890025 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 25236 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 22720 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 195466607 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 973207419 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 490834558 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts 195466614 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 973207403 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 490834559 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 36203648 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 40613994 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2806590548 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.memDep0.conflictingStores 40613980 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2806590515 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 29404 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2437414927 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 13391010 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 908731725 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 2361150738 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 2437414876 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 13391013 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 908731819 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 2361150824 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 8020 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1213960668 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.007820 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.875088 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 1213961612 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.007819 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.875089 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 377941740 31.13% 31.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 183591562 15.12% 46.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 202672032 16.70% 62.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 169721528 13.98% 76.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 132842997 10.94% 87.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 93759242 7.72% 95.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 37926001 3.12% 98.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 12454015 1.03% 99.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 377942739 31.13% 31.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 183591536 15.12% 46.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 202672014 16.70% 62.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 169721523 13.98% 76.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 132842970 10.94% 87.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 93759245 7.72% 95.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 37926008 3.12% 98.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 12454026 1.03% 99.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 3051551 0.25% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1213960668 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1213961612 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 716787 0.82% 0.82% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 24382 0.03% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 55152383 62.89% 63.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 55152382 62.89% 63.74% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 31800755 36.26% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1108357182 45.47% 45.47% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1108357154 45.47% 45.47% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 11223525 0.46% 45.93% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.93% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 5502589 0.23% 46.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 5502588 0.23% 46.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 23405387 0.96% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 23405386 0.96% 47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 838249114 34.39% 81.85% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 442425362 18.15% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 838249094 34.39% 81.85% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 442425361 18.15% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2437414927 # Type of FU issued
+system.cpu.iq.FU_type_0::total 2437414876 # Type of FU issued
system.cpu.iq.rate 1.941304 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 87694307 # FU busy when requested
+system.cpu.iq.fu_busy_cnt 87694306 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.035978 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6067361460 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3632711634 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2254358298 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 122514379 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 82707337 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 56439823 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2461788389 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 63320845 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 84306518 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_inst_queue_reads 6067362312 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3632711697 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2254358254 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 122514371 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 82707334 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 56439819 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2461788341 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 63320841 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 84306513 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 341820238 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 8584 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 1429957 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 213839261 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 341820222 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 8583 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 1429956 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 213839262 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 315 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 127113176 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 12638060 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1558330 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2806632420 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 127113175 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 12638633 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1558332 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2806632387 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 1396294 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 973207419 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 490834558 # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts 973207403 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 490834559 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 19418 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1554339 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents 1554341 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 1429957 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 32461973 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.memOrderViolationEvents 1429956 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 32461974 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1494406 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 33956379 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2363518803 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 792548176 # Number of load instructions executed
+system.cpu.iew.branchMispredicts 33956380 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2363518752 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 792548156 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 73896124 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 12468 # number of nop insts executed
-system.cpu.iew.exec_refs 1216269109 # number of memory reference insts executed
-system.cpu.iew.exec_branches 322574295 # Number of branches executed
-system.cpu.iew.exec_stores 423720933 # Number of stores executed
+system.cpu.iew.exec_refs 1216269086 # number of memory reference insts executed
+system.cpu.iew.exec_branches 322574286 # Number of branches executed
+system.cpu.iew.exec_stores 423720930 # Number of stores executed
system.cpu.iew.exec_rate 1.882449 # Inst execution rate
-system.cpu.iew.wb_sent 2336489279 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2310798121 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1347631532 # num instructions producing a value
-system.cpu.iew.wb_consumers 2523967593 # num instructions consuming a value
+system.cpu.iew.wb_sent 2336489228 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2310798073 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1347631579 # num instructions producing a value
+system.cpu.iew.wb_consumers 2523967689 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.840459 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.533934 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 921296208 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 921296175 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 30621417 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1086847492 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.734683 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.398806 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 30621418 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1086848437 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.734682 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.398805 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 446547765 41.09% 41.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 288590720 26.55% 67.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 95114963 8.75% 76.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 446548721 41.09% 41.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 288590719 26.55% 67.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 95114953 8.75% 76.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 70229595 6.46% 82.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 46461872 4.27% 87.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 22187807 2.04% 89.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 15847038 1.46% 90.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 10983680 1.01% 91.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 90884052 8.36% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 46461870 4.27% 87.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 22187798 2.04% 89.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 15847039 1.46% 90.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 10983692 1.01% 91.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 90884050 8.36% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1086847492 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1086848437 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 90884052 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 90884050 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3802577661 # The number of ROB reads
-system.cpu.rob.rob_writes 5740389540 # The number of ROB writes
-system.cpu.timesIdled 353175 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 41594649 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3802578575 # The number of ROB reads
+system.cpu.rob.rob_writes 5740389473 # The number of ROB writes
+system.cpu.timesIdled 353174 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 41593705 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated
system.cpu.cpi_total 0.906950 # CPI: Total CPI of All Threads
system.cpu.ipc 1.102596 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.102596 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 11774707522 # number of integer regfile reads
-system.cpu.int_regfile_writes 2226782313 # number of integer regfile writes
-system.cpu.fp_regfile_reads 68797358 # number of floating regfile reads
-system.cpu.fp_regfile_writes 49551948 # number of floating regfile writes
-system.cpu.misc_regfile_reads 1364040381 # number of misc regfile reads
+system.cpu.int_regfile_reads 11774707263 # number of integer regfile reads
+system.cpu.int_regfile_writes 2226782267 # number of integer regfile writes
+system.cpu.fp_regfile_reads 68797357 # number of floating regfile reads
+system.cpu.fp_regfile_writes 49551943 # number of floating regfile writes
+system.cpu.misc_regfile_reads 1364040345 # number of misc regfile reads
system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
system.cpu.icache.replacements 22740 # number of replacements
-system.cpu.icache.tagsinuse 1642.119595 # Cycle average of tags in use
-system.cpu.icache.total_refs 333085984 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1642.119596 # Cycle average of tags in use
+system.cpu.icache.total_refs 333085977 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 24420 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 13639.884685 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 13639.884398 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1642.119595 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 1642.119596 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.801816 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.801816 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 333090009 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 333090009 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 333090009 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 333090009 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 333090009 # number of overall hits
-system.cpu.icache.overall_hits::total 333090009 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 31628 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 31628 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 31628 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 31628 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 31628 # number of overall misses
-system.cpu.icache.overall_misses::total 31628 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 481224999 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 481224999 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 481224999 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 481224999 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 481224999 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 481224999 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 333121637 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 333121637 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 333121637 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 333121637 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 333121637 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 333090004 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 333090004 # number of ReadReq hits
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+system.cpu.icache.demand_hits::total 333090004 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 333090004 # number of overall hits
+system.cpu.icache.overall_hits::total 333090004 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 31630 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 31630 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 31630 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 31630 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 31630 # number of overall misses
+system.cpu.icache.overall_misses::total 31630 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 481232999 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 481232999 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 481232999 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 481232999 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 481232999 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 481232999 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 333121634 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 333121634 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 333121634 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 333121634 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 333121634 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 333121634 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000095 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000095 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000095 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000095 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000095 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000095 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15215.157424 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 15215.157424 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 15215.157424 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 15215.157424 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 15215.157424 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 15215.157424 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15214.448277 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 15214.448277 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 15214.448277 # average overall miss latency
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-system.cpu.dcache.overall_misses::cpu.data 2795405 # number of overall misses
-system.cpu.dcache.overall_misses::total 2795405 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 66482799000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 66482799000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 39425610969 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 39425610969 # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 2795409 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2795409 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2795409 # number of overall misses
+system.cpu.dcache.overall_misses::total 2795409 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 66484216000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 66484216000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 39427025969 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 39427025969 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 215500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 215500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 105908409969 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 105908409969 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 105908409969 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 105908409969 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 695815092 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 695815092 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 105911241969 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 105911241969 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 105911241969 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 105911241969 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 695815077 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 695815077 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10001 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10001 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 972750770 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 972750770 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 972750770 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 972750770 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 972750755 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 972750755 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 972750755 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 972750755 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002808 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002808 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003040 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::total 0.002874 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002874 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002874 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34031.944556 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34031.944556 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46831.330202 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 46831.330202 # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34032.669906 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34032.669906 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46832.788476 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 46832.788476 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71833.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 37886.606760 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 37886.606760 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 37886.606760 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 37886.606760 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37887.565637 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37887.565637 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 37887.565637 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 37887.565637 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 1756 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 747 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 57 # number of cycles access was blocked
system.cpu.dcache.writebacks::total 96321 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488834 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 488834 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765039 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 765039 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765041 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 765041 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1253873 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1253873 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1253873 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1253873 # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1253875 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1253875 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1253875 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1253875 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464707 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1464707 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76825 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 76825 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1541532 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1541532 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1541532 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1541532 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40831551000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 40831551000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3409167500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3409167500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44240718500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 44240718500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44240718500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 44240718500 # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76827 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 76827 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1541534 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1541534 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1541534 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1541534 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40831573000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 40831573000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3409419500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3409419500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44240992500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 44240992500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44240992500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 44240992500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27876.941259 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27876.941259 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44375.756590 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44375.756590 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28699.189183 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28699.189183 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28699.189183 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28699.189183 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27876.956279 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27876.956279 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44377.881474 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44377.881474 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28699.329694 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28699.329694 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28699.329694 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28699.329694 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 42726055500 # Number of ticks simulated
final_tick 42726055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 156388 # Simulator instruction rate (inst/s)
-host_op_rate 156388 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 75637274 # Simulator tick rate (ticks/s)
-host_mem_usage 259292 # Number of bytes of host memory used
-host_seconds 564.88 # Real time elapsed on the host
+host_inst_rate 89848 # Simulator instruction rate (inst/s)
+host_op_rate 89848 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 43455006 # Simulator tick rate (ticks/s)
+host_mem_usage 257260 # Number of bytes of host memory used
+host_seconds 983.23 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 454848 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 165519 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 114011 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 62480 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 76428 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 18694 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 7913 # What read queue length does an incoming req see
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 113997 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 62479 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 76432 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 18692 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 7912 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 2065 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3855 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 3856 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4866 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 4917 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 4945 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 2892 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 1102 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 1101 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 91 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 40 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 7053628221 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 9647149471 # Sum of mem lat for all requests
+system.physmem.totQLat 7053839750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 9647402250 # Sum of mem lat for all requests
system.physmem.totBusLat 827595000 # Total cycles spent in databus access
-system.physmem.totBankLat 1765926250 # Total cycles spent in bank access
-system.physmem.avgQLat 42615.22 # Average queueing delay per request
-system.physmem.avgBankLat 10669.02 # Average bank access latency per request
+system.physmem.totBankLat 1765967500 # Total cycles spent in bank access
+system.physmem.avgQLat 42616.50 # Average queueing delay per request
+system.physmem.avgBankLat 10669.27 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 58284.24 # Average memory access latency
+system.physmem.avgMemAccLat 58285.77 # Average memory access latency
system.physmem.avgRdBW 247.93 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 170.76 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 247.93 # Average consumed read bandwidth in MB/s
system.physmem.avgRdQLen 0.23 # Average read queue length over time
system.physmem.avgWrQLen 10.42 # Average write queue length over time
system.physmem.readRowHits 148856 # Number of row buffer hits during reads
-system.physmem.writeRowHits 71620 # Number of row buffer hits during writes
+system.physmem.writeRowHits 71619 # Number of row buffer hits during writes
system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 62.83 # Row buffer hit rate for writes
system.physmem.avgGap 152857.21 # Average gap between requests
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 77185122 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 77185132 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 229327 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.timesIdled 229329 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 15874710 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 69577402 # Number of cycles cpu stages are processed.
system.cpu.activity 81.422683 # Percentage of cycles cpu is active
system.cpu.stage4.runCycles 46049203 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 53.888900 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 84308 # number of replacements
-system.cpu.icache.tagsinuse 1908.296965 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1908.296945 # Cycle average of tags in use
system.cpu.icache.total_refs 12251160 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 86354 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 141.871367 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1908.296965 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 1908.296945 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.931786 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.931786 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 12251160 # number of ReadReq hits
system.cpu.icache.demand_misses::total 117106 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 117106 # number of overall misses
system.cpu.icache.overall_misses::total 117106 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 1888398500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 1888398500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 1888398500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 1888398500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 1888398500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 1888398500 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 1889037500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 1889037500 # number of ReadReq miss cycles
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-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12268407000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 12268407000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14177104000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 14177104000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14177104000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 14177104000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1908276000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 1908276000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12268587000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 12268587000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14176863000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 14176863000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14176863000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 14176863000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31411.124825 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31411.124825 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85446.489762 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85446.489762 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69378.276934 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 69378.276934 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69378.276934 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 69378.276934 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31404.196495 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31404.196495 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85447.743418 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85447.743418 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69377.097556 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 69377.097556 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69377.097556 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 69377.097556 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.023883 # Number of seconds simulated
-sim_ticks 23882696000 # Number of ticks simulated
-final_tick 23882696000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.023888 # Number of seconds simulated
+sim_ticks 23888231000 # Number of ticks simulated
+final_tick 23888231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 224964 # Simulator instruction rate (inst/s)
-host_op_rate 224964 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 67503934 # Simulator tick rate (ticks/s)
-host_mem_usage 262380 # Number of bytes of host memory used
-host_seconds 353.80 # Real time elapsed on the host
+host_inst_rate 143918 # Simulator instruction rate (inst/s)
+host_op_rate 143918 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 43194720 # Simulator tick rate (ticks/s)
+host_mem_usage 260336 # Number of bytes of host memory used
+host_seconds 553.04 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
sim_ops 79591756 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 490816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10154176 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10644992 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 490816 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 490816 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7297024 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7297024 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 7669 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 158659 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 166328 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 114016 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 114016 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 20551114 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 425168750 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 445719863 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 20551114 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 20551114 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 305536025 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 305536025 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 305536025 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 20551114 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 425168750 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 751255888 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 166328 # Total number of read requests seen
-system.physmem.writeReqs 114016 # Total number of write requests seen
-system.physmem.cpureqs 280344 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 10644992 # Total number of bytes read from memory
-system.physmem.bytesWritten 7297024 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 10644992 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7297024 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q
+system.physmem.bytes_read::cpu.inst 490944 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10154112 # Number of bytes read from this memory
+system.physmem.bytes_read::total 10645056 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 490944 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 490944 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7296832 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7296832 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 7671 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 158658 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 166329 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 114013 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 114013 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 20551710 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 425067557 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 445619267 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 20551710 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 20551710 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 305457194 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 305457194 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 305457194 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 20551710 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 425067557 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 751076461 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 166329 # Total number of read requests seen
+system.physmem.writeReqs 114013 # Total number of write requests seen
+system.physmem.cpureqs 280342 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 10645056 # Total number of bytes read from memory
+system.physmem.bytesWritten 7296832 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 10645056 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7296832 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 4 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 10650 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 10530 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 10319 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 10261 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 10573 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 10797 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 10412 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 10353 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 10494 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 10479 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 10254 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 10521 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 10326 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 10267 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 10582 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 10798 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 10408 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 10348 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 10490 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 10474 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 10257 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 9973 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 10566 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 10395 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 10156 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 10115 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 10565 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 10397 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 10153 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 10116 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 7374 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7243 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7242 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 6949 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 6836 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7243 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 6837 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7244 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 7385 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7027 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7026 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 7008 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 7264 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7157 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 7155 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 7041 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 6935 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7275 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7274 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 7040 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 6989 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 23882663000 # Total gap between requests
+system.physmem.totGap 23888198000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 166328 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 114016 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 67939 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 63061 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 27665 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 7639 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.readPktSize::6 166329 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 114013 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 67947 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 63103 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 27555 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 7700 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3042 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 4406 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 4866 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 4933 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 4949 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 3016 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 4341 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 4857 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 4925 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 1916 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 552 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 92 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 25 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 1942 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 617 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 32 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 7244561154 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 9788827404 # Sum of mem lat for all requests
-system.physmem.totBusLat 831635000 # Total cycles spent in databus access
-system.physmem.totBankLat 1712631250 # Total cycles spent in bank access
-system.physmem.avgQLat 43556.13 # Average queueing delay per request
-system.physmem.avgBankLat 10296.77 # Average bank access latency per request
+system.physmem.totQLat 7273642250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 9818352250 # Sum of mem lat for all requests
+system.physmem.totBusLat 831625000 # Total cycles spent in databus access
+system.physmem.totBankLat 1713085000 # Total cycles spent in bank access
+system.physmem.avgQLat 43731.50 # Average queueing delay per request
+system.physmem.avgBankLat 10299.62 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 58852.91 # Average memory access latency
-system.physmem.avgRdBW 445.72 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 305.54 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 445.72 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 305.54 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 59031.13 # Average memory access latency
+system.physmem.avgRdBW 445.62 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 305.46 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 445.62 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 305.46 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 5.87 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.41 # Average read queue length over time
-system.physmem.avgWrQLen 10.04 # Average write queue length over time
-system.physmem.readRowHits 149202 # Number of row buffer hits during reads
-system.physmem.writeRowHits 70865 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 89.70 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 62.15 # Row buffer hit rate for writes
-system.physmem.avgGap 85190.56 # Average gap between requests
-system.cpu.branchPred.lookups 16542352 # Number of BP lookups
-system.cpu.branchPred.condPredicted 10681130 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 417709 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 11519084 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7344749 # Number of BTB hits
+system.physmem.avgWrQLen 10.09 # Average write queue length over time
+system.physmem.readRowHits 149212 # Number of row buffer hits during reads
+system.physmem.writeRowHits 70966 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 89.71 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 62.24 # Row buffer hit rate for writes
+system.physmem.avgGap 85210.91 # Average gap between requests
+system.cpu.branchPred.lookups 16542734 # Number of BP lookups
+system.cpu.branchPred.condPredicted 10685518 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 416834 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 11542683 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7340422 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 63.761572 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1990053 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 40943 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 63.593724 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1986948 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 41598 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 22396635 # DTB read hits
-system.cpu.dtb.read_misses 219070 # DTB read misses
-system.cpu.dtb.read_acv 53 # DTB read access violations
-system.cpu.dtb.read_accesses 22615705 # DTB read accesses
-system.cpu.dtb.write_hits 15704107 # DTB write hits
-system.cpu.dtb.write_misses 40999 # DTB write misses
-system.cpu.dtb.write_acv 6 # DTB write access violations
-system.cpu.dtb.write_accesses 15745106 # DTB write accesses
-system.cpu.dtb.data_hits 38100742 # DTB hits
-system.cpu.dtb.data_misses 260069 # DTB misses
-system.cpu.dtb.data_acv 59 # DTB access violations
-system.cpu.dtb.data_accesses 38360811 # DTB accesses
-system.cpu.itb.fetch_hits 13916224 # ITB hits
-system.cpu.itb.fetch_misses 34938 # ITB misses
+system.cpu.dtb.read_hits 22395624 # DTB read hits
+system.cpu.dtb.read_misses 219289 # DTB read misses
+system.cpu.dtb.read_acv 61 # DTB read access violations
+system.cpu.dtb.read_accesses 22614913 # DTB read accesses
+system.cpu.dtb.write_hits 15707380 # DTB write hits
+system.cpu.dtb.write_misses 41224 # DTB write misses
+system.cpu.dtb.write_acv 1 # DTB write access violations
+system.cpu.dtb.write_accesses 15748604 # DTB write accesses
+system.cpu.dtb.data_hits 38103004 # DTB hits
+system.cpu.dtb.data_misses 260513 # DTB misses
+system.cpu.dtb.data_acv 62 # DTB access violations
+system.cpu.dtb.data_accesses 38363517 # DTB accesses
+system.cpu.itb.fetch_hits 13912342 # ITB hits
+system.cpu.itb.fetch_misses 34675 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 13951162 # ITB accesses
+system.cpu.itb.fetch_accesses 13947017 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
-system.cpu.numCycles 47765395 # number of cpu cycles simulated
+system.cpu.numCycles 47776465 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 15792461 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 105331722 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 16542352 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9334802 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 19546012 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2000871 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 6407929 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 7641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 309888 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13916224 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 206477 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 43516697 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.420490 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.137268 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 15792140 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 105356372 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 16542734 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9327370 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 19544101 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1999173 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 6408053 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 7580 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 309115 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 13912342 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 209427 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 43512690 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.421279 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.137905 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 23970685 55.08% 55.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1532413 3.52% 58.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1373284 3.16% 61.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1510754 3.47% 65.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4137026 9.51% 74.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1849440 4.25% 78.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 675147 1.55% 80.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1069291 2.46% 83.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 7398657 17.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 23968589 55.08% 55.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1529417 3.51% 58.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1370330 3.15% 61.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1513065 3.48% 65.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 4135878 9.50% 74.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1846880 4.24% 78.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 674126 1.55% 80.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1070808 2.46% 82.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 7403597 17.01% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 43516697 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.346325 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.205189 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 16865376 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 5950414 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 18541793 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 811002 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1348112 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3746218 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 106835 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 103623462 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 302130 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1348112 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 17322335 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 3664232 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 84922 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18847631 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 2249465 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 102361026 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 441 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 2593 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 2123305 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 61634933 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 123335826 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 122884489 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 451337 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 43512690 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.346253 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.205194 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 16866618 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 5950644 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18537765 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 810794 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1346869 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3745393 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 107096 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 103623154 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 304519 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1346869 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 17322284 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 3660735 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 85948 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 18844978 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 2251876 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 102372237 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 493 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 2675 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 2125269 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 61644392 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 123362389 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 122911717 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 450672 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 9088052 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 5535 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 5532 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 4634659 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 23233430 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 16268738 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1206800 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 454955 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 90740192 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 5270 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 88424187 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 96369 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 10688335 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 4670210 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 687 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 43516697 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.031960 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.108941 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 9097511 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 5543 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 5541 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 4645908 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 23234130 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 16272775 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1204976 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 463178 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 90743430 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 5284 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 88424765 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 96747 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 10698511 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 4674782 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 701 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 43512690 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.032160 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.108847 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 15243033 35.03% 35.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 6914940 15.89% 50.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 5620995 12.92% 63.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 4761900 10.94% 74.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4675938 10.75% 85.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2651856 6.09% 91.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1932644 4.44% 96.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1300467 2.99% 99.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 414924 0.95% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 15237669 35.02% 35.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 6914925 15.89% 50.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 5623850 12.92% 63.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 4759728 10.94% 74.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4676300 10.75% 85.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2652660 6.10% 91.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1932814 4.44% 96.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1300380 2.99% 99.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 414364 0.95% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 43516697 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 43512690 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 125783 6.76% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 785729 42.22% 48.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 949726 51.03% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 125555 6.75% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 785994 42.27% 49.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 947743 50.97% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 49355625 55.82% 55.82% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 43814 0.05% 55.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 49355125 55.82% 55.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 43912 0.05% 55.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 121422 0.14% 56.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 121345 0.14% 56.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 53 0.00% 56.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 38953 0.04% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 22849621 25.84% 82.03% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 15893267 17.97% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 121242 0.14% 56.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 91 0.00% 56.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 121107 0.14% 56.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 38943 0.04% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 22848081 25.84% 82.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 15896208 17.98% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 88424187 # Type of FU issued
-system.cpu.iq.rate 1.851219 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1861238 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.021049 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 221719097 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 101035757 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 86539045 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 603581 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 415879 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 294278 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 89983556 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 301869 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1467344 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 88424765 # Type of FU issued
+system.cpu.iq.rate 1.850802 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1859292 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.021027 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 221714954 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 101050466 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 86544122 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 603305 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 414877 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 294005 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 89982323 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 301734 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1469012 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 2956792 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 4757 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 18083 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1655361 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 2957492 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 4689 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18546 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1659398 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2846 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 90923 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2825 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 92449 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1348112 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2689881 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 74163 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 100228982 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 217751 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 23233430 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 16268738 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 5270 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 60091 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 514 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 18083 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 196583 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 160586 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 357169 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 87578672 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 22618883 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 845515 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1346869 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 2686448 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 74137 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 100230193 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 219543 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 23234130 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 16272775 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 5284 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 60080 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 507 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 18546 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 196235 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 160668 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 356903 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 87583307 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 22618160 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 841458 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 9483520 # number of nop insts executed
-system.cpu.iew.exec_refs 38364354 # number of memory reference insts executed
-system.cpu.iew.exec_branches 15084185 # Number of branches executed
-system.cpu.iew.exec_stores 15745471 # Number of stores executed
-system.cpu.iew.exec_rate 1.833517 # Inst execution rate
-system.cpu.iew.wb_sent 87223381 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 86833323 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 33358386 # num instructions producing a value
-system.cpu.iew.wb_consumers 43765374 # num instructions consuming a value
+system.cpu.iew.exec_nop 9481479 # number of nop insts executed
+system.cpu.iew.exec_refs 38367101 # number of memory reference insts executed
+system.cpu.iew.exec_branches 15084952 # Number of branches executed
+system.cpu.iew.exec_stores 15748941 # Number of stores executed
+system.cpu.iew.exec_rate 1.833189 # Inst execution rate
+system.cpu.iew.wb_sent 87228229 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 86838127 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 33365194 # num instructions producing a value
+system.cpu.iew.wb_consumers 43783216 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.817913 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.762210 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.817592 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.762054 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 8889050 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 8889017 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 313123 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 42168585 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.094940 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.806680 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 312044 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 42165821 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.095078 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.806430 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 19301880 45.77% 45.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 7026183 16.66% 62.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3423669 8.12% 70.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2056444 4.88% 75.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2047690 4.86% 80.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1162920 2.76% 83.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1093248 2.59% 85.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 719437 1.71% 87.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5337114 12.66% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 19296165 45.76% 45.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 7025692 16.66% 62.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3426859 8.13% 70.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2055479 4.87% 75.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2052042 4.87% 80.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1160972 2.75% 83.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1093221 2.59% 85.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 720657 1.71% 87.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5334734 12.65% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 42168585 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 42165821 # Number of insts commited each cycle
system.cpu.commit.committedInsts 88340672 # Number of instructions committed
system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions.
system.cpu.commit.int_insts 77942044 # Number of committed integer instructions.
system.cpu.commit.function_calls 1661057 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5337114 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5334734 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 132743851 # The number of ROB reads
-system.cpu.rob.rob_writes 195810249 # The number of ROB writes
-system.cpu.timesIdled 70469 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 4248698 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 132743434 # The number of ROB reads
+system.cpu.rob.rob_writes 195808907 # The number of ROB writes
+system.cpu.timesIdled 70658 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 4263775 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
-system.cpu.cpi 0.600130 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.600130 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.666306 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.666306 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 115907691 # number of integer regfile reads
-system.cpu.int_regfile_writes 57507162 # number of integer regfile writes
-system.cpu.fp_regfile_reads 249392 # number of floating regfile reads
-system.cpu.fp_regfile_writes 240337 # number of floating regfile writes
-system.cpu.misc_regfile_reads 38035 # number of misc regfile reads
+system.cpu.cpi 0.600269 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.600269 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.665920 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.665920 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 115915036 # number of integer regfile reads
+system.cpu.int_regfile_writes 57508829 # number of integer regfile writes
+system.cpu.fp_regfile_reads 249335 # number of floating regfile reads
+system.cpu.fp_regfile_writes 239876 # number of floating regfile writes
+system.cpu.misc_regfile_reads 38020 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.icache.replacements 91216 # number of replacements
-system.cpu.icache.tagsinuse 1928.922459 # Cycle average of tags in use
-system.cpu.icache.total_refs 13810559 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 93264 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 148.080277 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 19641578000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1928.922459 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.941857 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.941857 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 13810559 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 13810559 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 13810559 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 13810559 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 13810559 # number of overall hits
-system.cpu.icache.overall_hits::total 13810559 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 105664 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 105664 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 105664 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 105664 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 105664 # number of overall misses
-system.cpu.icache.overall_misses::total 105664 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 1863781999 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 1863781999 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 1863781999 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 1863781999 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 1863781999 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 1863781999 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 13916223 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 13916223 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 13916223 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 13916223 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 13916223 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 13916223 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007593 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.007593 # miss rate for ReadReq accesses
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+system.cpu.dcache.ReadReq_avg_miss_latency::total 45186.784482 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76224.904218 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 76224.904218 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 69880.492427 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 69880.492427 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 69880.492427 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 69880.492427 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 4400680 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 119 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 112282 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 112252 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 38.984966 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.203578 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 119 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 168913 # number of writebacks
-system.cpu.dcache.writebacks::total 168913 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204795 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 204795 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895965 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 895965 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1100760 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1100760 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1100760 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1100760 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62112 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 62112 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143415 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 143415 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 205527 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 205527 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 205527 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 205527 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2016329500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2016329500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12443477492 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 12443477492 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14459806992 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 14459806992 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14459806992 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 14459806992 # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks 168922 # number of writebacks
+system.cpu.dcache.writebacks::total 168922 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204918 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 204918 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895901 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 895901 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1100819 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1100819 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1100819 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1100819 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62109 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 62109 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143421 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 143421 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 205530 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 205530 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 205530 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 205530 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2021126000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2021126000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12474690492 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 12474690492 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14495816492 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 14495816492 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14495816492 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 14495816492 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002974 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002974 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.005789 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.005789 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32462.801069 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32462.801069 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86765.523076 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86765.523076 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70354.780598 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 70354.780598 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70354.780598 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 70354.780598 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005790 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.005790 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005790 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.005790 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32541.596226 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32541.596226 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86979.525258 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86979.525258 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70528.956804 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 70528.956804 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70528.956804 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 70528.956804 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 25577832000 # Number of ticks simulated
final_tick 25577832000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 153227 # Simulator instruction rate (inst/s)
-host_op_rate 217448 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 55271946 # Simulator tick rate (ticks/s)
-host_mem_usage 270340 # Number of bytes of host memory used
-host_seconds 462.76 # Real time elapsed on the host
+host_inst_rate 133487 # Simulator instruction rate (inst/s)
+host_op_rate 189436 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 48151664 # Simulator tick rate (ticks/s)
+host_mem_usage 268312 # Number of bytes of host memory used
+host_seconds 531.19 # Real time elapsed on the host
sim_insts 70907629 # Number of instructions simulated
sim_ops 100626876 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 128779 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 83944 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 312 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 70134 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 56500 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 2062 # What read queue length does an incoming req see
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 83944 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 70150 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 56485 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 2061 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3542 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 3543 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 3645 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 108 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3204614448 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 5248634448 # Sum of mem lat for all requests
+system.physmem.totQLat 3204596500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 5248699000 # Sum of mem lat for all requests
system.physmem.totBusLat 643885000 # Total cycles spent in databus access
-system.physmem.totBankLat 1400135000 # Total cycles spent in bank access
-system.physmem.avgQLat 24884.99 # Average queueing delay per request
-system.physmem.avgBankLat 10872.55 # Average bank access latency per request
+system.physmem.totBankLat 1400217500 # Total cycles spent in bank access
+system.physmem.avgQLat 24884.85 # Average queueing delay per request
+system.physmem.avgBankLat 10873.20 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 40757.55 # Average memory access latency
+system.physmem.avgMemAccLat 40758.05 # Average memory access latency
system.physmem.avgRdBW 322.23 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 210.04 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 322.23 # Average consumed read bandwidth in MB/s
system.cpu.numCycles 51155665 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 12532709 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 12532708 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 85214691 # Number of instructions fetch has processed
system.cpu.fetch.Branches 16629564 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 9594774 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 21193802 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2370777 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 10561174 # Number of cycles fetch has spent blocked
+system.cpu.fetch.BlockedCycles 10561405 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 619 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 11680132 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 179650 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 46029302 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.592220 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.335381 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheSquashes 179651 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 46029532 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.592208 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.335378 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 24855702 54.00% 54.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 24855932 54.00% 54.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2137922 4.64% 58.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1963242 4.27% 62.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2041100 4.43% 67.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 46029302 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 46029532 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.325078 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.665792 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 14615111 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 8910636 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19475070 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1390460 # Number of cycles decode is unblocking
+system.cpu.decode.IdleCycles 14615115 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 8910863 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 19475067 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1390462 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1638025 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3332403 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 104704 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 116875392 # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts 116875388 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 362618 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1638025 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 16327930 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 2553995 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 876400 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 19102314 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5530638 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 115006216 # Number of instructions processed by rename
+system.cpu.rename.IdleCycles 16327942 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 2554176 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 876402 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 19102307 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 5530680 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 115006208 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 128 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 16441 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4672566 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.LSQFullEvents 4672604 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 267 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 115315088 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 529845526 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 529838425 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 115315076 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 529845478 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 529838377 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 7101 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 16182416 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 16182404 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 20249 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 20243 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13070329 # count of insts added to the skid buffer
+system.cpu.rename.skidInsts 13070399 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 29628857 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 22448482 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 3867260 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 4365711 # Number of conflicting stores.
+system.cpu.memDep0.conflictingStores 4365710 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 111562544 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 35868 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 107265054 # Number of instructions issued
system.cpu.iq.iqSquashedInstsExamined 10824806 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 25919657 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2082 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 46029302 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.330365 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.988633 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 46029532 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.330353 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.988634 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10776543 23.41% 23.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 8085599 17.57% 40.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7427656 16.14% 57.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7135117 15.50% 72.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 5408591 11.75% 84.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3911102 8.50% 92.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1839411 4.00% 96.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 10776737 23.41% 23.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 8085644 17.57% 40.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7427640 16.14% 57.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7135127 15.50% 72.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 5408613 11.75% 84.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3911083 8.50% 92.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1839405 4.00% 96.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 869812 1.89% 98.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 575471 1.25% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 46029302 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 46029532 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 112614 4.57% 4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1347948 54.70% 59.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 1003479 40.72% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 1003472 40.72% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 107265054 # Type of FU issued
system.cpu.iq.rate 2.096836 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2464043 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.022972 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 263297262 # Number of integer instruction queue reads
+system.cpu.iq.fu_busy_cnt 2464036 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.022971 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 263297485 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 122451085 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 105577839 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_wakeup_accesses 105577838 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 597 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 998 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 169 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 109728805 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 109728798 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 292 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 2178424 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.cacheBlocked 510 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1638025 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1048423 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 45681 # Number of cycles IEW is unblocking
+system.cpu.iew.iewBlockCycles 1048533 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 45693 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 111608173 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 293378 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 29628857 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 22448482 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 19948 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 6875 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 5224 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 5227 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 30026 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 391684 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 181878 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 573562 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 106234972 # Number of executed instructions
+system.cpu.iew.iewExecutedInsts 106234971 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 28603939 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1030082 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecSquashedInsts 1030083 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 9761 # number of nop insts executed
system.cpu.iew.exec_refs 49948503 # number of memory reference insts executed
system.cpu.iew.exec_branches 14602542 # Number of branches executed
system.cpu.iew.exec_stores 21344564 # Number of stores executed
system.cpu.iew.exec_rate 2.076700 # Inst execution rate
-system.cpu.iew.wb_sent 105797759 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 105578008 # cumulative count of insts written-back
+system.cpu.iew.wb_sent 105797758 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 105578007 # cumulative count of insts written-back
system.cpu.iew.wb_producers 53282087 # num instructions producing a value
-system.cpu.iew.wb_consumers 103565148 # num instructions consuming a value
+system.cpu.iew.wb_consumers 103565099 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.063858 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.514479 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 10976636 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 500410 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 44391277 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.266941 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.764740 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 44391507 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.266930 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.764737 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 15317735 34.51% 34.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11646185 26.24% 60.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3462928 7.80% 68.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 15317930 34.51% 34.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11646230 26.24% 60.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3462929 7.80% 68.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2873664 6.47% 75.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1875712 4.23% 79.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1949355 4.39% 83.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 685853 1.55% 85.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 564106 1.27% 86.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 6015739 13.55% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1875708 4.23% 79.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1949349 4.39% 83.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 685850 1.55% 85.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 564105 1.27% 86.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 6015742 13.55% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 44391277 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 44391507 # Number of insts commited each cycle
system.cpu.commit.committedInsts 70913181 # Number of instructions committed
system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
system.cpu.commit.int_insts 91472779 # Number of committed integer instructions.
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 6015739 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 6015742 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 149959303 # The number of ROB reads
+system.cpu.rob.rob_reads 149959530 # The number of ROB reads
system.cpu.rob.rob_writes 224865260 # The number of ROB writes
-system.cpu.timesIdled 74068 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 5126363 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.timesIdled 74070 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 5126133 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 70907629 # Number of Instructions Simulated
system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated
system.cpu.cpi_total 0.721441 # CPI: Total CPI of All Threads
system.cpu.ipc 1.386115 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.386115 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 511661177 # number of integer regfile reads
-system.cpu.int_regfile_writes 103341315 # number of integer regfile writes
+system.cpu.int_regfile_reads 511661173 # number of integer regfile reads
+system.cpu.int_regfile_writes 103341311 # number of integer regfile writes
system.cpu.fp_regfile_reads 804 # number of floating regfile reads
system.cpu.fp_regfile_writes 688 # number of floating regfile writes
system.cpu.misc_regfile_reads 49186243 # number of misc regfile reads
system.cpu.misc_regfile_writes 31840 # number of misc regfile writes
system.cpu.icache.replacements 28586 # number of replacements
-system.cpu.icache.tagsinuse 1814.278230 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1814.278271 # Cycle average of tags in use
system.cpu.icache.total_refs 11645439 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 30619 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 380.333747 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1814.278230 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 1814.278271 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.885878 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.885878 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 11645446 # number of ReadReq hits
system.cpu.icache.demand_misses::total 34686 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 34686 # number of overall misses
system.cpu.icache.overall_misses::total 34686 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 739119000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 739119000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 739119000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 739119000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 739119000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 739119000 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 739337000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 739337000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 739337000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 739337000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 739337000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 739337000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 11680132 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 11680132 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 11680132 # number of demand (read+write) accesses
system.cpu.icache.demand_miss_rate::total 0.002970 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.002970 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.002970 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21308.856599 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 21308.856599 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 21308.856599 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 21308.856599 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 21308.856599 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 21308.856599 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21315.141556 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 21315.141556 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 21315.141556 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 21315.141556 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 761 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 30945 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 30945 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 30945 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 600341000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 600341000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 600341000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 600341000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 600341000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 600341000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 600567000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 600567000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 600567000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 600567000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 600567000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 600567000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002649 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.002649 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.002649 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19400.258523 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19400.258523 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19400.258523 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 19400.258523 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19400.258523 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 19400.258523 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19407.561803 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19407.561803 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 95649 # number of replacements
-system.cpu.l2cache.tagsinuse 30090.049168 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 30090.044330 # Cycle average of tags in use
system.cpu.l2cache.total_refs 88124 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 126758 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.695215 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 26935.644891 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 1374.538058 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 1779.866218 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks 26935.640674 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 1374.538102 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 1779.865554 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.822011 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.041948 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.054317 # Average percentage of cache occupancy
system.cpu.l2cache.overall_misses::cpu.inst 4676 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 124179 # number of overall misses
system.cpu.l2cache.overall_misses::total 128855 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 310311500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1482845500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 1793157000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 310537500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1482354000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1792891500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6640773000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 6640773000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 310311500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 8123618500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 8433930000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 310311500 # number of overall miss cycles
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-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63375.003400 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63375.003400 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53338.193308 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53338.193308 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53338.193308 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53338.193308 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33886.606031 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33886.606031 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63379.144332 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63379.144332 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 993559170500 # Number of ticks simulated
final_tick 993559170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 148425 # Simulator instruction rate (inst/s)
-host_op_rate 148425 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 81036604 # Simulator tick rate (ticks/s)
-host_mem_usage 464668 # Number of bytes of host memory used
-host_seconds 12260.62 # Real time elapsed on the host
+host_inst_rate 139940 # Simulator instruction rate (inst/s)
+host_op_rate 139940 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 76403951 # Simulator tick rate (ticks/s)
+host_mem_usage 449176 # Number of bytes of host memory used
+host_seconds 13004.03 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 1959688 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 1018171 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1630106 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 205346 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 87736 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 35917 # What read queue length does an incoming req see
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 1018058 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 1630116 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 205318 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 87737 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 35934 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 41624 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 43771 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 43773 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 44240 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 44256 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 44259 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 2640 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 493 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 491 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 35848625999 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 104288840999 # Sum of mem lat for all requests
+system.physmem.totQLat 35843451500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 104284202750 # Sum of mem lat for all requests
system.physmem.totBusLat 9795530000 # Total cycles spent in databus access
-system.physmem.totBankLat 58644685000 # Total cycles spent in bank access
-system.physmem.avgQLat 18298.46 # Average queueing delay per request
-system.physmem.avgBankLat 29934.41 # Average bank access latency per request
+system.physmem.totBankLat 58645221250 # Total cycles spent in bank access
+system.physmem.avgQLat 18295.82 # Average queueing delay per request
+system.physmem.avgBankLat 29934.69 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 53232.87 # Average memory access latency
+system.physmem.avgMemAccLat 53230.51 # Average memory access latency
system.physmem.avgRdBW 126.23 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 65.58 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 126.23 # Average consumed read bandwidth in MB/s
system.physmem.busUtil 1.50 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.10 # Average read queue length over time
system.physmem.avgWrQLen 10.46 # Average write queue length over time
-system.physmem.readRowHits 770935 # Number of row buffer hits during reads
-system.physmem.writeRowHits 285714 # Number of row buffer hits during writes
+system.physmem.readRowHits 770937 # Number of row buffer hits during reads
+system.physmem.writeRowHits 285715 # Number of row buffer hits during writes
system.physmem.readRowHitRate 39.35 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes
system.physmem.avgGap 333661.47 # Average gap between requests
system.cpu.branchPred.lookups 326540496 # Number of BP lookups
-system.cpu.branchPred.condPredicted 252608544 # Number of conditional branches predicted
+system.cpu.branchPred.condPredicted 252608543 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 138248451 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 220022753 # Number of BTB lookups
system.cpu.branchPred.BTBHits 135563778 # Number of BTB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 444796007 # DTB read hits
+system.cpu.dtb.read_hits 444796009 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 449693085 # DTB read accesses
-system.cpu.dtb.write_hits 160833351 # DTB write hits
+system.cpu.dtb.read_accesses 449693087 # DTB read accesses
+system.cpu.dtb.write_hits 160833358 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 162534655 # DTB write accesses
-system.cpu.dtb.data_hits 605629358 # DTB hits
+system.cpu.dtb.write_accesses 162534662 # DTB write accesses
+system.cpu.dtb.data_hits 605629367 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 612227740 # DTB accesses
-system.cpu.itb.fetch_hits 232025962 # ITB hits
+system.cpu.dtb.data_accesses 612227749 # DTB accesses
+system.cpu.itb.fetch_hits 232025963 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 232025984 # ITB accesses
+system.cpu.itb.fetch_accesses 232025985 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.numCycles 1987118342 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.predictedTaken 172378846 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 154161650 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 1667662469 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.predictedTaken 172378847 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 154161649 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 1667662468 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 3043865086 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses 3043865085 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 651727789 # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens 617884568 # Number of Address Generations
+system.cpu.regfile_manager.regForwards 651727790 # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens 617884569 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 120519408 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 11130585 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 131649993 # Number of Branches Incorrectly Predicted
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 1741838166 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 1741838474 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 7484554 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 415293759 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 1571824583 # Number of cycles cpu stages are processed.
-system.cpu.activity 79.100703 # Percentage of cycles cpu is active
+system.cpu.timesIdled 7484621 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 415293731 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 1571824611 # Number of cycles cpu stages are processed.
+system.cpu.activity 79.100705 # Percentage of cycles cpu is active
system.cpu.comLoads 444595663 # Number of Load instructions committed
system.cpu.comStores 160728502 # Number of Store instructions committed
system.cpu.comBranches 214632552 # Number of Branches instructions committed
system.cpu.ipc 0.915789 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.915789 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 800261653 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 1186856689 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 59.727529 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 1053419210 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 933699132 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.idleCycles 800261647 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 1186856695 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 59.727530 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 1053419200 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 933699142 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 46.987596 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 1014725197 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 972393145 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 48.934838 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 1577495451 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 409622891 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.idleCycles 1014725184 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 972393158 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 48.934839 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 1577495448 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 409622894 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.613915 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 965781597 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 1021336745 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.idleCycles 965781598 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 1021336744 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 51.397882 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.tagsinuse 667.839755 # Cycle average of tags in use
-system.cpu.icache.total_refs 232024853 # Total number of references to valid blocks.
+system.cpu.icache.total_refs 232024854 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 270110.422584 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 270110.423749 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 667.839755 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.326094 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.326094 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 232024853 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 232024853 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 232024853 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 232024853 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 232024853 # number of overall hits
-system.cpu.icache.overall_hits::total 232024853 # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst 232024854 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 232024854 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 232024854 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 232024854 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 232024854 # number of overall hits
+system.cpu.icache.overall_hits::total 232024854 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1109 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1109 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1109 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1109 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1109 # number of overall misses
system.cpu.icache.overall_misses::total 1109 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 64824000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 64824000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 64824000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 64824000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 64824000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 64824000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 232025962 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 232025962 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 232025962 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 232025962 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 232025962 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 232025962 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 64819000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 64819000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 64819000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 64819000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 64819000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 64819000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 232025963 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 232025963 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 232025963 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 232025963 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 232025963 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 232025963 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58452.660054 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 58452.660054 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 58452.660054 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 58452.660054 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 58452.660054 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 58452.660054 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58448.151488 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 58448.151488 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 58448.151488 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 58448.151488 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 58448.151488 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 58448.151488 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51094000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 51094000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51094000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 51094000 # number of demand (read+write) MSHR miss cycles
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+system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.143253 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 72.563533 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3693293 # number of writebacks
system.cpu.dcache.writebacks::total 3693293 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104622 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 104622 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595195 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2595195 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 2699817 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 2699817 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 2699817 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 2699817 # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595235 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2595235 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 2699857 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 2699857 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2699857 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2699857 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222283 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7222283 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889185 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9111468 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9111468 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9111468 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150964459500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 150964459500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79317190500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 79317190500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230281650000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 230281650000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230281650000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 230281650000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150964297500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 150964297500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79314869000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 79314869000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230279166500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 230279166500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230279166500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 230279166500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20902.595412 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20902.595412 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41984.872048 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41984.872048 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25273.825250 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25273.825250 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25273.825250 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25273.825250 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20902.572981 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20902.572981 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41983.643211 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41983.643211 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25273.552681 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25273.552681 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25273.552681 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25273.552681 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.665563 # Number of seconds simulated
-sim_ticks 665562897500 # Number of ticks simulated
-final_tick 665562897500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.665771 # Number of seconds simulated
+sim_ticks 665770972500 # Number of ticks simulated
+final_tick 665770972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 181531 # Simulator instruction rate (inst/s)
-host_op_rate 181531 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 69595242 # Simulator tick rate (ticks/s)
-host_mem_usage 467736 # Number of bytes of host memory used
-host_seconds 9563.34 # Real time elapsed on the host
+host_inst_rate 179472 # Simulator instruction rate (inst/s)
+host_op_rate 179472 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 68827168 # Simulator tick rate (ticks/s)
+host_mem_usage 452252 # Number of bytes of host memory used
+host_seconds 9673.08 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
sim_ops 1736043781 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 125801472 # Number of bytes read from this memory
-system.physmem.bytes_read::total 125863104 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 65262912 # Number of bytes written to this memory
-system.physmem.bytes_written::total 65262912 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1965648 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1966611 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1019733 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1019733 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 92601 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 189015152 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 189107753 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 92601 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 92601 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 98056716 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 98056716 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 98056716 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 92601 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 189015152 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 287164469 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1966611 # Total number of read requests seen
-system.physmem.writeReqs 1019733 # Total number of write requests seen
-system.physmem.cpureqs 2988993 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 125863104 # Total number of bytes read from memory
-system.physmem.bytesWritten 65262912 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 125863104 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 65262912 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 562 # Number of read reqs serviced by write Q
+system.physmem.bytes_read::cpu.inst 62016 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 125796608 # Number of bytes read from this memory
+system.physmem.bytes_read::total 125858624 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 62016 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 62016 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 65265344 # Number of bytes written to this memory
+system.physmem.bytes_written::total 65265344 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 969 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1965572 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1966541 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1019771 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1019771 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 93149 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 188948772 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 189041922 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 93149 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 93149 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 98029723 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 98029723 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 98029723 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 93149 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 188948772 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 287071645 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1966541 # Total number of read requests seen
+system.physmem.writeReqs 1019771 # Total number of write requests seen
+system.physmem.cpureqs 2988947 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 125858624 # Total number of bytes read from memory
+system.physmem.bytesWritten 65265344 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 125858624 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 65265344 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 566 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 122665 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 122306 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 122208 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 124220 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 123661 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 122580 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 120700 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 121417 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 122611 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 122314 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 122187 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 124202 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 123643 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 122594 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 120701 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 121432 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 121606 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 122292 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 121462 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 123460 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 125578 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 124270 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 123173 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 124451 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 63478 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 62392 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 63122 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 63842 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 64138 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 63875 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 63473 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 63461 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 63474 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 63840 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 63360 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 64241 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 64652 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 64261 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 63751 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 64373 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::9 122264 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 121460 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 123481 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 125598 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 124291 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 123180 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 124411 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 63480 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 62406 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 63107 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 63843 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 64137 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 63874 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 63470 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 63464 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 63489 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 63818 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 63362 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 64260 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 64664 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 64287 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 63760 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 64350 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 2649 # Number of times wr buffer was full causing retry
-system.physmem.totGap 665562829000 # Total gap between requests
+system.physmem.numWrRetry 2635 # Number of times wr buffer was full causing retry
+system.physmem.totGap 665770904000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 1966611 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 1022382 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1625792 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 234895 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 77536 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 27805 # What read queue length does an incoming req see
+system.physmem.readPktSize::6 1966541 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 1019771 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 1625771 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 234883 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 77503 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 27794 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 42397 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 43965 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 44248 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 44303 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 44315 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 44317 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 44319 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 44319 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 44320 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 1940 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 372 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 89 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 34 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 42250 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 43943 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 44238 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 44300 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 44316 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 44321 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 44321 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 44322 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 44322 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 44338 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 44337 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 44337 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 44337 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 2088 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 395 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 34363983237 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 102498683237 # Sum of mem lat for all requests
-system.physmem.totBusLat 9830245000 # Total cycles spent in databus access
-system.physmem.totBankLat 58304455000 # Total cycles spent in bank access
-system.physmem.avgQLat 17478.70 # Average queueing delay per request
-system.physmem.avgBankLat 29655.65 # Average bank access latency per request
+system.physmem.totQLat 34478547500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 102599787500 # Sum of mem lat for all requests
+system.physmem.totBusLat 9829875000 # Total cycles spent in databus access
+system.physmem.totBankLat 58291365000 # Total cycles spent in bank access
+system.physmem.avgQLat 17537.63 # Average queueing delay per request
+system.physmem.avgBankLat 29650.10 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 52134.35 # Average memory access latency
-system.physmem.avgRdBW 189.11 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 98.06 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 189.11 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 98.06 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 52187.74 # Average memory access latency
+system.physmem.avgRdBW 189.04 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 98.03 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 189.04 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 98.03 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.24 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.15 # Average read queue length over time
-system.physmem.avgWrQLen 10.79 # Average write queue length over time
-system.physmem.readRowHits 776053 # Number of row buffer hits during reads
-system.physmem.writeRowHits 286138 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 39.47 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes
-system.physmem.avgGap 222868.77 # Average gap between requests
-system.cpu.branchPred.lookups 381322658 # Number of BP lookups
-system.cpu.branchPred.condPredicted 296346711 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 16069927 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 262182430 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 259521497 # Number of BTB hits
+system.physmem.avgWrQLen 10.14 # Average write queue length over time
+system.physmem.readRowHits 776350 # Number of row buffer hits during reads
+system.physmem.writeRowHits 285987 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 39.49 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 28.04 # Row buffer hit rate for writes
+system.physmem.avgGap 222940.84 # Average gap between requests
+system.cpu.branchPred.lookups 381390262 # Number of BP lookups
+system.cpu.branchPred.condPredicted 296397889 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 16086653 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 262140629 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 259559256 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 98.985083 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 24701305 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 3076 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 99.015272 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 24699160 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 3055 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 613798645 # DTB read hits
-system.cpu.dtb.read_misses 11251599 # DTB read misses
+system.cpu.dtb.read_hits 613788534 # DTB read hits
+system.cpu.dtb.read_misses 11249325 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 625050244 # DTB read accesses
-system.cpu.dtb.write_hits 212271089 # DTB write hits
-system.cpu.dtb.write_misses 7143652 # DTB write misses
+system.cpu.dtb.read_accesses 625037859 # DTB read accesses
+system.cpu.dtb.write_hits 212245958 # DTB write hits
+system.cpu.dtb.write_misses 7142739 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 219414741 # DTB write accesses
-system.cpu.dtb.data_hits 826069734 # DTB hits
-system.cpu.dtb.data_misses 18395251 # DTB misses
+system.cpu.dtb.write_accesses 219388697 # DTB write accesses
+system.cpu.dtb.data_hits 826034492 # DTB hits
+system.cpu.dtb.data_misses 18392064 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 844464985 # DTB accesses
-system.cpu.itb.fetch_hits 390709896 # ITB hits
-system.cpu.itb.fetch_misses 44 # ITB misses
+system.cpu.dtb.data_accesses 844426556 # DTB accesses
+system.cpu.itb.fetch_hits 390787767 # ITB hits
+system.cpu.itb.fetch_misses 43 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 390709940 # ITB accesses
+system.cpu.itb.fetch_accesses 390787810 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
-system.cpu.numCycles 1331125796 # number of cpu cycles simulated
+system.cpu.numCycles 1331541946 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 402151320 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 3159313188 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 381322658 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 284222802 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 574163176 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 140279243 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 173671179 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1322 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 390709896 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 8056983 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1266457048 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.494607 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.152796 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 402238482 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 3159760476 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 381390262 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 284258416 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 574242721 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 140320135 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 173885771 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1317 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 44 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 390787767 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 8065204 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1266865295 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.494157 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.152669 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 692293872 54.66% 54.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 42630313 3.37% 58.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 21744461 1.72% 59.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 39673370 3.13% 62.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 129246893 10.21% 73.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 61513639 4.86% 77.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 38552077 3.04% 80.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 28113770 2.22% 83.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 212688653 16.79% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 692622574 54.67% 54.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 42615431 3.36% 58.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 21758353 1.72% 59.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 39697295 3.13% 62.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 129259260 10.20% 73.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 61526950 4.86% 77.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 38544819 3.04% 80.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 28129154 2.22% 83.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 212711459 16.79% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1266457048 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.286466 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.373414 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 433835858 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 155176701 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 542390430 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 18584911 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 116469148 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 58290582 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 824 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3086789571 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2029 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 116469148 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 456704578 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 101399871 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 7042 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 535436988 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 56439421 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 3004825157 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 566473 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1727265 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 50367655 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2246602827 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3897066108 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3895827965 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1238143 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1266865295 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.286428 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.373009 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 433949818 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 155380202 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 542435049 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 18604092 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 116496134 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 58311036 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 855 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3087126857 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2089 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 116496134 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 456815247 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 101557658 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 5194 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 535499027 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 56492035 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 3005134049 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 566488 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1739616 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 50408333 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2246840239 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3897438135 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3896197591 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1240544 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 870399864 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 162 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 161 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 121306422 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 679329311 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 255341435 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 67772546 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 36892101 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2723405673 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2508908939 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 3097394 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 978157995 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 414914582 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1266457048 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.981045 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.973109 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 870637276 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 168 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 166 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 121366950 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 679350790 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 255350759 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 67967300 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 37114772 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2723579625 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 126 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2508981641 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 3091159 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 978310045 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 415071720 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 97 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1266865295 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.980464 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.972855 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 426262331 33.66% 33.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 201879469 15.94% 49.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 185440300 14.64% 64.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 153069981 12.09% 76.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 133127020 10.51% 86.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 81075751 6.40% 93.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 65263497 5.15% 98.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 15238482 1.20% 99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 5100217 0.40% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 426523141 33.67% 33.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 201951837 15.94% 49.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 185492394 14.64% 64.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 153160708 12.09% 76.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 133131866 10.51% 86.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 81031270 6.40% 93.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 65244416 5.15% 98.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 15224722 1.20% 99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 5104941 0.40% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1266457048 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1266865295 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2147356 11.64% 11.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 2143481 11.64% 11.64% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 11.64% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 11882629 64.43% 76.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 4412064 23.92% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 11871999 64.46% 76.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 4401590 23.90% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1643457358 65.50% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 108 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 284 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 162 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 38 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 641426814 25.57% 91.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 224024134 8.93% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1643559437 65.51% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 106 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 261 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 162 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 31 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.51% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 641411468 25.56% 91.07% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 224010136 8.93% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2508908939 # Type of FU issued
-system.cpu.iq.rate 1.884802 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 18442049 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.007351 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6303917077 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3700456251 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2412530118 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 1897292 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1213669 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 850482 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2526413076 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 937912 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 62601543 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2508981641 # Type of FU issued
+system.cpu.iq.rate 1.884268 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 18417070 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.007340 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 6304440735 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3700781380 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2412589185 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 1896071 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1214370 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 849902 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2526461544 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 937167 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 62583251 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 234733648 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 263681 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 107887 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 94612933 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 234755127 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 263530 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 107682 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 94622257 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 149 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1508556 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 167 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1505929 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 116469148 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 45249808 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1153798 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2865411802 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 8865893 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 679329311 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 255341435 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 296621 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 17062 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 107887 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 10351897 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 8549059 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 18900956 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2461552831 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 625050873 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 47356108 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 116496134 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 45259128 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1153276 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2865598045 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 8882954 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 679350790 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 255350759 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 126 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 296462 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 17110 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 107682 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 10363121 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 8561161 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 18924282 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2461596227 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 625038408 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 47385414 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 142006007 # number of nop insts executed
-system.cpu.iew.exec_refs 844465652 # number of memory reference insts executed
-system.cpu.iew.exec_branches 300780520 # Number of branches executed
-system.cpu.iew.exec_stores 219414779 # Number of stores executed
-system.cpu.iew.exec_rate 1.849226 # Inst execution rate
-system.cpu.iew.wb_sent 2441340597 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2413380600 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1388547079 # num instructions producing a value
-system.cpu.iew.wb_consumers 1764258867 # num instructions consuming a value
+system.cpu.iew.exec_nop 142018294 # number of nop insts executed
+system.cpu.iew.exec_refs 844427141 # number of memory reference insts executed
+system.cpu.iew.exec_branches 300792164 # Number of branches executed
+system.cpu.iew.exec_stores 219388733 # Number of stores executed
+system.cpu.iew.exec_rate 1.848681 # Inst execution rate
+system.cpu.iew.wb_sent 2441396740 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2413439087 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1388573479 # num instructions producing a value
+system.cpu.iew.wb_consumers 1764243384 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.813037 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.787043 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.812515 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.787065 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 824496541 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 824671147 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 16069169 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1149987900 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.582434 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.513328 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 16085857 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1150369161 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.581910 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.512649 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 636582703 55.36% 55.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 174528815 15.18% 70.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 86154838 7.49% 78.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 53696009 4.67% 82.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 34510870 3.00% 85.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 25214106 2.19% 87.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 21871895 1.90% 89.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 22921084 1.99% 91.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 94507580 8.22% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 636844570 55.36% 55.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 174611268 15.18% 70.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 86171312 7.49% 78.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 53631613 4.66% 82.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 34569452 3.01% 85.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 25367501 2.21% 87.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 21831937 1.90% 89.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 22907604 1.99% 91.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 94433904 8.21% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1149987900 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1150369161 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1819780126 # Number of instructions committed
system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions.
system.cpu.commit.function_calls 16767440 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 94507580 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 94433904 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3613977787 # The number of ROB reads
-system.cpu.rob.rob_writes 5405122718 # The number of ROB writes
-system.cpu.timesIdled 818240 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 64668748 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3614607330 # The number of ROB reads
+system.cpu.rob.rob_writes 5405498913 # The number of ROB writes
+system.cpu.timesIdled 817784 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 64676651 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
-system.cpu.cpi 0.766758 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.766758 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.304192 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.304192 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3317304663 # number of integer regfile reads
-system.cpu.int_regfile_writes 1931628776 # number of integer regfile writes
-system.cpu.fp_regfile_reads 30090 # number of floating regfile reads
-system.cpu.fp_regfile_writes 557 # number of floating regfile writes
+system.cpu.cpi 0.766998 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.766998 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.303785 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.303785 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3317361939 # number of integer regfile reads
+system.cpu.int_regfile_writes 1931707111 # number of integer regfile writes
+system.cpu.fp_regfile_reads 30073 # number of floating regfile reads
+system.cpu.fp_regfile_writes 529 # number of floating regfile writes
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 1 # number of replacements
-system.cpu.icache.tagsinuse 772.264197 # Cycle average of tags in use
-system.cpu.icache.total_refs 390708412 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 963 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 405720.053998 # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 776.168102 # Cycle average of tags in use
+system.cpu.icache.total_refs 390786293 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 969 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 403288.228070 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 772.264197 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.377082 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.377082 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 390708412 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 390708412 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 390708412 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 390708412 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 390708412 # number of overall hits
-system.cpu.icache.overall_hits::total 390708412 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1482 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1482 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1482 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1482 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1482 # number of overall misses
-system.cpu.icache.overall_misses::total 1482 # number of overall misses
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+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49500 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31718.737826 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31718.737826 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31718.737826 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31718.737826 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 12309965 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 5809756 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 734892 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.767276 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 89.300335 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.750713 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 89.196979 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3725054 # number of writebacks
-system.cpu.dcache.writebacks::total 3725054 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3985636 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 3985636 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3198598 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 3198598 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7184234 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7184234 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7184234 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7184234 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296792 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7296792 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883566 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1883566 # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks 3724718 # number of writebacks
+system.cpu.dcache.writebacks::total 3724718 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3983366 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 3983366 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3198630 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 3198630 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 7181996 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7181996 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 7181996 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 7181996 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296577 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 7296577 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883555 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1883555 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9180358 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9180358 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9180358 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9180358 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 159255490500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 159255490500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71503545346 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 71503545346 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 429500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 429500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230759035846 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 230759035846 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230759035846 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 230759035846 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013268 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013268 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data 9180132 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9180132 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9180132 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9180132 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 159251608500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 159251608500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71602703007 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 71602703007 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 47500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 47500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230854311507 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 230854311507 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230854311507 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 230854311507 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013267 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013267 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.012917 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.012917 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21825.411839 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21825.411839 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37961.794461 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37961.794461 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 429500 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 429500 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25136.169618 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25136.169618 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25136.169618 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25136.169618 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21825.522913 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21825.522913 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38014.660048 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38014.660048 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 47500 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 47500 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25147.166893 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25147.166893 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25147.166893 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25147.166893 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.517386 # Number of seconds simulated
-sim_ticks 517386177000 # Number of ticks simulated
-final_tick 517386177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.517371 # Number of seconds simulated
+sim_ticks 517371024000 # Number of ticks simulated
+final_tick 517371024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 165493 # Simulator instruction rate (inst/s)
-host_op_rate 184620 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 55435711 # Simulator tick rate (ticks/s)
-host_mem_usage 502788 # Number of bytes of host memory used
-host_seconds 9333.08 # Real time elapsed on the host
+host_inst_rate 170437 # Simulator instruction rate (inst/s)
+host_op_rate 190135 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 57090080 # Simulator tick rate (ticks/s)
+host_mem_usage 485276 # Number of bytes of host memory used
+host_seconds 9062.36 # Real time elapsed on the host
sim_insts 1544563023 # Number of instructions simulated
sim_ops 1723073835 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 48000 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 143728256 # Number of bytes read from this memory
-system.physmem.bytes_read::total 143776256 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 48000 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 48000 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 70436224 # Number of bytes written to this memory
-system.physmem.bytes_written::total 70436224 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 750 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2245754 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2246504 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1100566 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1100566 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 92774 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 277796861 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 277889635 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 92774 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 92774 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 136138589 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 136138589 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 136138589 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 92774 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 277796861 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 414028224 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 2246504 # Total number of read requests seen
-system.physmem.writeReqs 1100566 # Total number of write requests seen
-system.physmem.cpureqs 3350665 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 143776256 # Total number of bytes read from memory
-system.physmem.bytesWritten 70436224 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 143776256 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 70436224 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 651 # Number of read reqs serviced by write Q
+system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 143734144 # Number of bytes read from this memory
+system.physmem.bytes_read::total 143782208 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 48064 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 48064 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 70446784 # Number of bytes written to this memory
+system.physmem.bytes_written::total 70446784 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 751 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 2245846 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2246597 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1100731 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1100731 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 92900 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 277816378 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 277909279 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 92900 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 92900 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 136162987 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 136162987 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 136162987 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 92900 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 277816378 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 414072265 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 2246597 # Total number of read requests seen
+system.physmem.writeReqs 1100731 # Total number of write requests seen
+system.physmem.cpureqs 3350452 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 143782208 # Total number of bytes read from memory
+system.physmem.bytesWritten 70446784 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 143782208 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 70446784 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 642 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 141458 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 139475 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 141540 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 141707 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 142337 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 139999 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 141291 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 140517 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 138551 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 136478 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 140625 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 140699 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 141026 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 139159 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 139234 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 141757 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 69121 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 68349 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 69146 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 69473 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 69281 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 68946 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 69052 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 68358 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 67825 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 67029 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 69533 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 69302 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 69105 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 68630 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 141495 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 139690 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 141603 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 141749 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 142295 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 140068 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 141091 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 140693 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 138519 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 136203 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 140642 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 140693 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 141066 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 139208 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 139271 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 141669 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 69094 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 68448 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 69171 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 69468 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 69338 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 68952 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 69046 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 68406 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 67828 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 66957 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 69534 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 69263 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 69109 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 68653 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 68505 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 68911 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 68959 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 3595 # Number of times wr buffer was full causing retry
-system.physmem.totGap 517386097500 # Total gap between requests
+system.physmem.numWrRetry 3124 # Number of times wr buffer was full causing retry
+system.physmem.totGap 517370944500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 2246504 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 1104161 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1563469 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 451045 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 162632 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 68688 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see
+system.physmem.readPktSize::6 2246597 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 1100731 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 1563680 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 451075 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 162592 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 68583 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 44097 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 47155 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 47729 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 47801 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 47826 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 47832 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 47832 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 47832 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 47832 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 47851 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 47851 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 47851 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 47851 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 47851 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 47851 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 47851 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 47850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 3754 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 696 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 122 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 25 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 19 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 19 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 19 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 51687050307 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 131176334057 # Sum of mem lat for all requests
-system.physmem.totBusLat 11229265000 # Total cycles spent in databus access
-system.physmem.totBankLat 68260018750 # Total cycles spent in bank access
-system.physmem.avgQLat 23014.44 # Average queueing delay per request
-system.physmem.avgBankLat 30393.81 # Average bank access latency per request
+system.physmem.wrQLenPdf::0 44125 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 47135 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 47739 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 47809 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 47829 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 47835 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 47837 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 47838 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 47840 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 47858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 47857 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 47857 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 47857 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 3733 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 723 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 119 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 49 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 29 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 21 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see
+system.physmem.totQLat 51812524750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 131293078500 # Sum of mem lat for all requests
+system.physmem.totBusLat 11229775000 # Total cycles spent in databus access
+system.physmem.totBankLat 68250778750 # Total cycles spent in bank access
+system.physmem.avgQLat 23069.26 # Average queueing delay per request
+system.physmem.avgBankLat 30388.31 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 58408.25 # Average memory access latency
-system.physmem.avgRdBW 277.89 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 136.14 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 277.89 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 136.14 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 58457.57 # Average memory access latency
+system.physmem.avgRdBW 277.91 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 136.16 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 277.91 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 136.16 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.23 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.25 # Average read queue length over time
-system.physmem.avgWrQLen 10.38 # Average write queue length over time
-system.physmem.readRowHits 827421 # Number of row buffer hits during reads
-system.physmem.writeRowHits 271011 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 36.84 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 24.62 # Row buffer hit rate for writes
-system.physmem.avgGap 154578.81 # Average gap between requests
-system.cpu.branchPred.lookups 303247532 # Number of BP lookups
-system.cpu.branchPred.condPredicted 249450034 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 15218023 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 175041543 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 161435617 # Number of BTB hits
+system.physmem.avgWrQLen 10.92 # Average write queue length over time
+system.physmem.readRowHits 827855 # Number of row buffer hits during reads
+system.physmem.writeRowHits 271156 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 36.86 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 24.63 # Row buffer hit rate for writes
+system.physmem.avgGap 154562.37 # Average gap between requests
+system.cpu.branchPred.lookups 303290886 # Number of BP lookups
+system.cpu.branchPred.condPredicted 249488582 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 15222231 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 174596646 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 161469311 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 92.227030 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 17558020 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 197 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 92.481336 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 17557313 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 202 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 1034772355 # number of cpu cycles simulated
+system.cpu.numCycles 1034742049 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 298171037 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2186159989 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 303247532 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 178993637 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 435067157 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 87822274 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 155469980 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 663 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 288529454 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 5728473 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 958589014 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.523348 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.213310 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 298209547 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2186343540 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 303290886 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 179026624 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 435120674 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 87852250 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 155399906 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 380 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 288562414 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 5732154 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 958634216 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.523474 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.213325 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 523521931 54.61% 54.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 25504837 2.66% 57.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 39086427 4.08% 61.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 48350867 5.04% 66.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 43002654 4.49% 70.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 46446539 4.85% 75.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 38408277 4.01% 79.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 18709630 1.95% 81.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 175557852 18.31% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 523513675 54.61% 54.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 25518990 2.66% 57.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 39095186 4.08% 61.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 48349741 5.04% 66.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 43010158 4.49% 70.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 46440341 4.84% 75.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 38425121 4.01% 79.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 18710957 1.95% 81.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 175570047 18.31% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 958589014 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.293057 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.112697 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 329732299 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 133726687 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 405163333 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 20087198 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 69879497 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 46055159 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 678 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 2366957956 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2458 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 69879497 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 353264569 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 63487571 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 18775 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 400193247 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 71745355 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2304463172 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 133379 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 5038858 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 58609164 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 17 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2279851599 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 10642208168 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 10642204755 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 3413 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 958634216 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.293108 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.112936 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 329763250 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 133666994 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 405221512 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 20079412 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 69903048 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 46058380 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 679 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 2367190993 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2433 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 69903048 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 353304996 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 63447183 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 15614 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 400231748 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 71731627 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2304653779 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 133097 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 5040028 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 58589233 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 7 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 2280042978 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 10643127773 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 10643124880 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 2893 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 573531669 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 681 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 678 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 158828994 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 624462299 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 220966139 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 86157140 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 71007424 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2201342631 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 714 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2018151759 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 3999657 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 473702297 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1125076843 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 544 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 958589014 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.105336 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.906417 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 573723048 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 497 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 494 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 158827938 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 624515157 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 220983969 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 86332349 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 71315853 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2201513470 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 522 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2018112827 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 4002858 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 473886256 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1126241029 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 958634216 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.105196 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.906381 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 277560944 28.96% 28.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 151408943 15.79% 44.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 161184316 16.81% 61.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 119741050 12.49% 74.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 124054843 12.94% 87.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 73850392 7.70% 94.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 38407609 4.01% 98.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 9813288 1.02% 99.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 2567629 0.27% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 277594004 28.96% 28.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 151404549 15.79% 44.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 161201477 16.82% 61.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 119812250 12.50% 74.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 123999377 12.94% 87.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 73820536 7.70% 94.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 38419650 4.01% 98.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 9808498 1.02% 99.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 2573875 0.27% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 958589014 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 958634216 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 872793 3.65% 3.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 5710 0.02% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 18283969 76.42% 80.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 4762893 19.91% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 872312 3.66% 3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 5645 0.02% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 18268766 76.62% 80.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 4697940 19.70% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1236667909 61.28% 61.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 925774 0.05% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1236677496 61.28% 61.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 926030 0.05% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 51 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 33 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 24 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 5 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 587469094 29.11% 90.43% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 193088896 9.57% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 587482532 29.11% 90.44% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 193026708 9.56% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2018151759 # Type of FU issued
-system.cpu.iq.rate 1.950334 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 23925365 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.011855 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 5022817228 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2675235301 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1957490366 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 326 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 628 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 132 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2042076961 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 163 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 64626006 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2018112827 # Type of FU issued
+system.cpu.iq.rate 1.950354 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 23844663 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.011815 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 5022707128 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2675590256 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1957438118 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 556 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2041957357 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 64629974 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 138535530 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 270863 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 192819 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 46119094 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 138588388 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 271831 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 192988 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 46136924 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 4653355 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 4659196 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 69879497 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 28935964 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1499081 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2201343583 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 6151222 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 624462299 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 220966139 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 652 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 473850 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 90091 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 192819 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 8153540 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 9614603 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 17768143 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1988132356 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 573881676 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 30019403 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 69903048 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 28888784 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1501235 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2201514122 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 6139547 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 624515157 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 220983969 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 460 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 475783 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 89669 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 192988 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 8156378 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 9617829 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 17774207 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1988116656 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 573901246 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 29996171 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 238 # number of nop insts executed
-system.cpu.iew.exec_refs 764075762 # number of memory reference insts executed
-system.cpu.iew.exec_branches 238335526 # Number of branches executed
-system.cpu.iew.exec_stores 190194086 # Number of stores executed
-system.cpu.iew.exec_rate 1.921323 # Inst execution rate
-system.cpu.iew.wb_sent 1965930006 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1957490498 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1296385031 # num instructions producing a value
-system.cpu.iew.wb_consumers 2061135459 # num instructions consuming a value
+system.cpu.iew.exec_nop 130 # number of nop insts executed
+system.cpu.iew.exec_refs 764045166 # number of memory reference insts executed
+system.cpu.iew.exec_branches 238330381 # Number of branches executed
+system.cpu.iew.exec_stores 190143920 # Number of stores executed
+system.cpu.iew.exec_rate 1.921365 # Inst execution rate
+system.cpu.iew.wb_sent 1965882705 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1957438221 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1296419261 # num instructions producing a value
+system.cpu.iew.wb_consumers 2061223018 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.891711 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.628966 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.891716 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.628956 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 478367692 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 478537797 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 15217365 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 888709517 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.938849 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.727981 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 15221576 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 888731168 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.938802 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.727796 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 401294450 45.15% 45.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 192123349 21.62% 66.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 72572906 8.17% 74.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 35244916 3.97% 78.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 18969010 2.13% 81.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 30763331 3.46% 84.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 20056672 2.26% 86.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 11441847 1.29% 88.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 106243036 11.95% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 401249220 45.15% 45.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 192209497 21.63% 66.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 72554391 8.16% 74.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 35214687 3.96% 78.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 19001350 2.14% 81.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 30768614 3.46% 84.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 20079948 2.26% 86.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 11444333 1.29% 88.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 106209128 11.95% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 888709517 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 888731168 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 106243036 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 106209128 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2983907427 # The number of ROB reads
-system.cpu.rob.rob_writes 4472910463 # The number of ROB writes
-system.cpu.timesIdled 1017511 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 76183341 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 2984133091 # The number of ROB reads
+system.cpu.rob.rob_writes 4473274350 # The number of ROB writes
+system.cpu.timesIdled 1017651 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 76107833 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated
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-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 673107596 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 673107596 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 673107596 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 673107596 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022929 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.022929 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032095 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.032095 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025279 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025279 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.025279 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.025279 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28137.189345 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 28137.189345 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41403.404204 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41403.404204 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62666.666667 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62666.666667 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 32455.763736 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 32455.763736 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32455.763736 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 32455.763736 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 26327984 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 1057907 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1182334 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 64553 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.267806 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 16.388193 # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 673116163 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 673116163 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 673116163 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 673116163 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022933 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.022933 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032092 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.032092 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.025281 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.025281 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.025281 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.025281 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28139.570735 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28139.570735 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41459.389561 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41459.389561 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 141166.666667 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 141166.666667 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 32474.859624 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 32474.859624 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32474.859624 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 32474.859624 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 26343962 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 1054966 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1182360 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 64552 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.280830 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 16.342886 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3781250 # number of writebacks
-system.cpu.dcache.writebacks::total 3781250 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767955 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 3767955 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645642 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 3645642 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 3781695 # number of writebacks
+system.cpu.dcache.writebacks::total 3781695 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3769070 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 3769070 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645155 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 3645155 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7413597 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7413597 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7413597 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7413597 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708472 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7708472 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893450 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1893450 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9601922 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9601922 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9601922 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9601922 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186178488500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 186178488500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508071510 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508071510 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269686560010 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 269686560010 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269686560010 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 269686560010 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015401 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015401 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24152.450512 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24152.450512 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44103.658143 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44103.658143 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28086.726804 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28086.726804 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28086.726804 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28086.726804 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data 7414225 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7414225 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 7414225 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 7414225 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7709443 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 7709443 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893551 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1893551 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 9602994 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9602994 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9602994 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9602994 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186232562000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 186232562000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83589909224 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 83589909224 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269822471224 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 269822471224 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269822471224 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 269822471224 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015403 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015403 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010972 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010972 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014266 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.014266 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014266 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.014266 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24156.422455 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24156.422455 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44144.524876 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44144.524876 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28097.744435 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28097.744435 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28097.744435 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28097.744435 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 41622221000 # Number of ticks simulated
final_tick 41622221000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 156492 # Simulator instruction rate (inst/s)
-host_op_rate 156492 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 70874179 # Simulator tick rate (ticks/s)
-host_mem_usage 228076 # Number of bytes of host memory used
-host_seconds 587.27 # Real time elapsed on the host
+host_inst_rate 75517 # Simulator instruction rate (inst/s)
+host_op_rate 75517 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 34200879 # Simulator tick rate (ticks/s)
+host_mem_usage 228092 # Number of bytes of host memory used
+host_seconds 1216.99 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 4938 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 0 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 3236 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1202 # What read queue length does an incoming req see
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 0 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 3235 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1203 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 433 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 23375922 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 122137172 # Sum of mem lat for all requests
+system.physmem.totQLat 23405750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 122167000 # Sum of mem lat for all requests
system.physmem.totBusLat 24690000 # Total cycles spent in databus access
system.physmem.totBankLat 74071250 # Total cycles spent in bank access
-system.physmem.avgQLat 4733.88 # Average queueing delay per request
+system.physmem.avgQLat 4739.93 # Average queueing delay per request
system.physmem.avgBankLat 15000.25 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 24734.14 # Average memory access latency
+system.physmem.avgMemAccLat 24740.18 # Average memory access latency
system.physmem.avgRdBW 7.59 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 7.59 # Average consumed read bandwidth in MB/s
system.cpu.stage4.runCycles 53859732 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 64.700694 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 7635 # number of replacements
-system.cpu.icache.tagsinuse 1492.649363 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1492.649326 # Cycle average of tags in use
system.cpu.icache.total_refs 9945578 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 9520 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1044.703571 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1492.649363 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 1492.649326 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.728833 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.728833 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 9945578 # number of ReadReq hits
system.cpu.icache.demand_misses::total 11365 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 11365 # number of overall misses
system.cpu.icache.overall_misses::total 11365 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 259189500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 259189500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 259189500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 259189500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 259189500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 259189500 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 259175500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 259175500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 259175500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 259175500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 259175500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 259175500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 9956943 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 9956943 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 9956943 # number of demand (read+write) accesses
system.cpu.icache.demand_miss_rate::total 0.001141 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001141 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001141 # miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52826.315789 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52826.315789 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49261.727689 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49261.727689 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50023.391813 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 50023.391813 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50023.391813 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 50023.391813 # average overall mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49293.764302 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49293.764302 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50048.582996 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 50048.582996 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50048.582996 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 50048.582996 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 23426793000 # Number of ticks simulated
final_tick 23426793000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 213464 # Simulator instruction rate (inst/s)
-host_op_rate 213464 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 59405864 # Simulator tick rate (ticks/s)
-host_mem_usage 230136 # Number of bytes of host memory used
-host_seconds 394.35 # Real time elapsed on the host
+host_inst_rate 128339 # Simulator instruction rate (inst/s)
+host_op_rate 128339 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 35715987 # Simulator tick rate (ticks/s)
+host_mem_usage 230140 # Number of bytes of host memory used
+host_seconds 655.92 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
sim_ops 84179709 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 5228 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
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-system.physmem.writePktSize::6 0 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 3174 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1385 # What read queue length does an incoming req see
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+system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.rdQLenPdf::2 549 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 106 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 28657456 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 133887456 # Sum of mem lat for all requests
+system.physmem.totQLat 28652250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 133882250 # Sum of mem lat for all requests
system.physmem.totBusLat 26140000 # Total cycles spent in databus access
system.physmem.totBankLat 79090000 # Total cycles spent in bank access
-system.physmem.avgQLat 5481.53 # Average queueing delay per request
+system.physmem.avgQLat 5480.54 # Average queueing delay per request
system.physmem.avgBankLat 15128.16 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 25609.69 # Average memory access latency
+system.physmem.avgMemAccLat 25608.69 # Average memory access latency
system.physmem.avgRdBW 14.28 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 14.28 # Average consumed read bandwidth in MB/s
system.cpu.l2cache.avg_refs 2.367688 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 17.668263 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 2005.213140 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 2005.213141 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 381.714191 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.061194 # Average percentage of cache occupancy
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2166 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5228 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106921693 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23470923 # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 65567754 # number of ReadExReq MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 89038677 # number of overall MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 65567128 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266446 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.893411 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.293388 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266446 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.380523 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34918.906924 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50913.065076 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37011.812660 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38456.160704 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38456.160704 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34918.906924 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41107.422438 # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34918.906924 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41107.422438 # average overall mshr miss latency
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38455.793548 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34918.060418 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41106.978763 # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34918.060418 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41106.978763 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37482.176167 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 159 # number of replacements
system.cpu.dcache.tagsinuse 1459.874578 # Cycle average of tags in use
sim_ticks 74155951500 # Number of ticks simulated
final_tick 74155951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 108940 # Simulator instruction rate (inst/s)
-host_op_rate 119280 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 46885764 # Simulator tick rate (ticks/s)
-host_mem_usage 245224 # Number of bytes of host memory used
-host_seconds 1581.63 # Real time elapsed on the host
+host_inst_rate 102580 # Simulator instruction rate (inst/s)
+host_op_rate 112316 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44148416 # Simulator tick rate (ticks/s)
+host_mem_usage 245240 # Number of bytes of host memory used
+host_seconds 1679.70 # Real time elapsed on the host
sim_insts 172303021 # Number of instructions simulated
sim_ops 188656503 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 131776 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 3811 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 0 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
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+system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 2809 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 787 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 160 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 17813284 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 103885784 # Sum of mem lat for all requests
+system.physmem.totQLat 17809500 # Total cycles spent in queuing delays
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system.physmem.totBusLat 19055000 # Total cycles spent in databus access
system.physmem.totBankLat 67017500 # Total cycles spent in bank access
-system.physmem.avgQLat 4674.18 # Average queueing delay per request
+system.physmem.avgQLat 4673.18 # Average queueing delay per request
system.physmem.avgBankLat 17585.28 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 27259.46 # Average memory access latency
+system.physmem.avgMemAccLat 27258.46 # Average memory access latency
system.physmem.avgRdBW 3.29 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 3.29 # Average consumed read bandwidth in MB/s
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2060 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1751 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 3811 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 78131980 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.502439 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869845 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.560911 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.502439 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940892 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.639322 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37928.145631 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45904.093333 # average ReadReq mshr miss latency
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33749.749071 # average ReadExReq mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37928.145631 # average overall mshr miss latency
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39895.796709 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33748.946097 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33748.946097 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37927.303883 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38434.394061 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38160.291262 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37927.303883 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38434.394061 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38160.291262 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 57 # number of replacements
system.cpu.dcache.tagsinuse 1410.136977 # Cycle average of tags in use
sim_ticks 82836235000 # Number of ticks simulated
final_tick 82836235000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 72340 # Simulator instruction rate (inst/s)
-host_op_rate 121249 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45372545 # Simulator tick rate (ticks/s)
+host_inst_rate 70076 # Simulator instruction rate (inst/s)
+host_op_rate 117454 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 43952394 # Simulator tick rate (ticks/s)
host_mem_usage 275820 # Number of bytes of host memory used
-host_seconds 1825.69 # Real time elapsed on the host
+host_seconds 1884.68 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
sim_ops 221362961 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 218368 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 5362 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 0 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 153 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 0 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 4169 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 943 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 199 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 15727084 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 132185834 # Sum of mem lat for all requests
+system.physmem.totQLat 15721750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 132180500 # Sum of mem lat for all requests
system.physmem.totBusLat 26795000 # Total cycles spent in databus access
system.physmem.totBankLat 89663750 # Total cycles spent in bank access
-system.physmem.avgQLat 2933.06 # Average queueing delay per request
+system.physmem.avgQLat 2932.07 # Average queueing delay per request
system.physmem.avgBankLat 16722.07 # Average bank access latency per request
system.physmem.avgBusLat 4997.20 # Average bus latency per request
-system.physmem.avgMemAccLat 24652.34 # Average memory access latency
+system.physmem.avgMemAccLat 24651.34 # Average memory access latency
system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3413 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1949 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5362 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 121268321 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18645617 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 139913938 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 121265541 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18645311 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 139910852 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1530153 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1530153 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49242500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49242500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 121268321 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67888117 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 189156438 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 121268321 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67888117 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 189156438 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49241002 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49241002 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 121265541 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67886313 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 189151854 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 121265541 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67886313 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 189151854 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496581 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929245 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.521721 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496581 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981370 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.605260 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35531.298271 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47323.901015 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36751.756764 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35530.483739 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47323.124365 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36750.946152 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31667.202572 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31667.202572 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35531.298271 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34832.281683 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35277.217083 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35531.298271 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34832.281683 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35277.217083 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31666.239228 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31666.239228 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35530.483739 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34831.356080 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35276.362178 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35530.483739 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34831.356080 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35276.362178 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 56 # number of replacements
system.cpu.dcache.tagsinuse 1416.460930 # Cycle average of tags in use
sim_ticks 1870325497500 # Number of ticks simulated
final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2356651 # Simulator instruction rate (inst/s)
-host_op_rate 2356650 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 69796056257 # Simulator tick rate (ticks/s)
-host_mem_usage 349376 # Number of bytes of host memory used
-host_seconds 26.80 # Real time elapsed on the host
+host_inst_rate 3609656 # Simulator instruction rate (inst/s)
+host_op_rate 3609654 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 106905838632 # Simulator tick rate (ticks/s)
+host_mem_usage 305660 # Number of bytes of host memory used
+host_seconds 17.50 # Real time elapsed on the host
sim_insts 63151114 # Number of instructions simulated
sim_ops 63151114 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 760896 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 0 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 0 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 0 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 0 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem.totBusLat 0 # Total cycles spent in databus access
sim_ticks 1829330593000 # Number of ticks simulated
final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1133415 # Simulator instruction rate (inst/s)
-host_op_rate 1133413 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 34534714924 # Simulator tick rate (ticks/s)
-host_mem_usage 347332 # Number of bytes of host memory used
-host_seconds 52.97 # Real time elapsed on the host
+host_inst_rate 3233953 # Simulator instruction rate (inst/s)
+host_op_rate 3233951 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 98537371937 # Simulator tick rate (ticks/s)
+host_mem_usage 303612 # Number of bytes of host memory used
+host_seconds 18.56 # Real time elapsed on the host
sim_insts 60037737 # Number of instructions simulated
sim_ops 60037737 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 0 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 0 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 0 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 0 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem.totBusLat 0 # Total cycles spent in databus access
system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
system.cpu.dcache.writebacks::total 833491 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 2042707 # number of replacements
-system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14038405 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 2043219 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 6.870729 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 7807769 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7807769 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 13655968 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 13655968 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 13655968 # number of overall hits
-system.cpu.dcache.overall_hits::total 13655968 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1721709 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1721709 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses
-system.cpu.dcache.overall_misses::total 2026074 # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
-system.cpu.dcache.writebacks::total 833491 # number of writebacks
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 1.952724 # Number of seconds simulated
-sim_ticks 1952724269500 # Number of ticks simulated
-final_tick 1952724269500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.954691 # Number of seconds simulated
+sim_ticks 1954691371500 # Number of ticks simulated
+final_tick 1954691371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1678586 # Simulator instruction rate (inst/s)
-host_op_rate 1678585 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 53851852439 # Simulator tick rate (ticks/s)
-host_mem_usage 333452 # Number of bytes of host memory used
-host_seconds 36.26 # Real time elapsed on the host
-sim_insts 60867235 # Number of instructions simulated
-sim_ops 60867235 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 830208 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24725568 # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 35200 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 438144 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28680000 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 830208 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 35200 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 865408 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7698816 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7698816 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 12972 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 386337 # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 550 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 6846 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 448125 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 120294 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 120294 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 425154 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 12662089 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1357529 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 18026 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 224376 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 14687173 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 425154 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 18026 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 443180 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3942603 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3942603 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3942603 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 425154 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 12662089 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1357529 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 18026 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 224376 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 18629776 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 448125 # Total number of read requests seen
-system.physmem.writeReqs 120294 # Total number of write requests seen
-system.physmem.cpureqs 598443 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28680000 # Total number of bytes read from memory
-system.physmem.bytesWritten 7698816 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28680000 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7698816 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 68 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 6945 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 28344 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 28173 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 28017 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 27785 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 27951 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 27964 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 28022 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 27886 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 28437 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 28288 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 28341 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 28051 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 27575 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 27797 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 27570 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 27856 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7821 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7610 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7567 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 7380 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7470 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7435 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7506 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 7435 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 7992 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7835 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7874 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 7588 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7131 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 7029 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 7371 # Track writes on a per bank basis
+host_inst_rate 798728 # Simulator instruction rate (inst/s)
+host_op_rate 798728 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 26318676085 # Simulator tick rate (ticks/s)
+host_mem_usage 332420 # Number of bytes of host memory used
+host_seconds 74.27 # Real time elapsed on the host
+sim_insts 59321614 # Number of instructions simulated
+sim_ops 59321614 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 829376 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24757440 # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 34176 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 389696 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28661504 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 829376 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 34176 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7676992 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7676992 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 12959 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 386835 # Number of read requests responded to by this memory
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+system.physmem.num_reads::cpu1.inst 534 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 6089 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 447836 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 119953 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 119953 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 424300 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 12665652 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1356130 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 17484 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 199364 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 14662931 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 424300 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 17484 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 441784 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3927470 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3927470 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3927470 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 424300 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 12665652 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::cpu1.inst 17484 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::total 18590401 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 447836 # Total number of read requests seen
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+system.physmem.bytesRead 28661504 # Total number of bytes read from memory
+system.physmem.bytesWritten 7676992 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28661504 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7676992 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 3161 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 28180 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 28120 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 28097 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 27826 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 27944 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 27900 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 27858 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 27869 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 28342 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 28141 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 28250 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 28016 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 27813 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 27987 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 27674 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 27750 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7637 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::2 7585 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 7374 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7488 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7379 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7353 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 7437 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7887 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 7685 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7821 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 7507 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7382 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 7492 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7142 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7280 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1406 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1952670553500 # Total gap between requests
+system.physmem.numWrRetry 1948 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1954684300500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 448125 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 121700 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 6945 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 407346 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4785 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 3654 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 2222 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3126 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2960 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::7 2681 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 2639 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::11 1459 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::14 1370 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 1401 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::17 1508 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 906 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see
+system.physmem.readPktSize::6 447836 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 119953 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 407021 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3696 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::2 4297 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::4 4866 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 5206 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 5215 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 5216 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 5218 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 5230 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 5230 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 5230 # What write queue length does an incoming req see
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+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8512910554 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 8512910554 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 8524904803 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 8524904803 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 8524904803 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8524904803 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68842.329545 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 68842.329545 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203911.028591 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 203911.028591 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68932.465517 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 68932.465517 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204873.665624 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 204873.665624 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204306.782414 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 204306.782414 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204306.782414 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 204306.782414 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 7490982 # DTB read hits
-system.cpu0.dtb.read_misses 7443 # DTB read misses
+system.cpu0.dtb.read_hits 8631552 # DTB read hits
+system.cpu0.dtb.read_misses 7447 # DTB read misses
system.cpu0.dtb.read_acv 210 # DTB read access violations
-system.cpu0.dtb.read_accesses 490673 # DTB read accesses
-system.cpu0.dtb.write_hits 5068153 # DTB write hits
+system.cpu0.dtb.read_accesses 490676 # DTB read accesses
+system.cpu0.dtb.write_hits 6044616 # DTB write hits
system.cpu0.dtb.write_misses 813 # DTB write misses
system.cpu0.dtb.write_acv 134 # DTB write access violations
system.cpu0.dtb.write_accesses 187452 # DTB write accesses
-system.cpu0.dtb.data_hits 12559135 # DTB hits
-system.cpu0.dtb.data_misses 8256 # DTB misses
+system.cpu0.dtb.data_hits 14676168 # DTB hits
+system.cpu0.dtb.data_misses 8260 # DTB misses
system.cpu0.dtb.data_acv 344 # DTB access violations
-system.cpu0.dtb.data_accesses 678125 # DTB accesses
-system.cpu0.itb.fetch_hits 3503456 # ITB hits
+system.cpu0.dtb.data_accesses 678128 # DTB accesses
+system.cpu0.itb.fetch_hits 3853435 # ITB hits
system.cpu0.itb.fetch_misses 3871 # ITB misses
system.cpu0.itb.fetch_acv 184 # ITB acv
-system.cpu0.itb.fetch_accesses 3507327 # ITB accesses
+system.cpu0.itb.fetch_accesses 3857306 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 3904305293 # number of cpu cycles simulated
+system.cpu0.numCycles 3908211536 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 47706703 # Number of instructions committed
-system.cpu0.committedOps 47706703 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 44241786 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 211423 # Number of float alu accesses
-system.cpu0.num_func_calls 1201591 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 5601417 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 44241786 # number of integer instructions
-system.cpu0.num_fp_insts 211423 # number of float instructions
-system.cpu0.num_int_register_reads 60797943 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 32968604 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 102697 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 104564 # number of times the floating registers were written
-system.cpu0.num_mem_refs 12599388 # number of memory refs
-system.cpu0.num_load_insts 7518173 # Number of load instructions
-system.cpu0.num_store_insts 5081215 # Number of store instructions
-system.cpu0.num_idle_cycles 3700976170.173713 # Number of idle cycles
-system.cpu0.num_busy_cycles 203329122.826288 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.052078 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.947922 # Percentage of idle cycles
+system.cpu0.committedInsts 54061829 # Number of instructions committed
+system.cpu0.committedOps 54061829 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 50032862 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 294101 # Number of float alu accesses
+system.cpu0.num_func_calls 1426501 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 6236445 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 50032862 # number of integer instructions
+system.cpu0.num_fp_insts 294101 # number of float instructions
+system.cpu0.num_int_register_reads 68513770 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 37070851 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 143419 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 146520 # number of times the floating registers were written
+system.cpu0.num_mem_refs 14722187 # number of memory refs
+system.cpu0.num_load_insts 8662865 # Number of load instructions
+system.cpu0.num_store_insts 6059322 # Number of store instructions
+system.cpu0.num_idle_cycles 3679287399.643625 # Number of idle cycles
+system.cpu0.num_busy_cycles 228924136.356375 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.058575 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.941425 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6787 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 165132 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 56916 40.19% 40.19% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1973 1.39% 41.67% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 418 0.30% 41.97% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 82194 58.03% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 141632 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 56372 49.08% 49.08% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 418 0.36% 51.28% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 55954 48.72% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 114848 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1900150859000 97.34% 97.34% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 92973000 0.00% 97.34% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 760723500 0.04% 97.38% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 310562000 0.02% 97.40% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 50837499000 2.60% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1952152616500 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.990442 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce 6369 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 202997 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 72749 40.62% 40.62% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21 131 0.07% 40.70% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22 1975 1.10% 41.80% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 104220 58.20% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 179081 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 71382 49.27% 49.27% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22 1975 1.36% 50.73% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 71376 49.27% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 144870 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1898301273000 97.14% 97.14% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 93023500 0.00% 97.15% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 762236500 0.04% 97.19% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 5235500 0.00% 97.19% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 54943969500 2.81% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1954105738000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.981209 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.680755 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.810890 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31 0.684859 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total 0.808964 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 222 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed
-system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed
-system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 3074 2.05% 2.39% # number of callpals executed
-system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed
-system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 134771 89.88% 92.30% # number of callpals executed
-system.cpu0.kern.callpal::rdps 6676 4.45% 96.75% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed
-system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed
-system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed
-system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed
-system.cpu0.kern.callpal::rti 4338 2.89% 99.66% # number of callpals executed
-system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed
-system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 149953 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 6892 # number of protection mode switches
+system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed
+system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed
+system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed
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+system.cpu0.kern.callpal::rti 4751 2.52% 99.73% # number of callpals executed
+system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed
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+system.cpu0.kern.callpal::total 188224 # number of callpals executed
+system.cpu0.kern.mode_switch::kernel 7304 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1283
system.cpu0.kern.mode_good::user 1283
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.186158 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.175657 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.313884 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1948377502000 99.82% 99.82% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 3456174500 0.18% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total 0.298824 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 1950347295500 99.82% 99.82% # number of ticks spent at the given mode
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system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3075 # number of times the context was actually changed
+system.cpu0.kern.swap_context 3897 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu0.icache.replacements 699703 # number of replacements
-system.cpu0.icache.tagsinuse 509.161264 # Cycle average of tags in use
-system.cpu0.icache.total_refs 47014995 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 700215 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 67.143656 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 32599184000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 509.161264 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.994456 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.994456 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 47014995 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 47014995 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 47014995 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 47014995 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 47014995 # number of overall hits
-system.cpu0.icache.overall_hits::total 47014995 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 700308 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 700308 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 700308 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 700308 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 700308 # number of overall misses
-system.cpu0.icache.overall_misses::total 700308 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9851397000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 9851397000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 9851397000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 9851397000 # number of demand (read+write) miss cycles
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-system.cpu0.icache.overall_miss_latency::total 9851397000 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 47715303 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 47715303 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 47715303 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 47715303 # number of demand (read+write) accesses
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-system.cpu0.icache.overall_accesses::total 47715303 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014677 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.014677 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014677 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.014677 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014677 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.014677 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14067.234702 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14067.234702 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14067.234702 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14067.234702 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14067.234702 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14067.234702 # average overall miss latency
+system.cpu0.icache.replacements 915312 # number of replacements
+system.cpu0.icache.tagsinuse 509.170565 # Cycle average of tags in use
+system.cpu0.icache.total_refs 53154487 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 915824 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 58.040068 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 32594703000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst 509.170565 # Average occupied blocks per requestor
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+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13115.798923 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5834.883721 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5834.883721 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23046.581213 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 23046.581213 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23046.581213 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 23046.581213 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 680601 # number of writebacks
-system.cpu0.dcache.writebacks::total 680601 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939643 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 939643 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251886 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 251886 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13649 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13649 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5418 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 5418 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 1191529 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 1191529 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 1191529 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 1191529 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19241816500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19241816500 # number of ReadReq MSHR miss cycles
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121870500 # number of LoadLockedReq MSHR miss cycles
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-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26380720500 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465344500 # number of ReadReq MSHR uncacheable cycles
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-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2274931000 # number of WriteReq MSHR uncacheable cycles
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-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3740275500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127856 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127856 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051285 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051285 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088509 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088509 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035260 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035260 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.097183 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.097183 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20477.794758 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20477.794758 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28341.805420 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28341.805420 # average WriteReq mshr miss latency
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-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8928.895890 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5610.926541 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5610.926541 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 789805 # number of writebacks
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3557617500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122521 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122521 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049738 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049738 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086551 # mshr miss rate for LoadLockedReq accesses
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+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002238 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002238 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092752 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.092752 # mshr miss rate for demand accesses
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+system.cpu0.dcache.overall_mshr_miss_rate::total 0.092752 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 19614.825841 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19614.825841 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26142.720441 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26142.720441 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11115.798923 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11115.798923 # average LoadLockedReq mshr miss latency
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+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21046.581213 # average overall mshr miss latency
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system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 2417694 # DTB read hits
+system.cpu1.dtb.read_hits 1047086 # DTB read hits
system.cpu1.dtb.read_misses 2992 # DTB read misses
system.cpu1.dtb.read_acv 0 # DTB read access violations
system.cpu1.dtb.read_accesses 239363 # DTB read accesses
-system.cpu1.dtb.write_hits 1754404 # DTB write hits
+system.cpu1.dtb.write_hits 650181 # DTB write hits
system.cpu1.dtb.write_misses 341 # DTB write misses
system.cpu1.dtb.write_acv 29 # DTB write access violations
system.cpu1.dtb.write_accesses 105247 # DTB write accesses
-system.cpu1.dtb.data_hits 4172098 # DTB hits
+system.cpu1.dtb.data_hits 1697267 # DTB hits
system.cpu1.dtb.data_misses 3333 # DTB misses
system.cpu1.dtb.data_acv 29 # DTB access violations
system.cpu1.dtb.data_accesses 344610 # DTB accesses
-system.cpu1.itb.fetch_hits 1961503 # ITB hits
+system.cpu1.itb.fetch_hits 1487534 # ITB hits
system.cpu1.itb.fetch_misses 1216 # ITB misses
system.cpu1.itb.fetch_acv 0 # ITB acv
-system.cpu1.itb.fetch_accesses 1962719 # ITB accesses
+system.cpu1.itb.fetch_accesses 1488750 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 3905448539 # number of cpu cycles simulated
+system.cpu1.numCycles 3909382743 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 13160532 # Number of instructions committed
-system.cpu1.committedOps 13160532 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 12141335 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 171917 # Number of float alu accesses
-system.cpu1.num_func_calls 411397 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 1307333 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 12141335 # number of integer instructions
-system.cpu1.num_fp_insts 171917 # number of float instructions
-system.cpu1.num_int_register_reads 16724790 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 8912820 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 89976 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 91834 # number of times the floating registers were written
-system.cpu1.num_mem_refs 4195541 # number of memory refs
-system.cpu1.num_load_insts 2431931 # Number of load instructions
-system.cpu1.num_store_insts 1763610 # Number of store instructions
-system.cpu1.num_idle_cycles 3855992964.998025 # Number of idle cycles
-system.cpu1.num_busy_cycles 49455574.001975 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.012663 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.987337 # Percentage of idle cycles
+system.cpu1.committedInsts 5259785 # Number of instructions committed
+system.cpu1.committedOps 5259785 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 4928462 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses
+system.cpu1.num_func_calls 156703 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 508760 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 4928462 # number of integer instructions
+system.cpu1.num_fp_insts 34031 # number of float instructions
+system.cpu1.num_int_register_reads 6858583 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 3715950 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written
+system.cpu1.num_mem_refs 1706720 # number of memory refs
+system.cpu1.num_load_insts 1053093 # Number of load instructions
+system.cpu1.num_store_insts 653627 # Number of store instructions
+system.cpu1.num_idle_cycles 3890042761.998010 # Number of idle cycles
+system.cpu1.num_busy_cycles 19339981.001990 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.004947 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.995053 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2696 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 78331 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 26451 38.35% 38.35% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1967 2.85% 41.20% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 500 0.72% 41.92% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 40063 58.08% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 68981 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 25618 48.15% 48.15% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1967 3.70% 51.85% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 500 0.94% 52.79% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 25118 47.21% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 53203 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1909244973500 97.77% 97.77% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 705660500 0.04% 97.81% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 346600000 0.02% 97.83% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 42426277500 2.17% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1952723511500 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.968508 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce 2297 # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei 35535 # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0 8961 31.73% 31.73% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22 1969 6.97% 38.70% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30 88 0.31% 39.01% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31 17223 60.99% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 28241 # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0 8951 45.05% 45.05% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22 1969 9.91% 54.95% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 88 0.44% 55.40% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 8863 44.60% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 19871 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1917858613000 98.12% 98.12% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 705516000 0.04% 98.15% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 59546500 0.00% 98.15% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 36066938000 1.85% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1954690613500 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.998884 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.626963 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.771270 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31 0.514603 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total 0.703622 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 104 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
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system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
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-system.cpu1.kern.mode_good::idle 424
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system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
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-system.cpu1.icache.occ_percent::total 0.875049 # Average percentage of cache occupancy
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-system.cpu1.icache.ReadReq_miss_latency::total 4168917000 # number of ReadReq miss cycles
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-system.cpu1.icache.demand_miss_latency::total 4168917000 # number of demand (read+write) miss cycles
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-system.cpu1.icache.overall_miss_latency::total 4168917000 # number of overall miss cycles
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-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13216.238322 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13216.238322 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13216.238322 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13216.238322 # average overall miss latency
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+system.cpu1.kern.swap_context 338 # number of times the context was actually changed
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+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13529.747112 # average overall miss latency
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system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
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-system.cpu1.icache.demand_mshr_miss_latency::total 3538039000 # number of demand (read+write) MSHR miss cycles
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-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average overall mshr miss latency
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+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11529.747112 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 165415 # number of replacements
-system.cpu1.dcache.tagsinuse 486.567196 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 4004380 # Total number of references to valid blocks.
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-system.cpu1.dcache.warmup_cycle 60834829000 # Cycle when the warmup percentage was hit.
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-system.cpu1.dcache.LoadLockedReq_hits::total 47962 # number of LoadLockedReq hits
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-system.cpu1.dcache.LoadLockedReq_misses::total 8861 # number of LoadLockedReq misses
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-system.cpu1.dcache.ReadReq_miss_latency::total 1427906500 # number of ReadReq miss cycles
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-system.cpu1.dcache.WriteReq_miss_latency::total 1084822000 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81394000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 81394000 # number of LoadLockedReq miss cycles
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-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56823 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 56823 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56353 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 56353 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 4071922 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 4071922 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 4071922 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 4071922 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049608 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.049608 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036669 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.036669 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155940 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155940 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103224 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103224 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044207 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.044207 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044207 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.044207 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12134.632708 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12134.632708 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17403.375365 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 17403.375365 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.644961 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.644961 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7253.223311 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7253.223311 # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13959.137473 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 13959.137473 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13959.137473 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 13959.137473 # average overall miss latency
+system.cpu1.dcache.replacements 52807 # number of replacements
+system.cpu1.dcache.tagsinuse 417.673106 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 1641018 # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs 53319 # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs 30.777359 # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 1938580812000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data 417.673106 # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data 0.815768 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total 0.815768 # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data 1001238 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 1001238 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 616220 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 616220 # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 10806 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 10806 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11203 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 11203 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 1617458 # number of demand (read+write) hits
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+system.cpu1.dcache.overall_hits::cpu1.data 1617458 # number of overall hits
+system.cpu1.dcache.overall_hits::total 1617458 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 37008 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 37008 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 20401 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 20401 # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 956 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 956 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 500 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 500 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 57409 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 57409 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 57409 # number of overall misses
+system.cpu1.dcache.overall_misses::total 57409 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 463706500 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 463706500 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 540901000 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 540901000 # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 10601500 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 10601500 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3694000 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total 3694000 # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 1004607500 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 1004607500 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 1004607500 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 1004607500 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 1038246 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 1038246 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 636621 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 636621 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 11762 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 11762 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 11703 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 11703 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 1674867 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 1674867 # number of demand (read+write) accesses
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+system.cpu1.dcache.overall_accesses::total 1674867 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035645 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.035645 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032046 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.032046 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081279 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081279 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.042724 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.042724 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034277 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.034277 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034277 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.034277 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12529.898941 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12529.898941 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26513.455223 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 26513.455223 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11089.435146 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11089.435146 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7388 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7388 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17499.129056 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 17499.129056 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17499.129056 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 17499.129056 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 113605 # number of writebacks
-system.cpu1.dcache.writebacks::total 113605 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117672 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 117672 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62334 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 62334 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8861 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8861 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5817 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 5817 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 180006 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 180006 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 180006 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 180006 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1192562500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1192562500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 960154000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 960154000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63672000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 63672000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30558000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30558000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2152716500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 2152716500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2152716500 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 2152716500 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19380500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19380500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 712390500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 712390500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 731771000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 731771000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049608 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049608 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036669 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036669 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155940 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155940 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103224 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103224 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.044207 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.044207 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10134.632708 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10134.632708 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15403.375365 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15403.375365 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7185.644961 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7185.644961 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5253.223311 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5253.223311 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 30630 # number of writebacks
+system.cpu1.dcache.writebacks::total 30630 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37008 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 37008 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20401 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 20401 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 956 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 956 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 500 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 500 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 57409 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 57409 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 57409 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 57409 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 389690500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 389690500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 500099000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 500099000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8689500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8689500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2694000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2694000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 889789500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 889789500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 889789500 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 889789500 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19380000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19380000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 529600000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 529600000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 548980000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 548980000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035645 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035645 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032046 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032046 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081279 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.081279 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.042724 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.042724 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034277 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.034277 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034277 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.034277 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10529.898941 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10529.898941 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24513.455223 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24513.455223 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9089.435146 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9089.435146 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5388 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5388 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15499.129056 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15499.129056 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15499.129056 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15499.129056 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 1.910548 # Number of seconds simulated
-sim_ticks 1910547559000 # Number of ticks simulated
-final_tick 1910547559000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.913475 # Number of seconds simulated
+sim_ticks 1913474690000 # Number of ticks simulated
+final_tick 1913474690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1284259 # Simulator instruction rate (inst/s)
-host_op_rate 1284258 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 43720523895 # Simulator tick rate (ticks/s)
-host_mem_usage 330356 # Number of bytes of host memory used
-host_seconds 43.70 # Real time elapsed on the host
-sim_insts 56120911 # Number of instructions simulated
-sim_ops 56120911 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24858368 # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28361344 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7404352 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7404352 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 388412 # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 443146 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 115693 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 115693 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 445225 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 13011122 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1388268 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 14844616 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 445225 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 445225 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3875513 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3875513 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3875513 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 445225 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 13011122 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1388268 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 18720129 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 443146 # Total number of read requests seen
-system.physmem.writeReqs 115693 # Total number of write requests seen
-system.physmem.cpureqs 561589 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28361344 # Total number of bytes read from memory
-system.physmem.bytesWritten 7404352 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28361344 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7404352 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 45 # Number of read reqs serviced by write Q
+host_inst_rate 1324010 # Simulator instruction rate (inst/s)
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+host_seconds 42.40 # Real time elapsed on the host
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+sim_ops 56131527 # Number of ops (including micro ops) simulated
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+system.physmem.bw_total::total 18692227 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 443158 # Total number of read requests seen
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+system.physmem.bytesRead 28362112 # Total number of bytes read from memory
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+system.physmem.bytesConsumedWr 7404992 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 27901 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 27706 # Track reads on a per bank basis
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-system.physmem.perBankRdReqs::3 27375 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 27676 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 27765 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 27827 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 27615 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 28008 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 27828 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 27777 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 27792 # Track reads on a per bank basis
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-system.physmem.perBankWrReqs::0 7483 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7263 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 7148 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::5 7214 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7312 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 7182 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 7584 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 7357 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 7354 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::15 7079 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 2065 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1910535659000 # Total gap between requests
+system.physmem.numWrRetry 1735 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1913462790000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 443146 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
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+system.physmem.readPktSize::6 443158 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
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+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 4718066660 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13230246660 # Sum of mem lat for all requests
-system.physmem.totBusLat 2215505000 # Total cycles spent in databus access
-system.physmem.totBankLat 6296675000 # Total cycles spent in bank access
-system.physmem.avgQLat 10647.84 # Average queueing delay per request
-system.physmem.avgBankLat 14210.47 # Average bank access latency per request
+system.physmem.totQLat 4718928250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 13231418250 # Sum of mem lat for all requests
+system.physmem.totBusLat 2215485000 # Total cycles spent in databus access
+system.physmem.totBankLat 6297005000 # Total cycles spent in bank access
+system.physmem.avgQLat 10649.88 # Average queueing delay per request
+system.physmem.avgBankLat 14211.35 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 29858.31 # Average memory access latency
-system.physmem.avgRdBW 14.84 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 3.88 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 14.84 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 3.88 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 29861.22 # Average memory access latency
+system.physmem.avgRdBW 14.82 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 14.82 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 3.87 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.15 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 11.47 # Average write queue length over time
-system.physmem.readRowHits 415807 # Number of row buffer hits during reads
-system.physmem.writeRowHits 89941 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.84 # Row buffer hit rate for reads
+system.physmem.avgWrQLen 9.64 # Average write queue length over time
+system.physmem.readRowHits 415747 # Number of row buffer hits during reads
+system.physmem.writeRowHits 89943 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 93.83 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 77.74 # Row buffer hit rate for writes
-system.physmem.avgGap 3418758.64 # Average gap between requests
+system.physmem.avgGap 3423861.73 # Average gap between requests
system.iocache.replacements 41685 # number of replacements
-system.iocache.tagsinuse 1.342284 # Cycle average of tags in use
+system.iocache.tagsinuse 1.364719 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 1745701071000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide 1.342284 # Average occupied blocks per requestor
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system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles
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system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
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system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency
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-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256168.940268 # average WriteReq miss latency
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-system.iocache.blocked_cycles::no_mshrs 285028 # number of cycles access was blocked
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
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system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
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system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
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system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
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+system.iocache.overall_avg_mshr_miss_latency::total 203999.840072 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9055197 # DTB read hits
+system.cpu.dtb.read_hits 9056964 # DTB read hits
system.cpu.dtb.read_misses 10329 # DTB read misses
system.cpu.dtb.read_acv 210 # DTB read access violations
system.cpu.dtb.read_accesses 728856 # DTB read accesses
-system.cpu.dtb.write_hits 6350929 # DTB write hits
+system.cpu.dtb.write_hits 6352252 # DTB write hits
system.cpu.dtb.write_misses 1142 # DTB write misses
system.cpu.dtb.write_acv 157 # DTB write access violations
system.cpu.dtb.write_accesses 291931 # DTB write accesses
-system.cpu.dtb.data_hits 15406126 # DTB hits
+system.cpu.dtb.data_hits 15409216 # DTB hits
system.cpu.dtb.data_misses 11471 # DTB misses
system.cpu.dtb.data_acv 367 # DTB access violations
system.cpu.dtb.data_accesses 1020787 # DTB accesses
-system.cpu.itb.fetch_hits 4974131 # ITB hits
+system.cpu.itb.fetch_hits 4974658 # ITB hits
system.cpu.itb.fetch_misses 5006 # ITB misses
system.cpu.itb.fetch_acv 184 # ITB acv
-system.cpu.itb.fetch_accesses 4979137 # ITB accesses
+system.cpu.itb.fetch_accesses 4979664 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 3821095118 # number of cpu cycles simulated
+system.cpu.numCycles 3826949380 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 56120911 # Number of instructions committed
-system.cpu.committedOps 56120911 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 51995405 # Number of integer alu accesses
+system.cpu.committedInsts 56131527 # Number of instructions committed
+system.cpu.committedOps 56131527 # Number of ops (including micro ops) committed
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system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses
-system.cpu.num_func_calls 1481756 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 6462892 # number of instructions that are conditional controls
-system.cpu.num_int_insts 51995405 # number of integer instructions
+system.cpu.num_func_calls 1482234 # number of times a function call or return occured
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+system.cpu.num_int_insts 52005592 # number of integer instructions
system.cpu.num_fp_insts 324259 # number of float instructions
-system.cpu.num_int_register_reads 71234690 # number of times the integer registers were read
-system.cpu.num_int_register_writes 38473511 # number of times the integer registers were written
+system.cpu.num_int_register_reads 71250465 # number of times the integer registers were read
+system.cpu.num_int_register_writes 38480970 # number of times the integer registers were written
system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read
system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written
-system.cpu.num_mem_refs 15458726 # number of memory refs
-system.cpu.num_load_insts 9092044 # Number of load instructions
-system.cpu.num_store_insts 6366682 # Number of store instructions
-system.cpu.num_idle_cycles 3587142255.998123 # Number of idle cycles
-system.cpu.num_busy_cycles 233952862.001878 # Number of busy cycles
-system.cpu.not_idle_fraction 0.061227 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.938773 # Percentage of idle cycles
+system.cpu.num_mem_refs 15461819 # number of memory refs
+system.cpu.num_load_insts 9093811 # Number of load instructions
+system.cpu.num_store_insts 6368008 # Number of store instructions
+system.cpu.num_idle_cycles 3593003741.998122 # Number of idle cycles
+system.cpu.num_busy_cycles 233945638.001878 # Number of busy cycles
+system.cpu.not_idle_fraction 0.061131 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.938869 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei 211970 # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0 74891 40.89% 40.89% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
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system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22 1930 1.05% 42.01% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 106204 57.99% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 183156 # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0 73524 49.31% 49.31% # number of times we switched to this ipl from a different ipl
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+system.cpu.kern.ipl_count::31 106230 57.99% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total 183193 # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0 73532 49.31% 49.31% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22 1930 1.29% 50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31 73524 49.31% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total 149109 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1855675111500 97.13% 97.13% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 91586500 0.00% 97.13% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 735892500 0.04% 97.17% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 54044234500 2.83% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1910546825000 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::22 1933 1.30% 50.69% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total 149128 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0 1858610780000 97.13% 97.13% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21 91300500 0.00% 97.14% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22 737276500 0.04% 97.18% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 54034599000 2.82% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1913473956000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31 0.692290 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total 0.814109 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31 0.692196 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total 0.814049 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl 175939 91.22% 93.42% # number of callpals executed
-system.cpu.kern.callpal::rdps 6831 3.54% 96.96% # number of callpals executed
+system.cpu.kern.callpal::swpipl 175970 91.22% 93.41% # number of callpals executed
+system.cpu.kern.callpal::rdps 6834 3.54% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
-system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
+system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
-system.cpu.kern.callpal::rti 5155 2.67% 99.64% # number of callpals executed
+system.cpu.kern.callpal::rti 5158 2.67% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 192879 # number of callpals executed
+system.cpu.kern.callpal::total 192916 # number of callpals executed
system.cpu.kern.mode_switch::kernel 5900 # number of protection mode switches
-system.cpu.kern.mode_switch::user 1744 # number of protection mode switches
-system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches
-system.cpu.kern.mode_good::kernel 1913
-system.cpu.kern.mode_good::user 1744
+system.cpu.kern.mode_switch::user 1742 # number of protection mode switches
+system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches
+system.cpu.kern.mode_good::kernel 1911
+system.cpu.kern.mode_good::user 1742
system.cpu.kern.mode_good::idle 169
-system.cpu.kern.mode_switch_good::kernel 0.324237 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel 0.323898 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total 0.392853 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 45393996500 2.38% 2.38% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 5132973000 0.27% 2.64% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1860019853500 97.36% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::idle 0.080553 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel 45394142000 2.37% 2.37% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 5131394000 0.27% 2.64% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1862948418000 97.36% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4175 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu.icache.replacements 927816 # number of replacements
-system.cpu.icache.tagsinuse 509.100001 # Cycle average of tags in use
-system.cpu.icache.total_refs 55204264 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 928327 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 59.466399 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 32331359000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 509.100001 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.994336 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.994336 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 55204264 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 55204264 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 55204264 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 55204264 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 55204264 # number of overall hits
-system.cpu.icache.overall_hits::total 55204264 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 928486 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 928486 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 928486 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 928486 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 928486 # number of overall misses
-system.cpu.icache.overall_misses::total 928486 # number of overall misses
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 21412.279782 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27558.258918 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 27558.258918 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13321.027008 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13321.027008 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22774.664079 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22774.664079 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22774.664079 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22774.664079 # average overall miss latency
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+system.cpu.dcache.ReadReq_hits::total 7807394 # number of ReadReq hits
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+system.cpu.dcache.WriteReq_hits::total 5848285 # number of WriteReq hits
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+system.cpu.dcache.LoadLockedReq_hits::total 183004 # number of LoadLockedReq hits
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+system.cpu.dcache.StoreCondReq_hits::total 199228 # number of StoreCondReq hits
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+system.cpu.dcache.overall_hits::total 13655679 # number of overall hits
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+system.cpu.dcache.LoadLockedReq_misses::total 17244 # number of LoadLockedReq misses
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+system.cpu.dcache.overall_misses::total 1373087 # number of overall misses
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+system.cpu.dcache.ReadReq_miss_latency::total 22867911000 # number of ReadReq miss cycles
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+system.cpu.dcache.LoadLockedReq_miss_latency::total 228869000 # number of LoadLockedReq miss cycles
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+system.cpu.dcache.demand_miss_latency::total 31253597000 # number of demand (read+write) miss cycles
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+system.cpu.dcache.overall_miss_latency::total 31253597000 # number of overall miss cycles
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+system.cpu.dcache.overall_accesses::total 15028766 # number of overall (read+write) accesses
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+system.cpu.dcache.ReadReq_avg_miss_latency::total 21397.876860 # average ReadReq miss latency
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+system.cpu.dcache.WriteReq_avg_miss_latency::total 27549.422282 # average WriteReq miss latency
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+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13272.384598 # average LoadLockedReq miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 22761.556260 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22761.556260 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22761.556260 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 834499 # number of writebacks
-system.cpu.dcache.writebacks::total 834499 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068716 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1068716 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304374 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 304374 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17254 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 17254 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1373090 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1373090 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1373090 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1373090 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20746214000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 20746214000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7779269500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 7779269500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 195333000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195333000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28525483500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 28525483500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28525483500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 28525483500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010997000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010997000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435232500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435232500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120428 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120428 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049481 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049481 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086167 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086167 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.091383 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.091383 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19412.279782 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19412.279782 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25558.258918 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25558.258918 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11321.027008 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11321.027008 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20774.664079 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20774.664079 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20774.664079 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20774.664079 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 834498 # number of writebacks
+system.cpu.dcache.writebacks::total 834498 # number of writebacks
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+system.cpu.dcache.ReadReq_mshr_misses::total 1068700 # number of ReadReq MSHR misses
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+system.cpu.dcache.WriteReq_mshr_misses::total 304387 # number of WriteReq MSHR misses
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+system.cpu.dcache.LoadLockedReq_mshr_misses::total 17244 # number of LoadLockedReq MSHR misses
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+system.cpu.dcache.demand_mshr_misses::total 1373087 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1373087 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1373087 # number of overall MSHR misses
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+system.cpu.dcache.ReadReq_mshr_miss_latency::total 20730511000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7776912000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 7776912000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194381000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194381000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28507423000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 28507423000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28507423000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 28507423000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011665000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011665000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435901000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435901000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120402 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120402 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049472 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049472 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086113 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086113 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091364 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.091364 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091364 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.091364 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19397.876860 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19397.876860 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25549.422282 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25549.422282 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.384598 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.384598 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20761.556260 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20761.556260 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20761.556260 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20761.556260 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
sim_ticks 912096763500 # Number of ticks simulated
final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1193297 # Simulator instruction rate (inst/s)
-host_op_rate 1536367 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 17661410361 # Simulator tick rate (ticks/s)
-host_mem_usage 435356 # Number of bytes of host memory used
-host_seconds 51.64 # Real time elapsed on the host
+host_inst_rate 1025890 # Simulator instruction rate (inst/s)
+host_op_rate 1320831 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 15183699019 # Simulator tick rate (ticks/s)
+host_mem_usage 392232 # Number of bytes of host memory used
+host_seconds 60.07 # Real time elapsed on the host
sim_insts 61625970 # Number of instructions simulated
sim_ops 79343340 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 0 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 0 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 0 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 0 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem.totBusLat 0 # Total cycles spent in databus access
sim_ticks 2332810264000 # Number of ticks simulated
final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1101050 # Simulator instruction rate (inst/s)
-host_op_rate 1415882 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 42519386287 # Simulator tick rate (ticks/s)
-host_mem_usage 435224 # Number of bytes of host memory used
-host_seconds 54.86 # Real time elapsed on the host
+host_inst_rate 1712706 # Simulator instruction rate (inst/s)
+host_op_rate 2202434 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 66139785958 # Simulator tick rate (ticks/s)
+host_mem_usage 391204 # Number of bytes of host memory used
+host_seconds 35.27 # Real time elapsed on the host
sim_insts 60408639 # Number of instructions simulated
sim_ops 77681819 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 0 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 0 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 0 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 0 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem.totBusLat 0 # Total cycles spent in databus access
---------- Begin Simulation Statistics ----------
-sim_seconds 1.183003 # Number of seconds simulated
-sim_ticks 1183003114000 # Number of ticks simulated
-final_tick 1183003114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.182958 # Number of seconds simulated
+sim_ticks 1182958259000 # Number of ticks simulated
+final_tick 1182958259000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 673901 # Simulator instruction rate (inst/s)
-host_op_rate 858757 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 12970235901 # Simulator tick rate (ticks/s)
-host_mem_usage 408748 # Number of bytes of host memory used
-host_seconds 91.21 # Real time elapsed on the host
-sim_insts 61465824 # Number of instructions simulated
-sim_ops 78326377 # Number of ops (including micro ops) simulated
+host_inst_rate 332432 # Simulator instruction rate (inst/s)
+host_op_rate 423606 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6399087906 # Simulator tick rate (ticks/s)
+host_mem_usage 408760 # Number of bytes of host memory used
+host_seconds 184.86 # Real time elapsed on the host
+sim_insts 61454647 # Number of instructions simulated
+sim_ops 78309315 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 379748 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4530164 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4709236 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 336668 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4964784 # Number of bytes read from this memory
-system.physmem.bytes_read::total 62116388 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 379748 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 336668 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 716416 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4089728 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 4815472 # Number of bytes read from this memory
+system.physmem.bytes_read::total 62146212 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4116096 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7117072 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7143440 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 12152 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 70856 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 73654 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 5342 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 77601 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6654023 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 63902 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 75268 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 6654489 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 64314 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 820738 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 43875212 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 821150 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 43876875 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 162 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 321003 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 3829376 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 332539 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 3980898 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 284588 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 4196763 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 52507375 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 321003 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 284588 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 605591 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3457073 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 14370 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 2544663 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6016106 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3457073 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 43875212 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 273183 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 4070703 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 52534577 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 332539 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 273183 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 605722 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3479494 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 14371 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 2544759 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6038624 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3479494 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 43876875 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 162 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 321003 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3843746 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 332539 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 3995269 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 284588 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 6741426 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 58523481 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 6654023 # Total number of read requests seen
-system.physmem.writeReqs 820738 # Total number of write requests seen
-system.physmem.cpureqs 272097 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 425857472 # Total number of bytes read from memory
-system.physmem.bytesWritten 52527232 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 62116388 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7117072 # bytesWritten derated as per pkt->getSize()
+system.physmem.bw_total::cpu1.inst 273183 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 6615462 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 58573201 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 6654489 # Total number of read requests seen
+system.physmem.writeReqs 821150 # Total number of write requests seen
+system.physmem.cpureqs 235683 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 425887296 # Total number of bytes read from memory
+system.physmem.bytesWritten 52553600 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 62146212 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7143440 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 112 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 11760 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 422267 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 415727 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 415213 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 415818 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 415767 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 415004 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 415107 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 415928 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 415784 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 415110 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 415164 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 415654 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 415632 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 415090 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 415000 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 415646 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 51297 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 51187 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50850 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51382 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 51290 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 50625 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50696 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 51406 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51898 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51190 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51285 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51758 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51708 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51260 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51138 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51768 # Track writes on a per bank basis
+system.physmem.neitherReadNorWrite 11769 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 422283 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 415708 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 415257 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 415923 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 415836 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 415086 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 415138 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 415982 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 415774 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 415145 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 415183 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 415686 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 415664 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 415065 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 414968 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 415679 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 51312 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 51158 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 50892 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 51475 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 51354 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 50696 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 50735 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 51449 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51887 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 51295 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51778 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51726 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 51254 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 51118 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51796 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1182998675500 # Total gap between requests
+system.physmem.totGap 1182953705000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6825 # Categorize read packet sizes
system.physmem.readPktSize::3 6488064 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 159134 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 756836 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 63902 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 11760 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 570635 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 408572 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 415826 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1537846 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 1165216 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1169840 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1140716 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 29537 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 27577 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 48457 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 69066 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 48178 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 5864 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 5691 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 5515 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 5307 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 68 # What read queue length does an incoming req see
+system.physmem.readPktSize::6 159600 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 756836 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 64314 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 571059 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 408588 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 415867 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1537787 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 1165425 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1169620 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1140545 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 29607 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 27579 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 48460 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 69110 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 48185 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 5882 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 5724 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 5512 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 5352 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 75 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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+system.l2c.overall_mshr_miss_latency::cpu1.inst 213513533 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 2706578538 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 5621827882 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 209633632 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12454649323 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3082087 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154326885776 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 166994250818 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1000448248 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8209486413 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 9209934661 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 209633632 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13455097571 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3082087 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162536372189 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 176204185479 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000267 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001203 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036711 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000742 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for ReadReq accesses
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+system.l2c.ReadReq_mshr_miss_rate::total 0.017549 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.807593 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.855783 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.827796 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.722721 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.824253 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.765579 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540220 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.581239 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.560812 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000267 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001203 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.221438 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000742 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.280035 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.106730 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000267 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001203 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.221438 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000742 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.280035 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.106730 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39765.958828 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40533.525754 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42330.200833 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49189.672461 # average ReadReq mshr miss latency
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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10025.461902 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10021.418465 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10049.822380 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.648188 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10039.745155 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32136.778001 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34767.810300 # average ReadExReq mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39765.958828 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 33018.115387 # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42330.200833 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35452.406712 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 34694.074809 # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35452.406712 # average overall mshr miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 5883553 # DTB read hits
-system.cpu0.dtb.read_misses 2148 # DTB read misses
-system.cpu0.dtb.write_hits 4842455 # DTB write hits
-system.cpu0.dtb.write_misses 405 # DTB write misses
+system.cpu0.dtb.read_hits 7073604 # DTB read hits
+system.cpu0.dtb.read_misses 3763 # DTB read misses
+system.cpu0.dtb.write_hits 5658971 # DTB write hits
+system.cpu0.dtb.write_misses 806 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 1536 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 5885701 # DTB read accesses
-system.cpu0.dtb.write_accesses 4842860 # DTB write accesses
+system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 7077367 # DTB read accesses
+system.cpu0.dtb.write_accesses 5659777 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 10726008 # DTB hits
-system.cpu0.dtb.misses 2553 # DTB misses
-system.cpu0.dtb.accesses 10728561 # DTB accesses
-system.cpu0.itb.inst_hits 24779849 # ITB inst hits
-system.cpu0.itb.inst_misses 1350 # ITB inst misses
+system.cpu0.dtb.hits 12732575 # DTB hits
+system.cpu0.dtb.misses 4569 # DTB misses
+system.cpu0.dtb.accesses 12737144 # DTB accesses
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+system.cpu0.itb.inst_misses 2205 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 24781199 # ITB inst accesses
-system.cpu0.itb.hits 24779849 # DTB hits
-system.cpu0.itb.misses 1350 # DTB misses
-system.cpu0.itb.accesses 24781199 # DTB accesses
-system.cpu0.numCycles 2364565551 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 29575573 # ITB inst accesses
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+system.cpu0.itb.misses 2205 # DTB misses
+system.cpu0.itb.accesses 29575573 # DTB accesses
+system.cpu0.numCycles 2365916518 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 24381823 # Number of instructions committed
-system.cpu0.committedOps 31476006 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 28075203 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses
-system.cpu0.num_func_calls 1070639 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 3752398 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 28075203 # number of integer instructions
-system.cpu0.num_fp_insts 4364 # number of float instructions
-system.cpu0.num_int_register_reads 160702802 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 30522196 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written
-system.cpu0.num_mem_refs 11318426 # number of memory refs
-system.cpu0.num_load_insts 6163151 # Number of load instructions
-system.cpu0.num_store_insts 5155275 # Number of store instructions
-system.cpu0.num_idle_cycles 2243464250.276980 # Number of idle cycles
-system.cpu0.num_busy_cycles 121101300.723020 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.051215 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.948785 # Percentage of idle cycles
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+system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
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+system.cpu0.num_conditional_control_insts 4373656 # number of instructions that are conditional controls
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+system.cpu0.num_int_register_reads 190112848 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 36234022 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
+system.cpu0.num_mem_refs 13400902 # number of memory refs
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+system.cpu0.not_idle_fraction 0.059566 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.940434 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 38919 # number of quiesce instructions executed
-system.cpu0.icache.replacements 354669 # number of replacements
-system.cpu0.icache.tagsinuse 509.601981 # Cycle average of tags in use
-system.cpu0.icache.total_refs 24424650 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 355181 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 68.766770 # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce 46697 # number of quiesce instructions executed
+system.cpu0.icache.replacements 425482 # number of replacements
+system.cpu0.icache.tagsinuse 509.601890 # Cycle average of tags in use
+system.cpu0.icache.total_refs 29147356 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 425994 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 68.421987 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 74995953000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 509.601981 # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu0.inst 509.601890 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.995316 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.995316 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 24424650 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 24424650 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 24424650 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 24424650 # number of demand (read+write) hits
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-system.cpu0.icache.overall_hits::total 24424650 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 355182 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 355182 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 355182 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 355182 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 355182 # number of overall misses
-system.cpu0.icache.overall_misses::total 355182 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 4877233500 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 4877233500 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 4877233500 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 4877233500 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 4877233500 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 4877233500 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 24779832 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 24779832 # number of ReadReq accesses(hits+misses)
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-system.cpu0.icache.overall_accesses::total 24779832 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014334 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.014334 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014334 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.014334 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014334 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.014334 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13731.646029 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13731.646029 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13731.646029 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13731.646029 # average overall miss latency
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+system.cpu0.icache.ReadReq_hits::total 29147356 # number of ReadReq hits
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+system.cpu0.icache.overall_hits::cpu0.inst 29147356 # number of overall hits
+system.cpu0.icache.overall_hits::total 29147356 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 425995 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 425995 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 425995 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 425995 # number of demand (read+write) misses
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+system.cpu0.icache.overall_misses::total 425995 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5809941500 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 5809941500 # number of ReadReq miss cycles
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+system.cpu0.icache.demand_miss_latency::total 5809941500 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 5809941500 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 5809941500 # number of overall miss cycles
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system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu0.dcache.warmup_cycle 473552000 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 257540 # number of writebacks
-system.cpu0.dcache.writebacks::total 257540 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191756 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 191756 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126522 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 126522 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8645 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8645 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7700 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 7700 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 318278 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 318278 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 318278 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 318278 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2295207000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2295207000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3557101000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3557101000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 61365500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 61365500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30208000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30208000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.writebacks::writebacks 306714 # number of writebacks
+system.cpu0.dcache.writebacks::total 306714 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228068 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 228068 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141674 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 141674 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9338 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9338 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7487 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 7487 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 369742 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 369742 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 369742 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 369742 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2690632000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2690632000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3849543500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3849543500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69909500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69909500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29541500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29541500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5852308000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 5852308000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5852308000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 5852308000 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12211047000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12211047000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1122364500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1122364500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13333411500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13333411500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033824 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033824 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026929 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026929 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062643 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062643 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.055826 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.055826 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.030699 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.030699 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11969.414256 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11969.414256 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28114.486018 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28114.486018 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7098.380567 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7098.380567 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3923.116883 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3923.116883 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6540175500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 6540175500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6540175500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 6540175500 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13562243000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13562243000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128446000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128446000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14690689000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14690689000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033386 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033386 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025780 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025780 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059374 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059374 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047631 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047631 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029995 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.029995 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029995 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.029995 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11797.498992 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11797.498992 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27171.841693 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27171.841693 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7486.560291 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7486.560291 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3945.705890 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3945.705890 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17688.484132 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17688.484132 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17688.484132 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17688.484132 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 9504194 # DTB read hits
-system.cpu1.dtb.read_misses 5263 # DTB read misses
-system.cpu1.dtb.write_hits 6646220 # DTB write hits
-system.cpu1.dtb.write_misses 1833 # DTB write misses
+system.cpu1.dtb.read_hits 8309714 # DTB read hits
+system.cpu1.dtb.read_misses 3643 # DTB read misses
+system.cpu1.dtb.write_hits 5826503 # DTB write hits
+system.cpu1.dtb.write_misses 1435 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2237 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 191 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 9509457 # DTB read accesses
-system.cpu1.dtb.write_accesses 6648053 # DTB write accesses
+system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 8313357 # DTB read accesses
+system.cpu1.dtb.write_accesses 5827938 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 16150414 # DTB hits
-system.cpu1.dtb.misses 7096 # DTB misses
-system.cpu1.dtb.accesses 16157510 # DTB accesses
-system.cpu1.itb.inst_hits 37994467 # ITB inst hits
-system.cpu1.itb.inst_misses 3017 # ITB inst misses
+system.cpu1.dtb.hits 14136217 # DTB hits
+system.cpu1.dtb.misses 5078 # DTB misses
+system.cpu1.dtb.accesses 14141295 # DTB accesses
+system.cpu1.itb.inst_hits 33189716 # ITB inst hits
+system.cpu1.itb.inst_misses 2171 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 37997484 # ITB inst accesses
-system.cpu1.itb.hits 37994467 # DTB hits
-system.cpu1.itb.misses 3017 # DTB misses
-system.cpu1.itb.accesses 37997484 # DTB accesses
-system.cpu1.numCycles 2366006228 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 33191887 # ITB inst accesses
+system.cpu1.itb.hits 33189716 # DTB hits
+system.cpu1.itb.misses 2171 # DTB misses
+system.cpu1.itb.accesses 33191887 # DTB accesses
+system.cpu1.numCycles 2364475282 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 37084001 # Number of instructions committed
-system.cpu1.committedOps 46850371 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 42360540 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses
-system.cpu1.num_func_calls 1133542 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 4355119 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 42360540 # number of integer instructions
-system.cpu1.num_fp_insts 5457 # number of float instructions
-system.cpu1.num_int_register_reads 243148462 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 45181015 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written
-system.cpu1.num_mem_refs 16764021 # number of memory refs
-system.cpu1.num_load_insts 9884261 # Number of load instructions
-system.cpu1.num_store_insts 6879760 # Number of store instructions
-system.cpu1.num_idle_cycles 1849775265.196436 # Number of idle cycles
-system.cpu1.num_busy_cycles 516230962.803564 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.218187 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.781813 # Percentage of idle cycles
+system.cpu1.committedInsts 32579235 # Number of instructions committed
+system.cpu1.committedOps 41086550 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 37310899 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
+system.cpu1.num_func_calls 962009 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 3732730 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 37310899 # number of integer instructions
+system.cpu1.num_fp_insts 6793 # number of float instructions
+system.cpu1.num_int_register_reads 213650265 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 39453467 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
+system.cpu1.num_mem_refs 14673985 # number of memory refs
+system.cpu1.num_load_insts 8631614 # Number of load instructions
+system.cpu1.num_store_insts 6042371 # Number of store instructions
+system.cpu1.num_idle_cycles 1868339828.826306 # Number of idle cycles
+system.cpu1.num_busy_cycles 496135453.173694 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.209829 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.790171 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 51687 # number of quiesce instructions executed
-system.cpu1.icache.replacements 540342 # number of replacements
-system.cpu1.icache.tagsinuse 478.756805 # Cycle average of tags in use
-system.cpu1.icache.total_refs 37453609 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 540854 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 69.249019 # Average number of references to valid blocks.
+system.cpu1.kern.inst.quiesce 43883 # number of quiesce instructions executed
+system.cpu1.icache.replacements 469209 # number of replacements
+system.cpu1.icache.tagsinuse 478.755545 # Cycle average of tags in use
+system.cpu1.icache.total_refs 32719991 # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs 469721 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 69.658353 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 92137748500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 478.756805 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.935072 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.935072 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 37453609 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 37453609 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 37453609 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 37453609 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 37453609 # number of overall hits
-system.cpu1.icache.overall_hits::total 37453609 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 540854 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 540854 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 540854 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 540854 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 540854 # number of overall misses
-system.cpu1.icache.overall_misses::total 540854 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7301553500 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 7301553500 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 7301553500 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 7301553500 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 7301553500 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 7301553500 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 37994463 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 37994463 # number of ReadReq accesses(hits+misses)
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-system.cpu1.icache.demand_accesses::total 37994463 # number of demand (read+write) accesses
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+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92810 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 92810 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92737 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 92737 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 12092003 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 12092003 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 12092003 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 12092003 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023992 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.023992 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030117 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.030117 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119082 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119082 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108134 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108134 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026513 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.026513 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026513 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.026513 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12700.199151 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12700.199151 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30193.057845 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 30193.057845 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8348.760405 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8348.760405 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5151.276426 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5151.276426 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20877.578043 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 20877.578043 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20877.578043 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 20877.578043 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 315665 # number of writebacks
-system.cpu1.dcache.writebacks::total 315665 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 207178 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 207178 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 165249 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 165249 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11790 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11790 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9830 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 9830 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 372427 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 372427 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 372427 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 372427 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2224779500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2224779500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4504444000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4504444000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79540000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 79540000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30847000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30847000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.writebacks::writebacks 265550 # number of writebacks
+system.cpu1.dcache.writebacks::total 265550 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170725 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 170725 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149867 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 149867 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11052 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11052 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10024 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 10024 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 320592 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 320592 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 320592 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 320592 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1826791500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1826791500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4225209000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4225209000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70166500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70166500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31611000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31611000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6729223500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 6729223500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6729223500 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 6729223500 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169996101000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169996101000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17674592500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17674592500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 187670693500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 187670693500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025015 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025015 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028607 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028607 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.105151 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.105151 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087730 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087730 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.026491 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.026491 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10738.492987 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10738.492987 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27258.525014 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27258.525014 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6746.395250 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6746.395250 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3138.046796 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3138.046796 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6052000500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 6052000500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6052000500 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 6052000500 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168642802500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168642802500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17668343500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17668343500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186311146000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186311146000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023992 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023992 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030117 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030117 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119082 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119082 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108091 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108091 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.026513 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.026513 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10700.199151 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10700.199151 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28193.057845 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28193.057845 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6348.760405 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6348.760405 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3153.531524 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3153.531524 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18877.578043 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18877.578043 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18877.578043 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18877.578043 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509652310593 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 509652310593 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509652310593 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 509652310593 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509685021664 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 509685021664 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509685021664 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 509685021664 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 2.603665 # Number of seconds simulated
-sim_ticks 2603664815000 # Number of ticks simulated
-final_tick 2603664815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.603674 # Number of seconds simulated
+sim_ticks 2603674284000 # Number of ticks simulated
+final_tick 2603674284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 536000 # Simulator instruction rate (inst/s)
-host_op_rate 682052 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 23183028791 # Simulator tick rate (ticks/s)
-host_mem_usage 404656 # Number of bytes of host memory used
-host_seconds 112.31 # Real time elapsed on the host
-sim_insts 60197643 # Number of instructions simulated
-sim_ops 76600583 # Number of ops (including micro ops) simulated
+host_inst_rate 271279 # Simulator instruction rate (inst/s)
+host_op_rate 345198 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 11733407598 # Simulator tick rate (ticks/s)
+host_mem_usage 403640 # Number of bytes of host memory used
+host_seconds 221.90 # Real time elapsed on the host
+sim_insts 60197457 # Number of instructions simulated
+sim_ops 76600355 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory
-system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory
+system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47119503 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47119332 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 270695 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3475919 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50866314 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 270695 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 270695 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1412434 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1158395 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2570829 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1412434 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47119503 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 270817 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3475931 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 50866276 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 270817 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 270817 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1412478 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1158391 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2570868 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1412478 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47119332 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 270695 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4634314 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53437143 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15494089 # Total number of read requests seen
-system.physmem.writeReqs 811479 # Total number of write requests seen
-system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 991621696 # Total number of bytes read from memory
-system.physmem.bytesWritten 51934656 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize()
+system.physmem.bw_total::cpu.inst 270817 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4634322 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53437145 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15494095 # Total number of read requests seen
+system.physmem.writeReqs 811481 # Total number of write requests seen
+system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 991622080 # Total number of bytes read from memory
+system.physmem.bytesWritten 51934784 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 974844 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 967635 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 967737 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 968249 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 968097 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 967668 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 968007 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 968101 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 967570 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 967431 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 968087 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 50753 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 50356 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 50139 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 50212 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 50710 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51141 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51142 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 51058 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 51155 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 50650 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 50586 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 50587 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 51214 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2603660455000 # Total gap between requests
+system.physmem.totGap 2603669924000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6652 # Categorize read packet sizes
system.physmem.readPktSize::3 15335424 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 152013 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
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-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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+system.physmem.readPktSize::6 152019 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
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+system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::24 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 341507754589 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 436421735839 # Sum of mem lat for all requests
-system.physmem.totBusLat 77468765000 # Total cycles spent in databus access
-system.physmem.totBankLat 17445216250 # Total cycles spent in bank access
-system.physmem.avgQLat 22041.64 # Average queueing delay per request
-system.physmem.avgBankLat 1125.95 # Average bank access latency per request
+system.physmem.totQLat 341488215750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 436408620750 # Sum of mem lat for all requests
+system.physmem.totBusLat 77468795000 # Total cycles spent in databus access
+system.physmem.totBankLat 17451610000 # Total cycles spent in bank access
+system.physmem.avgQLat 22040.37 # Average queueing delay per request
+system.physmem.avgBankLat 1126.36 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 28167.59 # Average memory access latency
-system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 28166.74 # Average memory access latency
+system.physmem.avgRdBW 380.85 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.13 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.17 # Average read queue length over time
-system.physmem.avgWrQLen 12.39 # Average write queue length over time
-system.physmem.readRowHits 15418905 # Number of row buffer hits during reads
-system.physmem.writeRowHits 794060 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 12.40 # Average write queue length over time
+system.physmem.readRowHits 15418728 # Number of row buffer hits during reads
+system.physmem.writeRowHits 794030 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes
-system.physmem.avgGap 159679.22 # Average gap between requests
+system.physmem.avgGap 159679.73 # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 14995667 # DTB read hits
+system.cpu.dtb.read_hits 14995645 # DTB read hits
system.cpu.dtb.read_misses 7332 # DTB read misses
-system.cpu.dtb.write_hits 11230865 # DTB write hits
+system.cpu.dtb.write_hits 11230857 # DTB write hits
system.cpu.dtb.write_misses 2203 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 15002999 # DTB read accesses
-system.cpu.dtb.write_accesses 11233068 # DTB write accesses
+system.cpu.dtb.read_accesses 15002977 # DTB read accesses
+system.cpu.dtb.write_accesses 11233060 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 26226532 # DTB hits
+system.cpu.dtb.hits 26226502 # DTB hits
system.cpu.dtb.misses 9535 # DTB misses
-system.cpu.dtb.accesses 26236067 # DTB accesses
-system.cpu.itb.inst_hits 61491584 # ITB inst hits
+system.cpu.dtb.accesses 26236037 # DTB accesses
+system.cpu.itb.inst_hits 61491397 # ITB inst hits
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 61496055 # ITB inst accesses
-system.cpu.itb.hits 61491584 # DTB hits
+system.cpu.itb.inst_accesses 61495868 # ITB inst accesses
+system.cpu.itb.hits 61491397 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
-system.cpu.itb.accesses 61496055 # DTB accesses
-system.cpu.numCycles 5207329630 # number of cpu cycles simulated
+system.cpu.itb.accesses 61495868 # DTB accesses
+system.cpu.numCycles 5207348568 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 60197643 # Number of instructions committed
-system.cpu.committedOps 76600583 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 68868344 # Number of integer alu accesses
+system.cpu.committedInsts 60197457 # Number of instructions committed
+system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed
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system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
-system.cpu.num_func_calls 2139730 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 7947806 # number of instructions that are conditional controls
-system.cpu.num_int_insts 68868344 # number of integer instructions
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system.cpu.num_fp_insts 10269 # number of float instructions
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-system.cpu.num_int_register_writes 74176271 # number of times the integer registers were written
+system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read
+system.cpu.num_int_register_writes 74176013 # number of times the integer registers were written
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
-system.cpu.num_mem_refs 27393912 # number of memory refs
-system.cpu.num_load_insts 15659685 # Number of load instructions
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-system.cpu.idle_fraction 0.879355 # Percentage of idle cycles
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+system.cpu.idle_fraction 0.879352 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed
-system.cpu.icache.replacements 855486 # number of replacements
-system.cpu.icache.tagsinuse 510.979431 # Cycle average of tags in use
-system.cpu.icache.total_refs 60635586 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 855998 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 70.836130 # Average number of references to valid blocks.
+system.cpu.icache.replacements 855484 # number of replacements
+system.cpu.icache.tagsinuse 510.979435 # Cycle average of tags in use
+system.cpu.icache.total_refs 60635401 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 855996 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 70.836080 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 18713179000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 510.979431 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.998007 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.998007 # Average percentage of cache occupancy
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-system.cpu.icache.ReadReq_hits::total 60635586 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 60635586 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 60635586 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 60635586 # number of overall hits
-system.cpu.icache.overall_hits::total 60635586 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 855998 # number of ReadReq misses
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu.dcache.warmup_cycle 472186000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1199398748332 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1199398748332 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1199377224257 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1199377224257 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
sim_ticks 2332810256000 # Number of ticks simulated
final_tick 2332810256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1011951 # Simulator instruction rate (inst/s)
-host_op_rate 1301307 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 39078665084 # Simulator tick rate (ticks/s)
-host_mem_usage 435224 # Number of bytes of host memory used
-host_seconds 59.70 # Real time elapsed on the host
+host_inst_rate 685945 # Simulator instruction rate (inst/s)
+host_op_rate 882083 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 26489224850 # Simulator tick rate (ticks/s)
+host_mem_usage 391216 # Number of bytes of host memory used
+host_seconds 88.07 # Real time elapsed on the host
sim_insts 60408639 # Number of instructions simulated
sim_ops 77681819 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 0 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 0 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 0 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 0 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem.totBusLat 0 # Total cycles spent in databus access
sim_ticks 5112040970500 # Number of ticks simulated
final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1816388 # Simulator instruction rate (inst/s)
-host_op_rate 3719186 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 46471341970 # Simulator tick rate (ticks/s)
-host_mem_usage 582576 # Number of bytes of host memory used
-host_seconds 110.00 # Real time elapsed on the host
+host_inst_rate 1074050 # Simulator instruction rate (inst/s)
+host_op_rate 2199194 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 27479001055 # Simulator tick rate (ticks/s)
+host_mem_usage 583620 # Number of bytes of host memory used
+host_seconds 186.03 # Real time elapsed on the host
sim_insts 199810242 # Number of instructions simulated
sim_ops 409125913 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 0 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 0 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 0 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 0 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem.totBusLat 0 # Total cycles spent in databus access
sim_ticks 5195162021000 # Number of ticks simulated
final_tick 5195162021000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 973985 # Simulator instruction rate (inst/s)
-host_op_rate 1877578 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 39447094407 # Simulator tick rate (ticks/s)
-host_mem_usage 612564 # Number of bytes of host memory used
-host_seconds 131.70 # Real time elapsed on the host
-sim_insts 128273348 # Number of instructions simulated
-sim_ops 247275973 # Number of ops (including micro ops) simulated
+host_inst_rate 926995 # Simulator instruction rate (inst/s)
+host_op_rate 1786992 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 37543942770 # Simulator tick rate (ticks/s)
+host_mem_usage 611560 # Number of bytes of host memory used
+host_seconds 138.38 # Real time elapsed on the host
+sim_insts 128273323 # Number of instructions simulated
+sim_ops 247275942 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2861312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
system.physmem.bw_total::total 4007716 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 198400 # Total number of read requests seen
system.physmem.writeReqs 126924 # Total number of write requests seen
-system.physmem.cpureqs 331611 # Reqs generatd by CPU via cache - shady
+system.physmem.cpureqs 327581 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 12697600 # Total number of bytes read from memory
system.physmem.bytesWritten 8123136 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 12697600 # bytesRead derated as per pkt->getSize()
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 198400 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 127557 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 1624 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 155111 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 8768 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 6671 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3417 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3399 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2809 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2248 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 2166 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 2070 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 2020 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1315 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1213 # What read queue length does an incoming req see
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 126924 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 155117 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 8774 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 6658 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::5 2811 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::9 2021 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1130 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1043 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 1042 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 972 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 1102 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 1082 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 971 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 1103 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 1084 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 505 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 37 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 4190 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 4518 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 4189 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 4520 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 5322 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 5432 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 5474 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 5502 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 5509 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 5510 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 5511 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 5434 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 5475 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 5503 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 5510 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 5511 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 5512 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5519 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5518 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5518 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5518 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5518 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5518 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 1329 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 1001 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 1330 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 999 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 197 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 87 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 45 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 4076582985 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 7872522985 # Sum of mem lat for all requests
+system.physmem.wrQLenPdf::26 85 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 44 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see
+system.physmem.totQLat 4073325250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 7869155250 # Sum of mem lat for all requests
system.physmem.totBusLat 991710000 # Total cycles spent in databus access
-system.physmem.totBankLat 2804230000 # Total cycles spent in bank access
-system.physmem.avgQLat 20553.30 # Average queueing delay per request
-system.physmem.avgBankLat 14138.36 # Average bank access latency per request
+system.physmem.totBankLat 2804120000 # Total cycles spent in bank access
+system.physmem.avgQLat 20536.88 # Average queueing delay per request
+system.physmem.avgBankLat 14137.80 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 39691.66 # Average memory access latency
+system.physmem.avgMemAccLat 39674.68 # Average memory access latency
system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 12.66 # Average write queue length over time
-system.physmem.readRowHits 175587 # Number of row buffer hits during reads
-system.physmem.writeRowHits 94819 # Number of row buffer hits during writes
+system.physmem.readRowHits 175586 # Number of row buffer hits during reads
+system.physmem.writeRowHits 94818 # Number of row buffer hits during writes
system.physmem.readRowHitRate 88.53 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 74.71 # Row buffer hit rate for writes
+system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes
system.physmem.avgGap 15969193.66 # Average gap between requests
system.iocache.replacements 47509 # number of replacements
system.iocache.tagsinuse 0.124742 # Cycle average of tags in use
system.iocache.overall_misses::total 47564 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 139479932 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 139479932 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10701739160 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10701739160 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 10841219092 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10841219092 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 10841219092 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10841219092 # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10699969160 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10699969160 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 10839449092 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10839449092 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 10839449092 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 10839449092 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165260.582938 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 165260.582938 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229061.197774 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 229061.197774 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227929.086957 # average overall miss latency
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-system.cpu.dtb_walker_cache.demand_miss_latency::total 92081500 # number of demand (read+write) miss cycles
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-system.cpu.dtb_walker_cache.overall_miss_latency::total 92081500 # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13180 # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total 13180 # number of ReadReq hits
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+system.cpu.dtb_walker_cache.demand_hits::total 13180 # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13180 # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total 13180 # number of overall hits
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+system.cpu.dtb_walker_cache.ReadReq_misses::total 8726 # number of ReadReq misses
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+system.cpu.dtb_walker_cache.overall_misses::total 8726 # number of overall misses
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+system.cpu.dtb_walker_cache.overall_miss_latency::total 92094500 # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21906 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21906 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21906 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 21906 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21906 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 21906 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398293 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398293 # miss rate for ReadReq accesses
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-system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398293 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10553.753582 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10553.753582 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10553.753582 # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10553.753582 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10553.753582 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10553.753582 # average overall miss latency
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398338 # miss rate for ReadReq accesses
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+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10554.033922 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10554.033922 # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10554.033922 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10554.033922 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10554.033922 # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks 2712 # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total 2712 # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8725 # number of ReadReq MSHR misses
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-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8725 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total 8725 # number of overall MSHR misses
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-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74631500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74631500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74631500 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74631500 # number of overall MSHR miss cycles
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-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398293 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398293 # mshr miss rate for overall accesses
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+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74642500 # number of overall MSHR miss cycles
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+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average overall mshr miss latency
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+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8554.033922 # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1618787 # number of replacements
+system.cpu.dcache.replacements 1618785 # number of replacements
system.cpu.dcache.tagsinuse 511.997766 # Cycle average of tags in use
-system.cpu.dcache.total_refs 20025899 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1619299 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 12.367017 # Average number of references to valid blocks.
+system.cpu.dcache.total_refs 20025893 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1619297 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 12.367029 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 39012000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.997766 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
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-system.cpu.dcache.demand_miss_latency::total 26900451000 # number of demand (read+write) miss cycles
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system.cpu.dcache.ReadReq_miss_rate::total 0.098279 # miss rate for ReadReq accesses
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 14039.480119 # average ReadReq miss latency
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-system.cpu.dcache.WriteReq_avg_miss_latency::total 27172.734433 # average WriteReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 16589.906845 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16589.906845 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16589.906845 # average overall miss latency
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+system.cpu.dcache.ReadReq_avg_miss_latency::total 14038.784573 # average ReadReq miss latency
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+system.cpu.dcache.WriteReq_avg_miss_latency::total 27173.587602 # average WriteReq miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 16589.532973 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16589.532973 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16589.532973 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1536049 # number of writebacks
-system.cpu.dcache.writebacks::total 1536049 # number of writebacks
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-system.cpu.l2cache.overall_mshr_miss_latency::total 6116888107 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4190411275 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4190411275 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 281255 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 627778857 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5485728232 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 6113844595 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 56251 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281255 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 627778857 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5485728232 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 6113844595 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86591175500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86591175500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305021500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019584 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823174 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823174 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362488 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362488 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362485 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362485 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087573 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063901 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56252 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48946.983608 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45667.229029 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46691.888156 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56251 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48770.886964 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45633.854395 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46613.996074 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.910557 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.910557 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36964.667037 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36964.667037 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56252 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48946.983608 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38707.414278 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39560.526106 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56252 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48946.983608 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38707.414278 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39560.526106 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36966.171554 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36966.171554 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48770.886964 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38701.934007 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39540.842415 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48770.886964 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38701.934007 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39540.842415 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
sim_ticks 200409293000 # Number of ticks simulated
final_tick 4321201686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 19440889 # Simulator instruction rate (inst/s)
-host_op_rate 19440880 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 7408936081 # Simulator tick rate (ticks/s)
-host_mem_usage 472492 # Number of bytes of host memory used
-host_seconds 27.05 # Real time elapsed on the host
+host_inst_rate 11931696 # Simulator instruction rate (inst/s)
+host_op_rate 11931689 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4547176905 # Simulator tick rate (ticks/s)
+host_mem_usage 472520 # Number of bytes of host memory used
+host_seconds 44.07 # Real time elapsed on the host
sim_insts 525869186 # Number of instructions simulated
sim_ops 525869186 # Number of ops (including micro ops) simulated
testsys.physmem.bytes_read::cpu.inst 81048564 # Number of bytes read from this memory
testsys.physmem.readPktSize::4 0 # Categorize read packet sizes
testsys.physmem.readPktSize::5 0 # Categorize read packet sizes
testsys.physmem.readPktSize::6 0 # Categorize read packet sizes
-testsys.physmem.readPktSize::7 0 # Categorize read packet sizes
-testsys.physmem.readPktSize::8 0 # Categorize read packet sizes
-testsys.physmem.writePktSize::0 0 # categorize write packet sizes
-testsys.physmem.writePktSize::1 0 # categorize write packet sizes
-testsys.physmem.writePktSize::2 0 # categorize write packet sizes
-testsys.physmem.writePktSize::3 0 # categorize write packet sizes
-testsys.physmem.writePktSize::4 0 # categorize write packet sizes
-testsys.physmem.writePktSize::5 0 # categorize write packet sizes
-testsys.physmem.writePktSize::6 0 # categorize write packet sizes
-testsys.physmem.writePktSize::7 0 # categorize write packet sizes
-testsys.physmem.writePktSize::8 0 # categorize write packet sizes
-testsys.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-testsys.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-testsys.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-testsys.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-testsys.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-testsys.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-testsys.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-testsys.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-testsys.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+testsys.physmem.writePktSize::0 0 # Categorize write packet sizes
+testsys.physmem.writePktSize::1 0 # Categorize write packet sizes
+testsys.physmem.writePktSize::2 0 # Categorize write packet sizes
+testsys.physmem.writePktSize::3 0 # Categorize write packet sizes
+testsys.physmem.writePktSize::4 0 # Categorize write packet sizes
+testsys.physmem.writePktSize::5 0 # Categorize write packet sizes
+testsys.physmem.writePktSize::6 0 # Categorize write packet sizes
testsys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
testsys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
testsys.physmem.totQLat 0 # Total cycles spent in queuing delays
testsys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
testsys.physmem.totBusLat 0 # Total cycles spent in databus access
drivesys.physmem.readPktSize::4 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::5 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::6 0 # Categorize read packet sizes
-drivesys.physmem.readPktSize::7 0 # Categorize read packet sizes
-drivesys.physmem.readPktSize::8 0 # Categorize read packet sizes
-drivesys.physmem.writePktSize::0 0 # categorize write packet sizes
-drivesys.physmem.writePktSize::1 0 # categorize write packet sizes
-drivesys.physmem.writePktSize::2 0 # categorize write packet sizes
-drivesys.physmem.writePktSize::3 0 # categorize write packet sizes
-drivesys.physmem.writePktSize::4 0 # categorize write packet sizes
-drivesys.physmem.writePktSize::5 0 # categorize write packet sizes
-drivesys.physmem.writePktSize::6 0 # categorize write packet sizes
-drivesys.physmem.writePktSize::7 0 # categorize write packet sizes
-drivesys.physmem.writePktSize::8 0 # categorize write packet sizes
-drivesys.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-drivesys.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-drivesys.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-drivesys.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-drivesys.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-drivesys.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-drivesys.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-drivesys.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-drivesys.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+drivesys.physmem.writePktSize::0 0 # Categorize write packet sizes
+drivesys.physmem.writePktSize::1 0 # Categorize write packet sizes
+drivesys.physmem.writePktSize::2 0 # Categorize write packet sizes
+drivesys.physmem.writePktSize::3 0 # Categorize write packet sizes
+drivesys.physmem.writePktSize::4 0 # Categorize write packet sizes
+drivesys.physmem.writePktSize::5 0 # Categorize write packet sizes
+drivesys.physmem.writePktSize::6 0 # Categorize write packet sizes
drivesys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
drivesys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
drivesys.physmem.totQLat 0 # Total cycles spent in queuing delays
drivesys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
drivesys.physmem.totBusLat 0 # Total cycles spent in databus access
sim_ticks 407365500 # Number of ticks simulated
final_tick 4321609052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 12024534237 # Simulator instruction rate (inst/s)
-host_op_rate 12021051237 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9308365303 # Simulator tick rate (ticks/s)
-host_mem_usage 472492 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
+host_inst_rate 6212406894 # Simulator instruction rate (inst/s)
+host_op_rate 6210790807 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4809282801 # Simulator tick rate (ticks/s)
+host_mem_usage 472520 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 525940622 # Number of instructions simulated
sim_ops 525940622 # Number of ops (including micro ops) simulated
testsys.physmem.bytes_read::cpu.inst 141136 # Number of bytes read from this memory
testsys.physmem.readPktSize::4 0 # Categorize read packet sizes
testsys.physmem.readPktSize::5 0 # Categorize read packet sizes
testsys.physmem.readPktSize::6 0 # Categorize read packet sizes
-testsys.physmem.readPktSize::7 0 # Categorize read packet sizes
-testsys.physmem.readPktSize::8 0 # Categorize read packet sizes
-testsys.physmem.writePktSize::0 0 # categorize write packet sizes
-testsys.physmem.writePktSize::1 0 # categorize write packet sizes
-testsys.physmem.writePktSize::2 0 # categorize write packet sizes
-testsys.physmem.writePktSize::3 0 # categorize write packet sizes
-testsys.physmem.writePktSize::4 0 # categorize write packet sizes
-testsys.physmem.writePktSize::5 0 # categorize write packet sizes
-testsys.physmem.writePktSize::6 0 # categorize write packet sizes
-testsys.physmem.writePktSize::7 0 # categorize write packet sizes
-testsys.physmem.writePktSize::8 0 # categorize write packet sizes
-testsys.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-testsys.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-testsys.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-testsys.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-testsys.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-testsys.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-testsys.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-testsys.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-testsys.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+testsys.physmem.writePktSize::0 0 # Categorize write packet sizes
+testsys.physmem.writePktSize::1 0 # Categorize write packet sizes
+testsys.physmem.writePktSize::2 0 # Categorize write packet sizes
+testsys.physmem.writePktSize::3 0 # Categorize write packet sizes
+testsys.physmem.writePktSize::4 0 # Categorize write packet sizes
+testsys.physmem.writePktSize::5 0 # Categorize write packet sizes
+testsys.physmem.writePktSize::6 0 # Categorize write packet sizes
testsys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
testsys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
testsys.physmem.totQLat 0 # Total cycles spent in queuing delays
testsys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
testsys.physmem.totBusLat 0 # Total cycles spent in databus access
drivesys.physmem.readPktSize::4 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::5 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::6 0 # Categorize read packet sizes
-drivesys.physmem.readPktSize::7 0 # Categorize read packet sizes
-drivesys.physmem.readPktSize::8 0 # Categorize read packet sizes
-drivesys.physmem.writePktSize::0 0 # categorize write packet sizes
-drivesys.physmem.writePktSize::1 0 # categorize write packet sizes
-drivesys.physmem.writePktSize::2 0 # categorize write packet sizes
-drivesys.physmem.writePktSize::3 0 # categorize write packet sizes
-drivesys.physmem.writePktSize::4 0 # categorize write packet sizes
-drivesys.physmem.writePktSize::5 0 # categorize write packet sizes
-drivesys.physmem.writePktSize::6 0 # categorize write packet sizes
-drivesys.physmem.writePktSize::7 0 # categorize write packet sizes
-drivesys.physmem.writePktSize::8 0 # categorize write packet sizes
-drivesys.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-drivesys.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-drivesys.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-drivesys.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-drivesys.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-drivesys.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-drivesys.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-drivesys.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-drivesys.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+drivesys.physmem.writePktSize::0 0 # Categorize write packet sizes
+drivesys.physmem.writePktSize::1 0 # Categorize write packet sizes
+drivesys.physmem.writePktSize::2 0 # Categorize write packet sizes
+drivesys.physmem.writePktSize::3 0 # Categorize write packet sizes
+drivesys.physmem.writePktSize::4 0 # Categorize write packet sizes
+drivesys.physmem.writePktSize::5 0 # Categorize write packet sizes
+drivesys.physmem.writePktSize::6 0 # Categorize write packet sizes
drivesys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
drivesys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
drivesys.physmem.totQLat 0 # Total cycles spent in queuing delays
drivesys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
drivesys.physmem.totBusLat 0 # Total cycles spent in databus access
sim_ticks 19476000 # Number of ticks simulated
final_tick 19476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 78389 # Simulator instruction rate (inst/s)
-host_op_rate 78368 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 238789679 # Simulator tick rate (ticks/s)
-host_mem_usage 223680 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 1322 # Simulator instruction rate (inst/s)
+host_op_rate 1322 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4028719 # Simulator tick rate (ticks/s)
+host_mem_usage 223696 # Number of bytes of host memory used
+host_seconds 4.83 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 469 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 0 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 0 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2628216 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13374466 # Sum of mem lat for all requests
+system.physmem.totQLat 2627750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 13374000 # Sum of mem lat for all requests
system.physmem.totBusLat 2345000 # Total cycles spent in databus access
system.physmem.totBankLat 8401250 # Total cycles spent in bank access
-system.physmem.avgQLat 5603.87 # Average queueing delay per request
+system.physmem.avgQLat 5602.88 # Average queueing delay per request
system.physmem.avgBankLat 17913.11 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 28516.99 # Average memory access latency
+system.physmem.avgMemAccLat 28515.99 # Average memory access latency
system.physmem.avgRdBW 1537.89 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1537.89 # Average consumed read bandwidth in MB/s
system.cpu.icache.overall_avg_mshr_miss_latency::total 52524.834437 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 199.973805 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 199.973821 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 143.049582 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 56.924223 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 143.049595 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 56.924226 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004366 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001737 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.006103 # Average percentage of cache occupancy
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11816499 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4177366 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15993865 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2666348 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2666348 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11816499 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6843714 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 18660213 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11816499 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6843714 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 18660213 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11816250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4177308 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15993558 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2666299 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2666299 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11816250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6843607 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 18659857 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11816250 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6843607 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 18659857 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39257.471761 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43972.273684 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40388.547980 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36525.315068 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36525.315068 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39257.471761 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40736.392857 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39787.234542 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39257.471761 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40736.392857 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39787.234542 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39256.644518 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43971.663158 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40387.772727 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36524.643836 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36524.643836 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39256.644518 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40735.755952 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39786.475480 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39256.644518 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40735.755952 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39786.475480 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 104.433203 # Cycle average of tags in use
---------- Begin Simulation Statistics ----------
sim_seconds 0.000016 # Number of seconds simulated
-sim_ticks 16030500 # Number of ticks simulated
-final_tick 16030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 16039500 # Number of ticks simulated
+final_tick 16039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 76258 # Simulator instruction rate (inst/s)
-host_op_rate 76239 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 191753794 # Simulator tick rate (ticks/s)
-host_mem_usage 225728 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 1336 # Simulator instruction rate (inst/s)
+host_op_rate 1336 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3362323 # Simulator tick rate (ticks/s)
+host_mem_usage 225744 # Number of bytes of host memory used
+host_seconds 4.77 # Real time elapsed on the host
sim_insts 6372 # Number of instructions simulated
sim_ops 6372 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory
system.physmem.num_reads::total 486 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1245625526 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 694675774 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1940301301 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1245625526 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1245625526 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1245625526 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 694675774 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1940301301 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1244926587 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 694285981 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1939212569 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1244926587 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1244926587 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1244926587 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 694285981 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1939212569 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 486 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 15817000 # Total gap between requests
+system.physmem.totGap 15803000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 486 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 0 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 0 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 247 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2909986 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13644986 # Sum of mem lat for all requests
+system.physmem.totQLat 2921750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 13656750 # Sum of mem lat for all requests
system.physmem.totBusLat 2430000 # Total cycles spent in databus access
system.physmem.totBankLat 8305000 # Total cycles spent in bank access
-system.physmem.avgQLat 5987.63 # Average queueing delay per request
+system.physmem.avgQLat 6011.83 # Average queueing delay per request
system.physmem.avgBankLat 17088.48 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 28076.10 # Average memory access latency
-system.physmem.avgRdBW 1940.30 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 28100.31 # Average memory access latency
+system.physmem.avgRdBW 1939.21 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1940.30 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1939.21 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 15.16 # Data bus utilization in percentage
+system.physmem.busUtil 15.15 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.85 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 396 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.48 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 32545.27 # Average gap between requests
+system.physmem.avgGap 32516.46 # Average gap between requests
system.cpu.branchPred.lookups 2896 # Number of BP lookups
system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 513 # Number of conditional branches incorrect
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 32062 # number of cpu cycles simulated
+system.cpu.numCycles 32080 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 8352 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 14509 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.090325 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.515470 # Number of inst fetches per cycle
+system.cpu.fetch.branchRate 0.090274 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.515181 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 9308 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 1148 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2753 # Number of cycles decode is running
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 10806 # Type of FU issued
-system.cpu.iq.rate 0.337034 # Inst issue rate
+system.cpu.iq.rate 0.336845 # Inst issue rate
system.cpu.iq.fu_busy_cnt 118 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010920 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 36268 # Number of integer instruction queue reads
system.cpu.iew.exec_refs 3233 # number of memory reference insts executed
system.cpu.iew.exec_branches 1613 # Number of branches executed
system.cpu.iew.exec_stores 1101 # Number of stores executed
-system.cpu.iew.exec_rate 0.316699 # Inst execution rate
+system.cpu.iew.exec_rate 0.316521 # Inst execution rate
system.cpu.iew.wb_sent 9857 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 9710 # cumulative count of insts written-back
system.cpu.iew.wb_producers 5134 # num instructions producing a value
system.cpu.iew.wb_consumers 6919 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.302851 # insts written-back per cycle
+system.cpu.iew.wb_rate 0.302681 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.742015 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 6741 # The number of squashed insts skipped by commit
system.cpu.rob.rob_reads 25928 # The number of ROB reads
system.cpu.rob.rob_writes 27481 # The number of ROB writes
system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 17553 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 17571 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 6372 # Number of Instructions Simulated
system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 6372 # Number of Instructions Simulated
-system.cpu.cpi 5.031701 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 5.031701 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.198740 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.198740 # IPC: Total IPC of All Threads
+system.cpu.cpi 5.034526 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 5.034526 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.198628 # IPC: Instructions Per Cycle
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system.physmem.rdQLenPdf::1 87 # What read queue length does an incoming req see
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system.physmem.totBankLat 5183750 # Total cycles spent in bank access
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system.physmem.avgBankLat 19057.90 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgRdBW 1861.82 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1861.82 # Average consumed read bandwidth in MB/s
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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sim_ticks 13709000 # Number of ticks simulated
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sim_insts 4591 # Number of instructions simulated
sim_ops 5729 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 394 # Categorize read packet sizes
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-system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see
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system.physmem.totBusLat 1970000 # Total cycles spent in databus access
system.physmem.totBankLat 7273750 # Total cycles spent in bank access
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system.physmem.avgBankLat 18461.29 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s
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sim_ticks 13709000 # Number of ticks simulated
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sim_insts 4591 # Number of instructions simulated
sim_ops 5729 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 394 # Categorize read packet sizes
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-system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency
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-host_op_rate 100592 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 334460805 # Simulator tick rate (ticks/s)
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sim_insts 5814 # Number of instructions simulated
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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-system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.avgBankLat 19854.40 # Average bank access latency per request
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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-host_inst_rate 76348 # Simulator instruction rate (inst/s)
-host_op_rate 76319 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 251939378 # Simulator tick rate (ticks/s)
-host_mem_usage 226380 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
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+host_op_rate 44889 # Simulator op (including micro ops) rate (op/s)
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sim_insts 5156 # Number of instructions simulated
sim_ops 5156 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 478 # Categorize read packet sizes
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-system.physmem.writePktSize::1 0 # categorize write packet sizes
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-system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.avgBankLat 19589.44 # Average bank access latency per request
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system.physmem.avgRdBW 1796.73 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1796.73 # Average consumed read bandwidth in MB/s
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39503.877976 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48141.852113 # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency
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-host_inst_rate 87376 # Simulator instruction rate (inst/s)
-host_op_rate 87343 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 221965921 # Simulator tick rate (ticks/s)
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-host_seconds 0.07 # Real time elapsed on the host
+host_inst_rate 62176 # Simulator instruction rate (inst/s)
+host_op_rate 62167 # Simulator op (including micro ops) rate (op/s)
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+host_mem_usage 222660 # Number of bytes of host memory used
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sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 446 # Categorize read packet sizes
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-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.avgBankLat 18528.59 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
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+system.physmem.avgMemAccLat 28653.59 # Average memory access latency
system.physmem.avgRdBW 1938.54 # Average achieved read bandwidth in MB/s
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37916.049275 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47941.564356 # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37915.272464 # average overall mshr miss latency
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sim_ticks 16783500 # Number of ticks simulated
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-host_inst_rate 84096 # Simulator instruction rate (inst/s)
-host_op_rate 84062 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 264753473 # Simulator tick rate (ticks/s)
-host_mem_usage 230292 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 48421 # Simulator instruction rate (inst/s)
+host_op_rate 48416 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 152524495 # Simulator tick rate (ticks/s)
+host_mem_usage 230316 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 423 # Categorize read packet sizes
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system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgRdBW 1613.01 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1613.01 # Average consumed read bandwidth in MB/s
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45923.753086 # average ReadExReq mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39887.391003 # average overall mshr miss latency
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45923.296296 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39886.602076 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47649.835821 # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39886.602076 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47649.835821 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42345.877069 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 84.137936 # Cycle average of tags in use
sim_ticks 15468000 # Number of ticks simulated
final_tick 15468000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 31666 # Simulator instruction rate (inst/s)
-host_op_rate 57357 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 91020367 # Simulator tick rate (ticks/s)
-host_mem_usage 241544 # Number of bytes of host memory used
+host_inst_rate 31901 # Simulator instruction rate (inst/s)
+host_op_rate 57781 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 91692634 # Simulator tick rate (ticks/s)
+host_mem_usage 241568 # Number of bytes of host memory used
host_seconds 0.17 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9746 # Number of ops (including micro ops) simulated
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 451 # Categorize read packet sizes
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-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
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-system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.rdQLenPdf::0 231 # What read queue length does an incoming req see
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system.physmem.totBusLat 2255000 # Total cycles spent in databus access
system.physmem.totBankLat 9006250 # Total cycles spent in bank access
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system.physmem.avgBankLat 19969.51 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
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+system.physmem.avgMemAccLat 29181.26 # Average memory access latency
system.physmem.avgRdBW 1857.77 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1857.77 # Average consumed read bandwidth in MB/s
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sim_ticks 24473000 # Number of ticks simulated
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sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 4068 # Simulator instruction rate (inst/s)
-host_op_rate 4068 # Simulator op (including micro ops) rate (op/s)
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-host_mem_usage 226312 # Number of bytes of host memory used
-host_seconds 3.13 # Real time elapsed on the host
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sim_ops 12745 # Number of ops (including micro ops) simulated
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system.physmem.avgRdBW 2536.67 # Average achieved read bandwidth in MB/s
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64537.032154 # average overall mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements::1 0 # number of replacements
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final_tick 23146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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+host_mem_usage 230244 # Number of bytes of host memory used
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sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39235.276888 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 99.212064 # Cycle average of tags in use
sim_ticks 23775500 # Number of ticks simulated
final_tick 23775500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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-host_op_rate 69204 # Simulator op (including micro ops) rate (op/s)
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+host_op_rate 69023 # Simulator op (including micro ops) rate (op/s)
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host_seconds 0.21 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 483 # Categorize read packet sizes
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-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.totBusLat 2415000 # Total cycles spent in databus access
system.physmem.totBankLat 8566250 # Total cycles spent in bank access
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system.physmem.avgBankLat 17735.51 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgRdBW 1300.16 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1300.16 # Average consumed read bandwidth in MB/s
system.cpu.icache.overall_avg_mshr_miss_latency::total 52118.343195 # average overall mshr miss latency
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system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks.
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38986.684524 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55701.639456 # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38985.901786 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55701.163265 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44073.155280 # average overall mshr miss latency
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sim_ticks 105801500 # Number of ticks simulated
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sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 99938 # Simulator instruction rate (inst/s)
-host_op_rate 99937 # Simulator op (including micro ops) rate (op/s)
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-host_seconds 10.37 # Real time elapsed on the host
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+host_op_rate 173787 # Simulator op (including micro ops) rate (op/s)
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+host_mem_usage 247480 # Number of bytes of host memory used
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sim_insts 1035849 # Number of instructions simulated
sim_ops 1035849 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 22848 # Number of bytes read from this memory
system.physmem.bw_total::total 399238196 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 661 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 978 # Reqs generatd by CPU via cache - shady
+system.physmem.cpureqs 732 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 42240 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 42240 # bytesRead derated as per pkt->getSize()
system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 661 # Categorize read packet sizes
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-system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.rdQLenPdf::0 377 # What read queue length does an incoming req see
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+system.physmem.avgQLat 6167.17 # Average queueing delay per request
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system.physmem.avgRdBW 399.24 # Average achieved read bandwidth in MB/s
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system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10222.777778 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.263158 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10094.562500 # average UpgradeReq mshr miss latency
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 100000000000 # Number of ticks simulated
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 29045358432 # Simulator tick rate (ticks/s)
-host_mem_usage 222412 # Number of bytes of host memory used
-host_seconds 3.44 # Real time elapsed on the host
+host_tick_rate 31852968745 # Simulator tick rate (ticks/s)
+host_mem_usage 226592 # Number of bytes of host memory used
+host_seconds 3.14 # Real time elapsed on the host
system.physmem.bytes_read::cpu 213337536 # Number of bytes read from this memory
system.physmem.bytes_read::total 213337536 # Number of bytes read from this memory
system.physmem.num_reads::cpu 3333399 # Number of read requests responded to by this memory
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 3333400 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
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-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.rdQLenPdf::0 3200711 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 105371 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 4811 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3752 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 4283 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 3751 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 3205 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2146 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1602 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::10 1076 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 546 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 6115686626 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 69505296626 # Sum of mem lat for all requests
+system.physmem.totQLat 6112380100 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 69501990100 # Sum of mem lat for all requests
system.physmem.totBusLat 16667000000 # Total cycles spent in databus access
system.physmem.totBankLat 46722610000 # Total cycles spent in bank access
-system.physmem.avgQLat 1834.67 # Average queueing delay per request
+system.physmem.avgQLat 1833.68 # Average queueing delay per request
system.physmem.avgBankLat 14016.50 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 20851.17 # Average memory access latency
+system.physmem.avgMemAccLat 20850.18 # Average memory access latency
system.physmem.avgRdBW 2133.38 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2133.38 # Average consumed read bandwidth in MB/s
system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s)
system.monitor.totalWrittenBytes 0 # Number of bytes written
system.monitor.readLatencyHist::samples 3333399 # Read request-response latency
-system.monitor.readLatencyHist::mean 20879.051770 # Read request-response latency
-system.monitor.readLatencyHist::gmean 19622.150808 # Read request-response latency
-system.monitor.readLatencyHist::stdev 15688.008500 # Read request-response latency
+system.monitor.readLatencyHist::mean 20878.092191 # Read request-response latency
+system.monitor.readLatencyHist::gmean 19621.155070 # Read request-response latency
+system.monitor.readLatencyHist::stdev 15688.085413 # Read request-response latency
system.monitor.readLatencyHist::0-32767 3201881 96.05% 96.05% # Read request-response latency
system.monitor.readLatencyHist::32768-65535 104731 3.14% 99.20% # Read request-response latency
system.monitor.readLatencyHist::65536-98303 5355 0.16% 99.36% # Read request-response latency
projects / gem5.git / commitdiff