verilog: disallow overriding global parameters

It was previously possible to override global parameters on a
per-instance basis. This could be dangerous when using positional
parameter bindings, hiding oversupplied parameters.

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index b601d2e259dc7d4f9978f4495c4809cd553226dd..06e2e23a8393c775e89b0537e39d8741fb6d6159 100644 (file)
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1286,6 +1286,8 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
                }
                else {
                        // must be global definition
+                       if ((*it)->type == AST_PARAMETER)
+                               (*it)->type = AST_LOCALPARAM; // cannot be overridden
                        (*it)->simplify(false, false, false, 1, -1, false, false); //process enum/other declarations
                        design->verilog_globals.push_back((*it)->clone());
                        current_scope.clear();

diff --git a/tests/verilog/global_parameter.ys b/tests/verilog/global_parameter.ys
new file mode 100644 (file)
index 0000000..a7a3cdd
--- /dev/null
+++ b/tests/verilog/global_parameter.ys
@@ -0,0 +1,16 @@
+read_verilog -sv <<EOF
+parameter P = 1;
+module example(
+    output integer out
+);
+    assign out = P;
+endmodule
+module top(
+    output integer out
+);
+    example #(2) e1(out);
+endmodule
+EOF
+
+logger -expect error "Can't find object for defparam" 1
+hierarchy