Oops

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 7bac1b974233666771e9e6fe6a1cf97479bda66b..d48c646c0846b14ea3d6cc92b508caea106c3654 100644 (file)
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -192,6 +192,7 @@ void pack_xilinx_simd(Module *module, const std::vector<Cell*> &selected_cells)
                SigSpec Y = lane->getPort("\\Y");
                A.extend_u0(24, lane->getParam("\\A_SIGNED").as_bool());
                B.extend_u0(24, lane->getParam("\\B_SIGNED").as_bool());
+               C.append(A);
                AB.append(B);
                if (GetSize(Y) < 25)
                        Y.append(module->addWire(NEW_ID, 25-GetSize(Y)));