Share some ARM target dependent code from GDB with GDBServer

This patch is in preparation for software single stepping support on ARM
it shares some functions and definitions that will be needed.

No regressions, tested on ubuntu 14.04 ARMv7 and x86.
With gdbserver-{native,extended} / { -marm -mthumb }

Not tested: wince/bsd build.

gdb/ChangeLog:

	* arch/arm.c (bitcount): Move from arm-tdep.c.
	(condition_true): Likewise.
	* arch/arm.h (Instruction Definitions): Move form arm-tdep.h.
	(condition_true): Move defenition from arm-tdep.h.
	(bitcount): Likewise.
	* arm-tdep.c (condition_true): Move to arch/arm.c.
	(bitcount): Likewise.
	* arm-tdep.h (Instruction Definitions): Move to arch/arm.h.
	* arm-wince-tdep.c: Include arch/arm.h.
	* armnbsd-tdep.c: Likewise.

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 3968c479dc6febc430c304ee3ca1116a77fd24b1..507a1cc53936f02445ceaa91a84fe38d93fcec00 100644 (file)
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,16 @@
+2015-12-18  Antoine Tremblay  <antoine.tremblay@ericsson.com>
+
+       * arch/arm.c (bitcount): Move from arm-tdep.c.
+       (condition_true): Likewise.
+       * arch/arm.h (Instruction Definitions): Move form arm-tdep.h.
+       (condition_true): Move defenition from arm-tdep.h.
+       (bitcount): Likewise.
+       * arm-tdep.c (condition_true): Move to arch/arm.c.
+       (bitcount): Likewise.
+       * arm-tdep.h (Instruction Definitions): Move to arch/arm.h.
+       * arm-wince-tdep.c: Include arch/arm.h.
+       * armnbsd-tdep.c: Likewise.
+
 2015-12-17  Pedro Alves  <palves@redhat.com>
 
        PR threads/19354

diff --git a/gdb/arch/arm.c b/gdb/arch/arm.c
index b11c6849309c7b450dabcd216cd0d52bb1e56923..426377fa880274adbb15d860d2fced2f689895ed 100644 (file)
--- a/gdb/arch/arm.c
+++ b/gdb/arch/arm.c
@@ -20,8 +20,7 @@
 #include "common-defs.h"
 #include "arm.h"
 
-/* Return the size in bytes of the complete Thumb instruction whose
-   first halfword is INST1.  */
+/* See arm.h.  */
 
 int
 thumb_insn_size (unsigned short inst1)
@@ -31,3 +30,60 @@ thumb_insn_size (unsigned short inst1)
   else
     return 2;
 }
+
+/* See arm.h.  */
+
+int
+bitcount (unsigned long val)
+{
+  int nbits;
+  for (nbits = 0; val != 0; nbits++)
+    val &= val - 1;            /* Delete rightmost 1-bit in val.  */
+  return nbits;
+}
+
+/* See arm.h.  */
+
+int
+condition_true (unsigned long cond, unsigned long status_reg)
+{
+  if (cond == INST_AL || cond == INST_NV)
+    return 1;
+
+  switch (cond)
+    {
+    case INST_EQ:
+      return ((status_reg & FLAG_Z) != 0);
+    case INST_NE:
+      return ((status_reg & FLAG_Z) == 0);
+    case INST_CS:
+      return ((status_reg & FLAG_C) != 0);
+    case INST_CC:
+      return ((status_reg & FLAG_C) == 0);
+    case INST_MI:
+      return ((status_reg & FLAG_N) != 0);
+    case INST_PL:
+      return ((status_reg & FLAG_N) == 0);
+    case INST_VS:
+      return ((status_reg & FLAG_V) != 0);
+    case INST_VC:
+      return ((status_reg & FLAG_V) == 0);
+    case INST_HI:
+      return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
+    case INST_LS:
+      return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
+    case INST_GE:
+      return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
+    case INST_LT:
+      return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
+    case INST_GT:
+      return (((status_reg & FLAG_Z) == 0)
+             && (((status_reg & FLAG_N) == 0)
+                 == ((status_reg & FLAG_V) == 0)));
+    case INST_LE:
+      return (((status_reg & FLAG_Z) != 0)
+             || (((status_reg & FLAG_N) == 0)
+                 != ((status_reg & FLAG_V) == 0)));
+    }
+  return 1;
+}

diff --git a/gdb/arch/arm.h b/gdb/arch/arm.h
index a054776da1136a1517b9eb1964c9acc817093053..1a877bcf3290cbc6543d0ddb488b42b761c8470d 100644 (file)
--- a/gdb/arch/arm.h
+++ b/gdb/arch/arm.h
@@ -58,6 +58,36 @@ enum gdb_regnum {
   ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
 };
 
+/* Instruction condition field values.  */
+#define INST_EQ                0x0
+#define INST_NE                0x1
+#define INST_CS                0x2
+#define INST_CC                0x3
+#define INST_MI                0x4
+#define INST_PL                0x5
+#define INST_VS                0x6
+#define INST_VC                0x7
+#define INST_HI                0x8
+#define INST_LS                0x9
+#define INST_GE                0xa
+#define INST_LT                0xb
+#define INST_GT                0xc
+#define INST_LE                0xd
+#define INST_AL                0xe
+#define INST_NV                0xf
+
+#define FLAG_N         0x80000000
+#define FLAG_Z         0x40000000
+#define FLAG_C         0x20000000
+#define FLAG_V         0x10000000
+
+#define CPSR_T         0x20
+
+#define XPSR_T         0x01000000
+
+/* Size of integer registers.  */
+#define INT_REGISTER_SIZE              4
+
 /* Addresses for calling Thumb functions have the bit 0 set.
    Here are some macros to test, set, or clear bit 0 of addresses.  */
 #define IS_THUMB_ADDR(addr)    ((addr) & 1)
@@ -68,4 +98,10 @@ enum gdb_regnum {
    first halfword is INST1.  */
 int thumb_insn_size (unsigned short inst1);
 
+/* Returns true if the condition evaluates to true.  */
+int condition_true (unsigned long cond, unsigned long status_reg);
+
+/* Return number of 1-bits in VAL.  */
+int bitcount (unsigned long val);
+
 #endif

diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 6ce6f09c37ff164d327281df1cdbe5a3d4f4136f..848af97362af7f97842fe58929366504b4da2b79 100644 (file)
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -4301,50 +4301,6 @@ convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
                               &d, dbl);
 }
 
-static int
-condition_true (unsigned long cond, unsigned long status_reg)
-{
-  if (cond == INST_AL || cond == INST_NV)
-    return 1;
-
-  switch (cond)
-    {
-    case INST_EQ:
-      return ((status_reg & FLAG_Z) != 0);
-    case INST_NE:
-      return ((status_reg & FLAG_Z) == 0);
-    case INST_CS:
-      return ((status_reg & FLAG_C) != 0);
-    case INST_CC:
-      return ((status_reg & FLAG_C) == 0);
-    case INST_MI:
-      return ((status_reg & FLAG_N) != 0);
-    case INST_PL:
-      return ((status_reg & FLAG_N) == 0);
-    case INST_VS:
-      return ((status_reg & FLAG_V) != 0);
-    case INST_VC:
-      return ((status_reg & FLAG_V) == 0);
-    case INST_HI:
-      return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
-    case INST_LS:
-      return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
-    case INST_GE:
-      return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
-    case INST_LT:
-      return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
-    case INST_GT:
-      return (((status_reg & FLAG_Z) == 0)
-             && (((status_reg & FLAG_N) == 0)
-                 == ((status_reg & FLAG_V) == 0)));
-    case INST_LE:
-      return (((status_reg & FLAG_Z) != 0)
-             || (((status_reg & FLAG_N) == 0)
-                 != ((status_reg & FLAG_V) == 0)));
-    }
-  return 1;
-}
-
 static unsigned long
 shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry,
                 unsigned long pc_val, unsigned long status_reg)
@@ -4395,17 +4351,6 @@ shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry,
   return res & 0xffffffff;
 }
 
-/* Return number of 1-bits in VAL.  */
-
-static int
-bitcount (unsigned long val)
-{
-  int nbits;
-  for (nbits = 0; val != 0; nbits++)
-    val &= val - 1;            /* Delete rightmost 1-bit in val.  */
-  return nbits;
-}
-
 static int
 thumb_advance_itstate (unsigned int itstate)
 {

diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h
index 3e06f79dd492626a4a9d160f5998731d4322167f..9b8447b0af4f006b2e48a506b79c0cb0d0dca7fd 100644 (file)
--- a/gdb/arm-tdep.h
+++ b/gdb/arm-tdep.h
@@ -26,9 +26,6 @@ struct address_space;
 
 #include "arch/arm.h"
 
-/* Size of integer registers.  */
-#define INT_REGISTER_SIZE              4
-
 /* Say how long FP registers are.  Used for documentation purposes and
    code readability in this header.  IEEE extended doubles are 80
    bits.  DWORD aligned they use 96 bits.  */
@@ -50,32 +47,6 @@ struct address_space;
 #define NUM_GREGS      16      /* Number of general purpose registers.  */
 
 
-/* Instruction condition field values.  */
-#define INST_EQ                0x0
-#define INST_NE                0x1
-#define INST_CS                0x2
-#define INST_CC                0x3
-#define INST_MI                0x4
-#define INST_PL                0x5
-#define INST_VS                0x6
-#define INST_VC                0x7
-#define INST_HI                0x8
-#define INST_LS                0x9
-#define INST_GE                0xa
-#define INST_LT                0xb
-#define INST_GT                0xc
-#define INST_LE                0xd
-#define INST_AL                0xe
-#define INST_NV                0xf
-
-#define FLAG_N         0x80000000
-#define FLAG_Z         0x40000000
-#define FLAG_C         0x20000000
-#define FLAG_V         0x10000000
-
-#define CPSR_T         0x20
-
-#define XPSR_T         0x01000000
 
 /* Type of floating-point code in use by inferior.  There are really 3 models
    that are traditionally supported (plus the endianness issue), but gcc can

diff --git a/gdb/arm-wince-tdep.c b/gdb/arm-wince-tdep.c
index 72295ba4caee51ca1cc6bef0768b51d185ded636..3abd89d541b4c494b7dc44dc73ede09b1b2d9c08 100644 (file)
--- a/gdb/arm-wince-tdep.c
+++ b/gdb/arm-wince-tdep.c
@@ -24,6 +24,7 @@
 #include "target.h"
 #include "frame.h"
 
+#include "arch/arm.h"
 #include "arm-tdep.h"
 #include "windows-tdep.h"
 

diff --git a/gdb/armnbsd-tdep.c b/gdb/armnbsd-tdep.c
index 4c128c2943c63838a0ee18495b6565d8077001b7..14eceaa6cdbaf10d30d1b4388b375980ecfab616 100644 (file)
--- a/gdb/armnbsd-tdep.c
+++ b/gdb/armnbsd-tdep.c
@@ -20,6 +20,7 @@
 #include "defs.h"
 #include "osabi.h"
 
+#include "arch/arm.h"
 #include "arm-tdep.h"
 #include "solib-svr4.h"