ARM: update TLB to set request packet ASID field

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 5e5735de7e6fea00398b41e27034f12a71322b83..1f84fa4ca04014b640c02ce87e4a7eeb342a9f4c 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -436,6 +436,11 @@ namespace ArmISA
        Bitfield<31,30> or7;
    EndBitUnion(NMRR)
 
+   BitUnion32(CONTEXTIDR)
+      Bitfield<7,0>  asid;
+      Bitfield<31,8> procid;
+   EndBitUnion(CONTEXTIDR)
+
    BitUnion32(L2CTLR)
       Bitfield<2,0>   sataRAMLatency;
       Bitfield<4,3>   reserved_4_3;

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 942f85120531680fbc31a90043b1481e305cb41c..a03e445cfa578fe3aa5cfb503ca5011b0b832758 100644 (file)
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -467,6 +467,8 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
     bool is_write = (mode == Write);
     bool is_priv = isPriv && !(flags & UserMode);
 
+    req->setAsid(contextId.asid);
+
     DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n",
             isPriv, flags & UserMode);
     // If this is a clrex instruction, provide a PA of 0 with no fault

diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index f78e38a3d6b9ff265db2607f0c6215e6c1904a31..3464e42b3a2412e5bcc745e696fb5827a5aee2ed 100644 (file)
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -222,7 +222,7 @@ class TLB : public BaseTLB
 protected:
     SCTLR sctlr;
     bool isPriv;
-    uint32_t contextId;
+    CONTEXTIDR contextId;
     PRRR prrr;
     NMRR nmrr;
     uint32_t dacr;