Remove copys from isa_desc, and implement a store and forward bus bridge

arch/alpha/isa_desc:
    Just to make sure, remove the new copy instructions until everything works.

--HG--
extra : convert_revision : cdd3d4c8fa415175aaee04f4a99340dcf82dbc3a

diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 0cfe5b4525da299d4ae3486d790fad8ea99902ab..a7665210fc88c6e48eac121bb1ee975146ffb95b 100644 (file)
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -1854,9 +1854,9 @@ decode OPCODE default Unknown::unknown() {
        0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }});
        0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED);
        0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED);
-       0x20: copy_load({{EA = Ra;}}, 
-                       {{memAccessObj->copySrcTranslate(EA);}},
-                       IsMemRef, IsLoad, IsCopy);
+       //0x20: copy_load({{EA = Ra;}}, 
+       //                {{memAccessObj->copySrcTranslate(EA);}},
+       //              IsMemRef, IsLoad, IsCopy);
     }
 
     format LoadOrPrefetch {
@@ -1876,9 +1876,9 @@ decode OPCODE default Unknown::unknown() {
        0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }});
        0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }});
        0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }});
-       0x24: copy_store({{EA = Rb;}},
-                        {{memAccessObj->copy(EA);}},
-                        IsMemRef, IsStore, IsCopy);
+       //0x24: copy_store({{EA = Rb;}},
+       //                 {{memAccessObj->copy(EA);}},
+       //               IsMemRef, IsStore, IsCopy);
     }
 
     format StoreCond {