fixed MOESI_CMP_directory bug

diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm
index edd67707e14fb5158c92132b6f921808e15be049..bafbc404eb03b052877491d415db0f2b59c256f4 100644 (file)
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm
@@ -101,7 +101,7 @@ machine(Directory, "Directory protocol")
   }
 
   structure(TBE, desc="...") {
-    Address address,   desc="Address for this entry";
+    Address PhysicalAddress,   desc="Physical address for this entry";
     int Len,           desc="Length of request";
     DataBlock DataBlk, desc="DataBlk";
     MachineID Requestor, desc="original requestor";
@@ -245,9 +245,9 @@ machine(Directory, "Directory protocol")
         } else if (in_msg.Type == CoherenceRequestType:PUTO_SHARERS) {
           trigger(Event:PUTO_SHARERS, in_msg.Address);
         } else if (in_msg.Type == CoherenceRequestType:DMA_READ) {
-          trigger(Event:DMA_READ, in_msg.Address);
+          trigger(Event:DMA_READ, makeLineAddress(in_msg.Address));
         } else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) {
-          trigger(Event:DMA_WRITE, in_msg.Address);
+          trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Address));
         } else {
           error("Invalid message");
         }
@@ -527,12 +527,15 @@ machine(Directory, "Directory protocol")
   }
 
   action(l_writeDMADataToMemoryFromTBE, "\ll", desc="Write data from a DMA_WRITE to memory") {
-    directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(address), TBEs[address].Len);
+    directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, 
+                                          addressOffset(TBEs[address].PhysicalAddress), 
+                                          TBEs[address].Len);
   }
 
   action(v_allocateTBE, "v", desc="Allocate TBE entry") {
     peek (requestQueue_in, RequestMsg) {
       TBEs.allocate(address);
+      TBEs[address].PhysicalAddress := in_msg.Address;
       TBEs[address].Len := in_msg.Len;
       TBEs[address].DataBlk := in_msg.DataBlk;
       TBEs[address].Requestor := in_msg.Requestor;

diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm
index da10695d052db602e5ddf9e6cb25a3b842816383..ae86e24dae2c4c0865660cd6aa96497f44e8ee7a 100644 (file)
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm
@@ -83,9 +83,9 @@ machine(DMA, "DMA Controller")
     if (dmaRequestQueue_in.isReady()) {
       peek(dmaRequestQueue_in, SequencerMsg) {
         if (in_msg.Type == SequencerRequestType:LD ) {
-          trigger(Event:ReadRequest, in_msg.PhysicalAddress);
+          trigger(Event:ReadRequest, in_msg.LineAddress);
         } else if (in_msg.Type == SequencerRequestType:ST) {
-          trigger(Event:WriteRequest, in_msg.PhysicalAddress);
+          trigger(Event:WriteRequest, in_msg.LineAddress);
         } else {
           error("Invalid request type");
         }
@@ -97,12 +97,12 @@ machine(DMA, "DMA Controller")
     if (dmaResponseQueue_in.isReady()) {
       peek( dmaResponseQueue_in, ResponseMsg) {
         if (in_msg.Type == CoherenceResponseType:DMA_ACK) {
-          trigger(Event:DMA_Ack, in_msg.Address);
+          trigger(Event:DMA_Ack, makeLineAddress(in_msg.Address));
         } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE ||
                   in_msg.Type == CoherenceResponseType:DATA) {
-          trigger(Event:Data, in_msg.Address);
+          trigger(Event:Data, makeLineAddress(in_msg.Address));
         } else if (in_msg.Type == CoherenceResponseType:ACK) {
-          trigger(Event:Inv_Ack, in_msg.Address);
+          trigger(Event:Inv_Ack, makeLineAddress(in_msg.Address));
         } else {
           error("Invalid response type");
         }
@@ -126,7 +126,7 @@ machine(DMA, "DMA Controller")
   action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
     peek(dmaRequestQueue_in, SequencerMsg) {
       enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
-        out_msg.Address := address;
+        out_msg.Address := in_msg.PhysicalAddress;
         out_msg.Type := CoherenceRequestType:DMA_READ;
         out_msg.DataBlk := in_msg.DataBlk;
         out_msg.Len := in_msg.Len;
@@ -140,7 +140,7 @@ machine(DMA, "DMA Controller")
   action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
     peek(dmaRequestQueue_in, SequencerMsg) {
       enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
-          out_msg.Address := address;
+          out_msg.Address := in_msg.PhysicalAddress;
           out_msg.Type := CoherenceRequestType:DMA_WRITE;
           out_msg.DataBlk := in_msg.DataBlk;
           out_msg.Len := in_msg.Len;