radeon/winsys: add VCE support v4

v2: add fw version query
v3: add README.VCE
v4: avoid error msg when kernel doesn't support it

Signed-off-by: Christian König <christian.koenig@amd.com>

diff --git a/docs/README.VCE b/docs/README.VCE
new file mode 100644 (file)
index 0000000..d4b4cc5
--- /dev/null
+++ b/docs/README.VCE
@@ -0,0 +1,43 @@
+The software may implement third party technologies (e.g. third party
+libraries) that are not licensed to you by AMD and for which you may need
+to obtain licenses from other parties.  Unless explicitly stated otherwise,
+these third party technologies are not licensed hereunder.  Such third
+party technologies include, but are not limited, to H.264, MPEG-2, MPEG-4,
+AVC, and VC-1.  
+
+For MPEG-2 Intermediate Products: ANY USE OF THIS PRODUCT IN ANY MANNER OTHER
+THAN PERSONAL USE THAT COMPLIES WITH THE MPEG-2 STANDARD IS EXPRESSLY
+PROHIBITED WITHOUT A LICENSE UNDER APPLICABLE PATENTS IN THE MPEG-2 PATENT
+PORTFOLIO, WHICH LICENSES IS AVAILABLE FROM MPEG LA, LLC, 6312 S. Fiddlers
+Green Circle, Suite 400E, Greenwood Village, Colorado 80111 U.S.A.
+
+WARRANTY DISCLAIMER: THE SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
+KIND.  AMD DISCLAIMS ALL WARRANTIES, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+PARTICULAR PURPOSE, TITLE, NON-INFRINGEMENT, THAT THE SOFTWARE WILL RUN
+UNINTERRUPTED OR ERROR-FREE OR WARRANTIES ARISING FROM CUSTOM OF TRADE OR
+COURSE OF USAGE.  THE ENTIRE RISK ASSOCIATED WITH THE USE OF THE SOFTWARE IS
+ASSUMED BY YOU.  Some jurisdictions do not allow the exclusion of implied
+warranties, so the above exclusion may not apply to You.
+
+LIMITATION OF LIABILITY AND INDEMNIFICATION:  AMD AND ITS LICENSORS WILL NOT,
+UNDER ANY CIRCUMSTANCES BE LIABLE FOR ANY PUNITIVE, DIRECT, INCIDENTAL,
+INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES ARISING FROM USE OF THE SOFTWARE OR
+THIS AGREEMENT EVEN IF AMD AND ITS LICENSORS HAVE BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.  In no event shall AMD's total liability to You
+for all damages, losses, and causes of action (whether in contract, tort
+(including negligence) or otherwise) exceed the amount of $100 USD.  You agree
+to defend, indemnify and hold harmless AMD and its licensors, and any of their
+directors, officers, employees, affiliates or agents from and against any and
+all loss, damage, liability and other expenses (including reasonable
+attorneys' fees), resulting from Your use of the Software or violation of the
+terms and conditions of this Agreement.
+
+U.S. GOVERNMENT RESTRICTED RIGHTS: The Software is provided with "RESTRICTED
+RIGHTS." Use, duplication, or disclosure by the Government is subject to the
+restrictions as set forth in FAR 52.227-14 and DFAR252.227-7013, et seq., or
+its successor.  Use of the Software by the Government constitutes
+acknowledgement of AMD's proprietary rights in them.
+
+EXPORT RESTRICTIONS: The Software may be subject to export restrictions as
+stated in the Software License Agreement.

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index d8ad297295862edb880dd2b2f315703089fc74fb..ccba0c0b791a0e32312f1be98d251098d104424d 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -99,6 +99,10 @@
 #define RADEON_CS_RING_UVD          3
 #endif
 
+#ifndef RADEON_CS_RING_VCE
+#define RADEON_CS_RING_VCE          4
+#endif
+
 #ifndef RADEON_CS_END_OF_FRAME
 #define RADEON_CS_END_OF_FRAME      0x04
 #endif
@@ -538,6 +542,12 @@ static void radeon_drm_cs_flush(struct radeon_winsys_cs *rcs, unsigned flags, ui
             cs->cst->cs.num_chunks = 3;
             break;
 
+        case RING_VCE:
+            cs->cst->flags[0] = 0;
+            cs->cst->flags[1] = RADEON_CS_RING_VCE;
+            cs->cst->cs.num_chunks = 3;
+            break;
+
         default:
         case RING_GFX:
             cs->cst->flags[0] = 0;

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 427ee7df64255e95cc28391ec00968abccda4afb..c28f3a7b89e6c1ce23b83653d15be6653dfbab7a 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -97,10 +97,18 @@
 #define RADEON_INFO_RING_WORKING 0x15
 #endif
 
+#ifndef RADEON_INFO_VCE_FW_VERSION
+#define RADEON_INFO_VCE_FW_VERSION 0x1b
+#endif
+
 #ifndef RADEON_CS_RING_UVD
 #define RADEON_CS_RING_UVD     3
 #endif
 
+#ifndef RADEON_CS_RING_VCE
+#define RADEON_CS_RING_VCE     4
+#endif
+
 static struct util_hash_table *fd_tab = NULL;
 
 /* Enable/disable feature access for one command stream.
@@ -341,13 +349,23 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
         ws->info.r600_has_dma = TRUE;
     }
 
-    /* Check for UVD */
+    /* Check for UVD and VCE */
     ws->info.has_uvd = FALSE;
+    ws->info.vce_fw_version = 0x00000000;
     if (ws->info.drm_minor >= 32) {
        uint32_t value = RADEON_CS_RING_UVD;
         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
                                  "UVD Ring working", &value))
             ws->info.has_uvd = value;
+
+        value = RADEON_CS_RING_VCE;
+        if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
+                                 NULL, &value) && value) {
+
+            if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
+                                     "VCE FW version", &value))
+                ws->info.vce_fw_version = value;
+       }
     }
 
     /* Get GEM info. */

diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index 55f60d3f4124b9f15cb1855ed9dcb7aa85bd4050..37affc3896d32f7fa1f93796139ff1f6426c35e8 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -149,6 +149,7 @@ enum ring_type {
     RING_GFX = 0,
     RING_DMA,
     RING_UVD,
+    RING_VCE,
     RING_LAST,
 };
 
@@ -180,6 +181,7 @@ struct radeon_info {
     uint32_t                    drm_patchlevel;
 
     boolean                     has_uvd;
+    uint32_t                    vce_fw_version;
 
     uint32_t                    r300_num_gb_pipes;
     uint32_t                    r300_num_z_pipes;