[xcc, sim] changed instruction format so imm12 subs for rs2

diff --git a/config.h.in b/config.h.in
index bef936b19a3652748b9edda6aa9e63f54f179951..0c3b9aa813446498f560f367e2aae54303234cf3 100644 (file)
--- a/config.h.in
+++ b/config.h.in
@@ -24,5 +24,11 @@
 /* Define if libopcodes exists */
 #undef RISCV_HAVE_LIBOPCODES
 
+/* Define if subproject MCPPBS_SPROJ_NORM is enabled */
+#undef SOFTFLOAT_ENABLED
+
+/* Define if subproject MCPPBS_SPROJ_NORM is enabled */
+#undef SOFTFLOAT_RISCV_ENABLED
+
 /* Define to 1 if you have the ANSI C header files. */
 #undef STDC_HEADERS

diff --git a/riscv/decode.h b/riscv/decode.h
index 627502ee3efa190b2a4ae4c732a11ed7c8c9fb70..f99e9ebe30328ecdd3a0bbfe164bff7390d98dc3 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -78,10 +78,10 @@ const int JUMP_ALIGN_BITS = 1;
 // note: bit fields are in little-endian order
 struct itype_t
 {
-  unsigned imm : IMM_BITS;
+  unsigned imm12 : IMM_BITS;
   unsigned funct : FUNCT_BITS;
-  unsigned rb : GPRID_BITS;
-  unsigned ra : GPRID_BITS;
+  unsigned rs1 : GPRID_BITS;
+  unsigned rdi : GPRID_BITS;
   unsigned opcode : OPCODE_BITS;
 };
 
@@ -93,28 +93,28 @@ struct jtype_t
 
 struct rtype_t
 {
-  unsigned rc : GPRID_BITS;
+  unsigned rdr : GPRID_BITS;
   unsigned functr : FUNCTR_BITS;
   unsigned funct : FUNCT_BITS;
-  unsigned rb : GPRID_BITS;
-  unsigned ra : GPRID_BITS;
+  unsigned rs1 : GPRID_BITS;
+  unsigned rs2 : GPRID_BITS;
   unsigned opcode : OPCODE_BITS;
 };
 
 struct btype_t
 {
   unsigned bigimm : BIGIMM_BITS;
-  unsigned rt : GPRID_BITS;
+  unsigned rdi : GPRID_BITS;
   unsigned opcode : OPCODE_BITS;
 };
 
 struct ftype_t
 {
-  unsigned rc : FPRID_BITS;
-  unsigned rd : FPRID_BITS;
+  unsigned rdr : FPRID_BITS;
+  unsigned rs3 : FPRID_BITS;
   unsigned ffunct : FFUNCT_BITS;
-  unsigned rb : FPRID_BITS;
-  unsigned ra : FPRID_BITS;
+  unsigned rs1 : FPRID_BITS;
+  unsigned rs2 : FPRID_BITS;
   unsigned opcode : OPCODE_BITS;
 };
 
@@ -129,18 +129,20 @@ union insn_t
 };
 
 // helpful macros, etc
-#define RA R[insn.rtype.ra]
-#define RB R[insn.rtype.rb]
-#define RC R[insn.rtype.rc]
-#define FRA FR[insn.ftype.ra]
-#define FRB FR[insn.ftype.rb]
-#define FRC FR[insn.ftype.rc]
-#define FRD FR[insn.ftype.rd]
+#define RS1 R[insn.rtype.rs1]
+#define RS2 R[insn.rtype.rs2]
+#define RDR R[insn.rtype.rdr]
+#define RDI R[insn.itype.rdi]
+#define FRS1 FR[insn.ftype.rs1]
+#define FRS2 FR[insn.ftype.rs2]
+#define FRS3 FR[insn.ftype.rs3]
+#define FRDR FR[insn.ftype.rdr]
+#define FRDI FR[insn.itype.rdi]
 #define BIGIMM insn.btype.bigimm
-#define IMM insn.itype.imm
-#define SIMM ((int32_t)((uint32_t)insn.itype.imm<<(32-IMM_BITS))>>(32-IMM_BITS))
-#define SHAMT (insn.itype.imm & 0x3F)
-#define SHAMTW (insn.itype.imm & 0x1F)
+#define IMM insn.itype.imm12
+#define SIMM ((int32_t)((uint32_t)insn.itype.imm12<<(32-IMM_BITS))>>(32-IMM_BITS))
+#define SHAMT (insn.itype.imm12 & 0x3F)
+#define SHAMTW (insn.itype.imm12 & 0x1F)
 #define TARGET insn.jtype.target
 #define BRANCH_TARGET (npc + (SIMM << BRANCH_ALIGN_BITS))
 #define JUMP_TARGET ((npc & ~((1<<(TARGET_BITS+JUMP_ALIGN_BITS))-1)) + (TARGET << JUMP_ALIGN_BITS))

diff --git a/riscv/execute.h b/riscv/execute.h
index 349fa9e69ca0a9ece1bf8ed0358e2fab7ede1a76..2c500c4d8e6a483f3389528910e12f015576a77e 100644 (file)
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -77,12 +77,12 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/sgninj_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd00004c0)
+        if((insn.bits & 0xfff07fe0) == 0xd00004c0)
         {
           #include "insns/cvt_s_w.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0000440)
+        if((insn.bits & 0xfff07fe0) == 0xd0000440)
         {
           #include "insns/trunc_w_s.h"
           break;
@@ -97,22 +97,22 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/sgninjn_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0000400)
+        if((insn.bits & 0xfff07fe0) == 0xd0000400)
         {
           #include "insns/trunc_l_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd00004e0)
+        if((insn.bits & 0xfff07fe0) == 0xd00004e0)
         {
           #include "insns/cvtu_s_w.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0000420)
+        if((insn.bits & 0xfff07fe0) == 0xd0000420)
         {
           #include "insns/truncu_l_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd00004a0)
+        if((insn.bits & 0xfff07fe0) == 0xd00004a0)
         {
           #include "insns/cvtu_s_l.h"
           break;
@@ -122,7 +122,7 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/sub_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0000080)
+        if((insn.bits & 0xfff07fe0) == 0xd0000080)
         {
           #include "insns/sqrt_s.h"
           break;
@@ -137,7 +137,7 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/sgnmul_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0000480)
+        if((insn.bits & 0xfff07fe0) == 0xd0000480)
         {
           #include "insns/cvt_s_l.h"
           break;
@@ -147,7 +147,7 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/div_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0000660)
+        if((insn.bits & 0xfff07fe0) == 0xd0000660)
         {
           #include "insns/cvt_s_d.h"
           break;
@@ -162,7 +162,7 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/mul_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0000460)
+        if((insn.bits & 0xfff07fe0) == 0xd0000460)
         {
           #include "insns/truncu_w_s.h"
           break;
@@ -186,17 +186,17 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/c_eq_d.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd00064a0)
+        if((insn.bits & 0xfff07fe0) == 0xd00064a0)
         {
           #include "insns/cvtu_d_l.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0006440)
+        if((insn.bits & 0xfff07fe0) == 0xd0006440)
         {
           #include "insns/trunc_w_d.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd00064e0)
+        if((insn.bits & 0xfff07fe0) == 0xd00064e0)
         {
           #include "insns/cvtu_d_w.h"
           break;
@@ -221,17 +221,17 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/sgninjn_d.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0006600)
+        if((insn.bits & 0xfff07fe0) == 0xd0006600)
         {
           #include "insns/cvt_d_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0006400)
+        if((insn.bits & 0xfff07fe0) == 0xd0006400)
         {
           #include "insns/trunc_l_d.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0006420)
+        if((insn.bits & 0xfff07fe0) == 0xd0006420)
         {
           #include "insns/truncu_l_d.h"
           break;
@@ -241,22 +241,22 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/sub_d.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0006080)
+        if((insn.bits & 0xfff07fe0) == 0xd0006080)
         {
           #include "insns/sqrt_d.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd00064c0)
+        if((insn.bits & 0xfff07fe0) == 0xd00064c0)
         {
           #include "insns/cvt_d_w.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0006480)
+        if((insn.bits & 0xfff07fe0) == 0xd0006480)
         {
           #include "insns/cvt_d_l.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0006460)
+        if((insn.bits & 0xfff07fe0) == 0xd0006460)
         {
           #include "insns/truncu_w_d.h"
           break;
@@ -317,12 +317,12 @@ switch((insn.bits >> 0x19) & 0x7f)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe0fffe0) == 0xd4000000)
+        if((insn.bits & 0xfff07fe0) == 0xd4000000)
         {
           #include "insns/mff_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd4000800)
+        if((insn.bits & 0xfff07fe0) == 0xd4000800)
         {
           #include "insns/mtf_s.h"
           break;
@@ -331,12 +331,12 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x6:
       {
-        if((insn.bits & 0xfe0fffe0) == 0xd4006000)
+        if((insn.bits & 0xfff07fe0) == 0xd4006000)
         {
           #include "insns/mff_d.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd4006400)
+        if((insn.bits & 0xfff07fe0) == 0xd4006400)
         {
           #include "insns/mffh_d.h"
           break;
@@ -346,7 +346,7 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/mtflh_d.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd4006800)
+        if((insn.bits & 0xfff07fe0) == 0xd4006800)
         {
           #include "insns/mtf_d.h"
           break;
@@ -947,17 +947,17 @@ switch((insn.bits >> 0x19) & 0x7f)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe0fffe0) == 0xf6000000)
+        if((insn.bits & 0xfff07fe0) == 0xf6000000)
         {
           #include "insns/jalr_c.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xf6000040)
+        if((insn.bits & 0xfff07fe0) == 0xf6000040)
         {
           #include "insns/jalr_j.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xf6000020)
+        if((insn.bits & 0xfff07fe0) == 0xf6000020)
         {
           #include "insns/jalr_r.h"
           break;
@@ -975,7 +975,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x2:
       {
-        if((insn.bits & 0xfff07fe0) == 0xf6002000)
+        if((insn.bits & 0xfe0fffe0) == 0xf6002000)
         {
           #include "insns/mfcr.h"
           break;
@@ -1058,7 +1058,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x4:
       {
-        if((insn.bits & 0xfff07fe0) == 0xfc004000)
+        if((insn.bits & 0xfe0fffe0) == 0xfc004000)
         {
           #include "insns/mfpcr.h"
           break;

diff --git a/riscv/insns/add.h b/riscv/insns/add.h
index 746cd80678ca0b19b35cd2bb48c69feb2d1a65d9..f7dede9f3de53530cf896ff7a103a97d513ad16e 100644 (file)
--- a/riscv/insns/add.h
+++ b/riscv/insns/add.h
@@ -1,2 +1,2 @@
 require64;
-RC = RA + RB;
+RDR = RS1 + RS2;

diff --git a/riscv/insns/add_d.h b/riscv/insns/add_d.h
index 964aa20885310f341aaf228611a5cbfe68d6fe1f..eae2c6ea2fc2ba82d602b7935388cb5ba3d43e79 100644 (file)
--- a/riscv/insns/add_d.h
+++ b/riscv/insns/add_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_add(FRA, FRB);
+FRDR = f64_add(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/add_s.h b/riscv/insns/add_s.h
index d4d0cd6037f37e70ce910c7a584df1198a88b562..7c9dc5073b811e32aecf012680a2ae94943d25ea 100644 (file)
--- a/riscv/insns/add_s.h
+++ b/riscv/insns/add_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_add(FRA, FRB);
+FRDR = f32_add(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/addi.h b/riscv/insns/addi.h
index b6b208dc7af74fec1be93eba21b026555a0b2cf1..e813eaec63c261b756638a92eb0510e7aa2a7e4a 100644 (file)
--- a/riscv/insns/addi.h
+++ b/riscv/insns/addi.h
@@ -1,2 +1,2 @@
 require64;
-RA = SIMM + RB;
+RDI = SIMM + RS1;

diff --git a/riscv/insns/addiw.h b/riscv/insns/addiw.h
index 6935ccadea8c0c76ce4f2cdff22232ef7e1631ae..6dfe5b1fab5643d3c8d3648e6234d3b2a03c9e00 100644 (file)
--- a/riscv/insns/addiw.h
+++ b/riscv/insns/addiw.h
@@ -1 +1 @@
-RA = sext32(SIMM + RB);
+RDI = sext32(SIMM + RS1);

diff --git a/riscv/insns/addw.h b/riscv/insns/addw.h
index bfbc48568ddbf707f67c57f718022f31b370199c..d95c95f8b449464cd78bfa94488c0f1e35b0f85b 100644 (file)
--- a/riscv/insns/addw.h
+++ b/riscv/insns/addw.h
@@ -1,2 +1,2 @@
-RC = sext32(RA + RB);
+RDR = sext32(RS1 + RS2);
 

diff --git a/riscv/insns/amo_add.h b/riscv/insns/amo_add.h
index 0ea67829680334c0dbfb91adae7ef8ab1a8108f6..18f6f4e047a95557c2171bec5719a5beb68dff00 100644 (file)
--- a/riscv/insns/amo_add.h
+++ b/riscv/insns/amo_add.h
@@ -1,4 +1,4 @@
 require64;
-reg_t v = mmu.load_uint64(RB);
-mmu.store_uint64(RB, RA + v);
-RC = v;
+reg_t v = mmu.load_uint64(RS1);
+mmu.store_uint64(RS1, RS2 + v);
+RDR = v;

diff --git a/riscv/insns/amo_and.h b/riscv/insns/amo_and.h
index c86e5373489f4be4f7e1701716da74f01d214fce..dd187df142a5d5a25bc2de84d2be155cfcf6ccb0 100644 (file)
--- a/riscv/insns/amo_and.h
+++ b/riscv/insns/amo_and.h
@@ -1,4 +1,4 @@
 require64;
-reg_t v = mmu.load_uint64(RB);
-mmu.store_uint64(RB, RA & v);
-RC = v;
+reg_t v = mmu.load_uint64(RS1);
+mmu.store_uint64(RS1, RS2 & v);
+RDR = v;

diff --git a/riscv/insns/amo_max.h b/riscv/insns/amo_max.h
index 6e3eeb66db9fe6c40e76185c281216d5757e6069..296b86a620ffcb4383deaf9900100ae7159673ce 100644 (file)
--- a/riscv/insns/amo_max.h
+++ b/riscv/insns/amo_max.h
@@ -1,4 +1,4 @@
 require64;
-sreg_t v = mmu.load_int64(RB);
-mmu.store_uint64(RB, std::max(sreg_t(RA),v));
-RC = v;
+sreg_t v = mmu.load_int64(RS1);
+mmu.store_uint64(RS1, std::max(sreg_t(RS2),v));
+RDR = v;

diff --git a/riscv/insns/amo_maxu.h b/riscv/insns/amo_maxu.h
index 471a1193c487dc4307f83c7df05ddb3c01cc16e7..533dde3ace98cb3e659ce22638d31d541de2d9b3 100644 (file)
--- a/riscv/insns/amo_maxu.h
+++ b/riscv/insns/amo_maxu.h
@@ -1,4 +1,4 @@
 require64;
-reg_t v = mmu.load_uint64(RB);
-mmu.store_uint64(RB, std::max(RA,v));
-RC = v;
+reg_t v = mmu.load_uint64(RS1);
+mmu.store_uint64(RS1, std::max(RS2,v));
+RDR = v;

diff --git a/riscv/insns/amo_min.h b/riscv/insns/amo_min.h
index 823550479ee91b3680cf412ab5938612ecbed8e1..7244e87d4ee8a84f66344d99cc30f742d6113014 100644 (file)
--- a/riscv/insns/amo_min.h
+++ b/riscv/insns/amo_min.h
@@ -1,4 +1,4 @@
 require64;
-sreg_t v = mmu.load_int64(RB);
-mmu.store_uint64(RB, std::min(sreg_t(RA),v));
-RC = v;
+sreg_t v = mmu.load_int64(RS1);
+mmu.store_uint64(RS1, std::min(sreg_t(RS2),v));
+RDR = v;

diff --git a/riscv/insns/amo_minu.h b/riscv/insns/amo_minu.h
index 0b617a10fd72bb9a956e3c7533756102d647bfba..3e365ab4a87153d92dbcbc2a8ca207ed2390e664 100644 (file)
--- a/riscv/insns/amo_minu.h
+++ b/riscv/insns/amo_minu.h
@@ -1,4 +1,4 @@
 require64;
-reg_t v = mmu.load_uint64(RB);
-mmu.store_uint64(RB, std::min(RA,v));
-RC = v;
+reg_t v = mmu.load_uint64(RS1);
+mmu.store_uint64(RS1, std::min(RS2,v));
+RDR = v;

diff --git a/riscv/insns/amo_or.h b/riscv/insns/amo_or.h
index 790a98caa49c9128c1d2e21e353b880cc20683ed..e7d81a8cd0d43ae3398ae1d4c6a0194a7c7c488e 100644 (file)
--- a/riscv/insns/amo_or.h
+++ b/riscv/insns/amo_or.h
@@ -1,4 +1,4 @@
 require64;
-reg_t v = mmu.load_uint64(RB);
-mmu.store_uint64(RB, RA | v);
-RC = v;
+reg_t v = mmu.load_uint64(RS1);
+mmu.store_uint64(RS1, RS2 | v);
+RDR = v;

diff --git a/riscv/insns/amo_swap.h b/riscv/insns/amo_swap.h
index 1995f834832df06c5053a56226bbce9d32d63ff7..0ee4ea21f36146920e1b4662ee013a06175cf5e8 100644 (file)
--- a/riscv/insns/amo_swap.h
+++ b/riscv/insns/amo_swap.h
@@ -1,4 +1,4 @@
 require64;
-reg_t v = mmu.load_uint64(RB);
-mmu.store_uint64(RB, RA);
-RC = v;
+reg_t v = mmu.load_uint64(RS1);
+mmu.store_uint64(RS1, RS2);
+RDR = v;

diff --git a/riscv/insns/amow_add.h b/riscv/insns/amow_add.h
index fbf475d58e8e9dac60b11d9cfd1e3be0be66dae9..a55ddf9a3ad7e32678d00fc0b358710b61aea642 100644 (file)
--- a/riscv/insns/amow_add.h
+++ b/riscv/insns/amow_add.h
@@ -1,3 +1,3 @@
-reg_t v = mmu.load_int32(RB);
-mmu.store_uint32(RB, RA + v);
-RC = v;
+reg_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, RS2 + v);
+RDR = v;

diff --git a/riscv/insns/amow_and.h b/riscv/insns/amow_and.h
index 1166e8673668dc34d8c099358bd11800bb5f724c..f1670bde03a2ce28549e665b5c63b2e23434793d 100644 (file)
--- a/riscv/insns/amow_and.h
+++ b/riscv/insns/amow_and.h
@@ -1,3 +1,3 @@
-reg_t v = mmu.load_int32(RB);
-mmu.store_uint32(RB, RA & v);
-RC = v;
+reg_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, RS2 & v);
+RDR = v;

diff --git a/riscv/insns/amow_max.h b/riscv/insns/amow_max.h
index c5318e789e54db8cd0b29b8211a549186572c813..c4854d1662139dd5338919a49c6bc85dd37033e2 100644 (file)
--- a/riscv/insns/amow_max.h
+++ b/riscv/insns/amow_max.h
@@ -1,3 +1,3 @@
-int32_t v = mmu.load_int32(RB);
-mmu.store_uint32(RB, std::max(int32_t(RA),v));
-RC = v;
+int32_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, std::max(int32_t(RS2),v));
+RDR = v;

diff --git a/riscv/insns/amow_maxu.h b/riscv/insns/amow_maxu.h
index 9f5bf2332c5aeaf6ef01cd0d0015dd6c68593073..37219a8d50ebcd3f97c2487891f172ecd8d2eeba 100644 (file)
--- a/riscv/insns/amow_maxu.h
+++ b/riscv/insns/amow_maxu.h
@@ -1,3 +1,3 @@
-uint32_t v = mmu.load_int32(RB);
-mmu.store_uint32(RB, std::max(uint32_t(RA),v));
-RC = v;
+uint32_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, std::max(uint32_t(RS2),v));
+RDR = v;

diff --git a/riscv/insns/amow_min.h b/riscv/insns/amow_min.h
index a5abc488683db1fd84d51a717786b31f6d9e56a8..ac1362393a8e32ad86a3ecec43b639cd9955049a 100644 (file)
--- a/riscv/insns/amow_min.h
+++ b/riscv/insns/amow_min.h
@@ -1,3 +1,3 @@
-int32_t v = mmu.load_int32(RB);
-mmu.store_uint32(RB, std::min(int32_t(RA),v));
-RC = v;
+int32_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, std::min(int32_t(RS2),v));
+RDR = v;

diff --git a/riscv/insns/amow_minu.h b/riscv/insns/amow_minu.h
index fe55d23f9333d9c6513101bf1a7e022df2435b67..de3ee566f0bd5a76528d0d6da0323ee59b2453b7 100644 (file)
--- a/riscv/insns/amow_minu.h
+++ b/riscv/insns/amow_minu.h
@@ -1,3 +1,3 @@
-uint32_t v = mmu.load_int32(RB);
-mmu.store_uint32(RB, std::min(uint32_t(RA),v));
-RC = v;
+uint32_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, std::min(uint32_t(RS2),v));
+RDR = v;

diff --git a/riscv/insns/amow_or.h b/riscv/insns/amow_or.h
index 09d105fa97321301f48728193a356d6c0dbb7dc0..e56966574381e4d9fb96fd19ae82440caee3a023 100644 (file)
--- a/riscv/insns/amow_or.h
+++ b/riscv/insns/amow_or.h
@@ -1,3 +1,3 @@
-reg_t v = mmu.load_int32(RB);
-mmu.store_uint32(RB, RA | v);
-RC = v;
+reg_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, RS2 | v);
+RDR = v;

diff --git a/riscv/insns/amow_swap.h b/riscv/insns/amow_swap.h
index 6aec206a1ed30812ed34abccc92d53693d44b5c7..c8b108a114e1decdbd235ec4b6234d1fdbab8cd3 100644 (file)
--- a/riscv/insns/amow_swap.h
+++ b/riscv/insns/amow_swap.h
@@ -1,3 +1,3 @@
-reg_t v = mmu.load_int32(RB);
-mmu.store_uint32(RB, RA);
-RC = v;
+reg_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, RS2);
+RDR = v;

diff --git a/riscv/insns/and.h b/riscv/insns/and.h
index 305e5417c384bde680a9307df209a2c1ef907438..a63e83f5feb35ea8755d7e80489b186366c464a5 100644 (file)
--- a/riscv/insns/and.h
+++ b/riscv/insns/and.h
@@ -1 +1 @@
-RC = RA & RB;
+RDR = RS1 & RS2;

diff --git a/riscv/insns/andi.h b/riscv/insns/andi.h
index 86a045c2ff0b54da48954d0a415f41b17237fb76..ada6657d65e05b62f7576c1f3ccd2be012246ef9 100644 (file)
--- a/riscv/insns/andi.h
+++ b/riscv/insns/andi.h
@@ -1 +1 @@
-RA = IMM & RB;
+RDI = IMM & RS1;

diff --git a/riscv/insns/beq.h b/riscv/insns/beq.h
index 320c33fa431f5bb180c2f1915afce77b5461d14b..072b7b8425965837758f63413b060ba821a40d13 100644 (file)
--- a/riscv/insns/beq.h
+++ b/riscv/insns/beq.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RA) == cmp_trunc(RB))
+if(cmp_trunc(RS1) == cmp_trunc(RS2))
   npc = BRANCH_TARGET;

diff --git a/riscv/insns/bge.h b/riscv/insns/bge.h
index 66db6b233bb5dee2692d856302c6f963f9692133..45dcc2ee12239aceecb0450724b35cc891e8d7a5 100644 (file)
--- a/riscv/insns/bge.h
+++ b/riscv/insns/bge.h
@@ -1,2 +1,2 @@
-if(sreg_t(cmp_trunc(RA)) >= sreg_t(cmp_trunc(RB)))
+if(sreg_t(cmp_trunc(RS1)) >= sreg_t(cmp_trunc(RS2)))
   npc = BRANCH_TARGET;

diff --git a/riscv/insns/bgeu.h b/riscv/insns/bgeu.h
index 52d66615e2fbad5803b62df861a59c6bc44decb5..2ba3fa81e438f7141403ca22e8b39011ead7cb2a 100644 (file)
--- a/riscv/insns/bgeu.h
+++ b/riscv/insns/bgeu.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RA) >= cmp_trunc(RB))
+if(cmp_trunc(RS1) >= cmp_trunc(RS2))
   npc = BRANCH_TARGET;

diff --git a/riscv/insns/blt.h b/riscv/insns/blt.h
index 8d95127c8cec52fa00004e90e09cf64970d0b1fa..3ffd20e780cbe51317abdf432f22aae95c19fcca 100644 (file)
--- a/riscv/insns/blt.h
+++ b/riscv/insns/blt.h
@@ -1,2 +1,2 @@
-if(sreg_t(cmp_trunc(RA)) < sreg_t(cmp_trunc(RB)))
+if(sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2)))
   npc = BRANCH_TARGET;

diff --git a/riscv/insns/bltu.h b/riscv/insns/bltu.h
index 27deefec7953c21915e7173db1e29bf278a7ffda..186dcbef5c4669d405db435b9df1d6f313274be6 100644 (file)
--- a/riscv/insns/bltu.h
+++ b/riscv/insns/bltu.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RA) < cmp_trunc(RB))
+if(cmp_trunc(RS1) < cmp_trunc(RS2))
   npc = BRANCH_TARGET;

diff --git a/riscv/insns/bne.h b/riscv/insns/bne.h
index aee98f6829362fc7ee4254b0c7cac4e56761c680..39b0b19ebe30f57ee18373f1aacbe4953c4fc774 100644 (file)
--- a/riscv/insns/bne.h
+++ b/riscv/insns/bne.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RA) != cmp_trunc(RB))
+if(cmp_trunc(RS1) != cmp_trunc(RS2))
   npc = BRANCH_TARGET;

diff --git a/riscv/insns/c_eq_d.h b/riscv/insns/c_eq_d.h
index cc7b77a92c042a8d08422d813c55bdb6029f34f6..127e57e29360d3a781401e42eb16ea997fc14922 100644 (file)
--- a/riscv/insns/c_eq_d.h
+++ b/riscv/insns/c_eq_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RC = f64_eq(FRA, FRB);
+RDR = f64_eq(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/c_eq_s.h b/riscv/insns/c_eq_s.h
index 5500c4cdadc09d4b0b1c0f580b8563b4636140b1..0a2ccd916ff57672097565f62d3a54ed8a1e316c 100644 (file)
--- a/riscv/insns/c_eq_s.h
+++ b/riscv/insns/c_eq_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RC = f32_eq(FRA, FRB);
+RDR = f32_eq(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/c_le_d.h b/riscv/insns/c_le_d.h
index 2fe6f3283907fb1f60d16f9baa9f2b65afd89d99..23f97035d25140dbd2c3b93848a36755ae917e3c 100644 (file)
--- a/riscv/insns/c_le_d.h
+++ b/riscv/insns/c_le_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RC = f64_le(FRA, FRB);
+RDR = f64_le(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/c_le_s.h b/riscv/insns/c_le_s.h
index e6e26b3d944d904db6ca6fe258df626a323ec941..7350a9e066111509d7d050fffde08754bd9962ab 100644 (file)
--- a/riscv/insns/c_le_s.h
+++ b/riscv/insns/c_le_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RC = f32_le(FRA, FRB);
+RDR = f32_le(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/c_lt_d.h b/riscv/insns/c_lt_d.h
index 3f3756d674569579c0366d5bd02939f1851c6768..77e7eec492b1647b2edfa57c4d7647220a50b082 100644 (file)
--- a/riscv/insns/c_lt_d.h
+++ b/riscv/insns/c_lt_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RC = f64_lt(FRA, FRB);
+RDR = f64_lt(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/c_lt_s.h b/riscv/insns/c_lt_s.h
index aef73340d7d88530b11f3173c674c939af7a4090..cdb43725474a8b56b3792917a77c7d0d9daf1e18 100644 (file)
--- a/riscv/insns/c_lt_s.h
+++ b/riscv/insns/c_lt_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RC = f32_lt(FRA, FRB);
+RDR = f32_lt(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_d_l.h b/riscv/insns/cvt_d_l.h
index 808d20cc81a4b09d2a43b045888584c010865603..5faac2a4691fceba6698cfef188a2f3a691ca4a5 100644 (file)
--- a/riscv/insns/cvt_d_l.h
+++ b/riscv/insns/cvt_d_l.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = i64_to_f64(FRA);
+FRDR = i64_to_f64(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_d_s.h b/riscv/insns/cvt_d_s.h
index 69206e1a80456c515164a9a649b67197568a1d21..7a26f7092c09c9cfed257a77b979f093d64b4a0e 100644 (file)
--- a/riscv/insns/cvt_d_s.h
+++ b/riscv/insns/cvt_d_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_to_f64(FRA);
+FRDR = f32_to_f64(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_d_w.h b/riscv/insns/cvt_d_w.h
index e1c36f22822b1a0bfc3278ecb09c36b65eb8b6c2..67bc7986abe267a407f30ed591d70f9dc80b1427 100644 (file)
--- a/riscv/insns/cvt_d_w.h
+++ b/riscv/insns/cvt_d_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = i32_to_f64(FRA);
+FRDR = i32_to_f64(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_s_d.h b/riscv/insns/cvt_s_d.h
index 0ee755e8e6ecb3a7ac559e7d3cafe0fabf14796f..56d6fe36128fc1112c216c0a57051811685157a6 100644 (file)
--- a/riscv/insns/cvt_s_d.h
+++ b/riscv/insns/cvt_s_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_to_f32(FRA);
+FRDR = f64_to_f32(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_s_l.h b/riscv/insns/cvt_s_l.h
index 66e45664b950100121de02e45dc731b3d7b9f544..f5332f9cf716e87df32ab414eede927f930ede22 100644 (file)
--- a/riscv/insns/cvt_s_l.h
+++ b/riscv/insns/cvt_s_l.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = i64_to_f32(FRA);
+FRDR = i64_to_f32(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_s_w.h b/riscv/insns/cvt_s_w.h
index 5bbe61f172ce06c378e6454336fa1ce385a17037..9db538636f045477a43354984739cb6a3a7802d4 100644 (file)
--- a/riscv/insns/cvt_s_w.h
+++ b/riscv/insns/cvt_s_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = i32_to_f32(FRA);
+FRDR = i32_to_f32(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_d_l.h b/riscv/insns/cvtu_d_l.h
index 808d20cc81a4b09d2a43b045888584c010865603..5faac2a4691fceba6698cfef188a2f3a691ca4a5 100644 (file)
--- a/riscv/insns/cvtu_d_l.h
+++ b/riscv/insns/cvtu_d_l.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = i64_to_f64(FRA);
+FRDR = i64_to_f64(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_d_w.h b/riscv/insns/cvtu_d_w.h
index 1a61ad6417fc0b5f6671301362877e800c91b7bb..1b35e06d572a65bef79380a971261398cc03d948 100644 (file)
--- a/riscv/insns/cvtu_d_w.h
+++ b/riscv/insns/cvtu_d_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = ui32_to_f64(FRA);
+FRDR = ui32_to_f64(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_s_l.h b/riscv/insns/cvtu_s_l.h
index 66e45664b950100121de02e45dc731b3d7b9f544..f5332f9cf716e87df32ab414eede927f930ede22 100644 (file)
--- a/riscv/insns/cvtu_s_l.h
+++ b/riscv/insns/cvtu_s_l.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = i64_to_f32(FRA);
+FRDR = i64_to_f32(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_s_w.h b/riscv/insns/cvtu_s_w.h
index 8eaeca3d8f2df691203132f0c32d48f5da3cb3c0..252e0cc010fba887dc0aff86ef306fd33c9a6055 100644 (file)
--- a/riscv/insns/cvtu_s_w.h
+++ b/riscv/insns/cvtu_s_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = ui32_to_f32(FRA);
+FRDR = ui32_to_f32(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/di.h b/riscv/insns/di.h
index f555c2c479260309cf016edc41186d02e4d13b51..0f3adf9c8adce2660a8520e1bc099a7db863e6e9 100644 (file)
--- a/riscv/insns/di.h
+++ b/riscv/insns/di.h
@@ -1,4 +1,4 @@
 require_supervisor;
 uint32_t temp = sr;
 set_sr(sr & ~SR_ET);
-RC = temp;
+RDR = temp;

diff --git a/riscv/insns/div.h b/riscv/insns/div.h
index f0c2d2be5742a9ec67ee1384adc0383bf203e6a3..2d6edfca0e144956e88542384aea55dba8fd29d3 100644 (file)
--- a/riscv/insns/div.h
+++ b/riscv/insns/div.h
@@ -1,2 +1,2 @@
 require64;
-RC = sreg_t(RA) / sreg_t(RB);
+RDR = sreg_t(RS1) / sreg_t(RS2);

diff --git a/riscv/insns/div_d.h b/riscv/insns/div_d.h
index 884effcbcef48c10bbdda0b17ad10041ef3a9b31..9902da6e4d2f2b84ff5492ba56d6c06a290ff4e7 100644 (file)
--- a/riscv/insns/div_d.h
+++ b/riscv/insns/div_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_div(FRA, FRB);
+FRDR = f64_div(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/div_s.h b/riscv/insns/div_s.h
index b2d086910e1d4171ccd405b52465ee8c5583a0af..99e343c87dad6c758e165a5b8b7135e5e3f06d37 100644 (file)
--- a/riscv/insns/div_s.h
+++ b/riscv/insns/div_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_div(FRA, FRB);
+FRDR = f32_div(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h
index a4e3f4f27355d4ad4434a3a29114af762bc04618..35eee14eae11774afdcbb4d27c49d2c51b6994e0 100644 (file)
--- a/riscv/insns/divu.h
+++ b/riscv/insns/divu.h
@@ -1,2 +1,2 @@
 require64;
-RC = RA / RB;
+RDR = RS1 / RS2;

diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h
index 68f96a5d0768bf48451c93ee5ef99c2e78f27701..f52fe5a536834ef372ef8c7e8bb1526ca6678629 100644 (file)
--- a/riscv/insns/divuw.h
+++ b/riscv/insns/divuw.h
@@ -1,2 +1,2 @@
-RC = sext32(uint32_t(RA)/uint32_t(RB));
+RDR = sext32(uint32_t(RS1)/uint32_t(RS2));
 

diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h
index e595c85af0c8af441552ac7fa3a7c9d84d4721a8..938478c0c9391da50e27e84486804b1839a20c12 100644 (file)
--- a/riscv/insns/divw.h
+++ b/riscv/insns/divw.h
@@ -1,2 +1,2 @@
-RC = sext32(int32_t(RA)/int32_t(RB));
+RDR = sext32(int32_t(RS1)/int32_t(RS2));
 

diff --git a/riscv/insns/ei.h b/riscv/insns/ei.h
index 75d79fecd66bd208c3ca9af30771af0cd6347c4e..f3e52075cc5c4f5550f6b884e7a07299ce978f9a 100644 (file)
--- a/riscv/insns/ei.h
+++ b/riscv/insns/ei.h
@@ -1,4 +1,4 @@
 require_supervisor;
 uint32_t temp = sr;
 set_sr(sr | SR_ET);
-RC = temp;
+RDR = temp;

diff --git a/riscv/insns/jalr_c.h b/riscv/insns/jalr_c.h
index 18b2508ec898357e17538366c4bd7baced9fc6d0..dade874cb807d6de6d11c4158d8de1d12d1da4af 100644 (file)
--- a/riscv/insns/jalr_c.h
+++ b/riscv/insns/jalr_c.h
@@ -1,3 +1,3 @@
 uint32_t temp = npc;
-npc = RA;
-RC = temp;
+npc = RS1;
+RDR = temp;

diff --git a/riscv/insns/l_d.h b/riscv/insns/l_d.h
index 760cf98e44cf619473beb307226503d4ed80384f..8a06e3d0bce4324b7fb6e127c18fea7c1cb0faf1 100644 (file)
--- a/riscv/insns/l_d.h
+++ b/riscv/insns/l_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRA = mmu.load_int64(RB+SIMM);
+FRDI = mmu.load_int64(RS1+SIMM);

diff --git a/riscv/insns/l_s.h b/riscv/insns/l_s.h
index 1637fed438a3108ef6cdfe0ab60f7b9e7867ac55..1e9bbf7ee17540725ccbc9e6ea623978d28c95bc 100644 (file)
--- a/riscv/insns/l_s.h
+++ b/riscv/insns/l_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRA = mmu.load_int32(RB+SIMM);
+FRDI = mmu.load_int32(RS1+SIMM);

diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h
index ac8bf6486307d693e5d7d156a52cbeabdb29a2c9..47e03d74c2403708006d1a020252d03d8e90f058 100644 (file)
--- a/riscv/insns/lb.h
+++ b/riscv/insns/lb.h
@@ -1 +1 @@
-RA = mmu.load_int8(RB+SIMM);
+RDI = mmu.load_int8(RS1+SIMM);

diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h
index 522eb8f98c16c92bffe61a6e314941b589aeb587..e378871edc14052d4b118a4663f6c56d0ccc35f9 100644 (file)
--- a/riscv/insns/lbu.h
+++ b/riscv/insns/lbu.h
@@ -1 +1 @@
-RA = mmu.load_uint8(RB+SIMM);
+RDI = mmu.load_uint8(RS1+SIMM);

diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h
index 241af6a1acb19e48bd93bad03d1b3ab5ef847be5..9959d2698d828c46726dd892e8ccec6e32cd3357 100644 (file)
--- a/riscv/insns/ld.h
+++ b/riscv/insns/ld.h
@@ -1,2 +1,2 @@
 require64;
-RA = mmu.load_int64(RB+SIMM);
+RDI = mmu.load_int64(RS1+SIMM);

diff --git a/riscv/insns/lh.h b/riscv/insns/lh.h
index e46ee1472edc0cd53e4ea2b66ac823a3d70e4da0..830b67339dba0543e1e85bdd68811c80c73a0ea4 100644 (file)
--- a/riscv/insns/lh.h
+++ b/riscv/insns/lh.h
@@ -1 +1 @@
-RA = mmu.load_int16(RB+SIMM);
+RDI = mmu.load_int16(RS1+SIMM);

diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h
index 1f22423b8e330ede3a84e0bc82d8b4912f137d1c..961c42702145c58a62ab1df99164ccc14ce9f9a4 100644 (file)
--- a/riscv/insns/lhu.h
+++ b/riscv/insns/lhu.h
@@ -1 +1 @@
-RA = mmu.load_uint16(RB+SIMM);
+RDI = mmu.load_uint16(RS1+SIMM);

diff --git a/riscv/insns/lui.h b/riscv/insns/lui.h
index 0eb14bc4010af13a49d0226cc587bf675a233d0b..20a0af841fed2321730dda69b0e2ab98b4fca050 100644 (file)
--- a/riscv/insns/lui.h
+++ b/riscv/insns/lui.h
@@ -1 +1 @@
-RA = sext32(BIGIMM << IMM_BITS);
+RDI = sext32(BIGIMM << IMM_BITS);

diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h
index e1f56fefa00308e3b479b883e80fa447f022f55f..6bd26463adba7445d6b2cc1569bbc4b9f4520edd 100644 (file)
--- a/riscv/insns/lw.h
+++ b/riscv/insns/lw.h
@@ -1 +1 @@
-RA = mmu.load_int32(RB+SIMM);
+RDI = mmu.load_int32(RS1+SIMM);

diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h
index 311292d8022ad8d29d80d2d902a216fbc1384e66..3c597af1da84af4b0bd5ca39f46c25795392d211 100644 (file)
--- a/riscv/insns/lwu.h
+++ b/riscv/insns/lwu.h
@@ -1 +1 @@
-RA = mmu.load_uint32(RB+SIMM);
+RDI = mmu.load_uint32(RS1+SIMM);

diff --git a/riscv/insns/madd_d.h b/riscv/insns/madd_d.h
index e1b92060525a748078af6e4c9d388204e914406e..c9d63186d99a06c8619476e30694f4a91ff77640 100644 (file)
--- a/riscv/insns/madd_d.h
+++ b/riscv/insns/madd_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_mulAdd(FRA, FRB, FRD);
+FRDR = f64_mulAdd(FRS1, FRS2, FRS3);
 set_fp_exceptions;

diff --git a/riscv/insns/madd_s.h b/riscv/insns/madd_s.h
index 3433adfe0d387de17a049ba2f5926153a6c8d9de..49f4861007238de198b36344f49f97c5b1cb9780 100644 (file)
--- a/riscv/insns/madd_s.h
+++ b/riscv/insns/madd_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_mulAdd(FRA, FRB, FRD);
+FRDR = f32_mulAdd(FRS1, FRS2, FRS3);
 set_fp_exceptions;

diff --git a/riscv/insns/mfcr.h b/riscv/insns/mfcr.h
index 088480cba7e4f18c96b5998a98284084df67cf25..1d6b4d153857d665c3a74983a5baae9dab6d5ea1 100644 (file)
--- a/riscv/insns/mfcr.h
+++ b/riscv/insns/mfcr.h
@@ -1,6 +1,6 @@
 reg_t val;
 
-switch(insn.rtype.rb)
+switch(insn.rtype.rs2)
 {
   case 0:
     val = fsr;
@@ -18,4 +18,4 @@ switch(insn.rtype.rb)
     val = -1;
 }
 
-RC = gprlen == 64 ? val : sext32(val);
+RDR = gprlen == 64 ? val : sext32(val);

diff --git a/riscv/insns/mff_d.h b/riscv/insns/mff_d.h
index e2e8415ce81e2a5a47cf5b4a214a88ec8d63466b..1f0182eb26365aea4170bfc152a16acbc52abd98 100644 (file)
--- a/riscv/insns/mff_d.h
+++ b/riscv/insns/mff_d.h
@@ -1,3 +1,3 @@
 require64;
 require_fp;
-RC = FRA;
+RDR = FRS1;

diff --git a/riscv/insns/mff_s.h b/riscv/insns/mff_s.h
index f92c935266ad9f55bb92b2003ea0800635242750..a258aa088ab3e58dacbdbab6fc3ac8df289fe6a7 100644 (file)
--- a/riscv/insns/mff_s.h
+++ b/riscv/insns/mff_s.h
@@ -1,2 +1,2 @@
 require_fp;
-RC = sext32(FRA);
+RDR = sext32(FRS1);

diff --git a/riscv/insns/mffh_d.h b/riscv/insns/mffh_d.h
index b466f60c86a8f9a886ab11a58aad8ab65bcd8081..45dd36ac1ca75b212b252c401164484f01a5c949 100644 (file)
--- a/riscv/insns/mffh_d.h
+++ b/riscv/insns/mffh_d.h
@@ -1,2 +1,2 @@
 require_fp;
-RC = sext32(FRA >> 32);
+RDR = sext32(FRS1 >> 32);

diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
index 3416db1f870674f6c4dc2a414e9fe6fa783a7c97..00609576689ae4b230210f5b411cb846ec172284 100644 (file)
--- a/riscv/insns/mfpcr.h
+++ b/riscv/insns/mfpcr.h
@@ -2,7 +2,7 @@ require_supervisor;
 
 reg_t val;
 
-switch(insn.rtype.rb)
+switch(insn.rtype.rs2)
 {
   case 0:
     val = sr;
@@ -42,4 +42,4 @@ switch(insn.rtype.rb)
     val = -1;
 }
 
-RC = gprlen == 64 ? val : sext32(val);
+RDR = gprlen == 64 ? val : sext32(val);

diff --git a/riscv/insns/msub_d.h b/riscv/insns/msub_d.h
index 747cacc4f1c0cce1c48f23fb63e576d6d2ee9ad1..939baca41f7cdfbe272f88ccc673b5602858bd79 100644 (file)
--- a/riscv/insns/msub_d.h
+++ b/riscv/insns/msub_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_mulAdd(FRA, FRB, FRD ^ (uint64_t)INT64_MIN);
+FRDR = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
 set_fp_exceptions;

diff --git a/riscv/insns/msub_s.h b/riscv/insns/msub_s.h
index 60f10a4d82427bc79b782eac5cd5e753714dc2c7..b80895102b30e3803a30fa21d790c20f28ca658a 100644 (file)
--- a/riscv/insns/msub_s.h
+++ b/riscv/insns/msub_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_mulAdd(FRA, FRB, FRD ^ (uint32_t)INT32_MIN);
+FRDR = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
 set_fp_exceptions;

diff --git a/riscv/insns/mtcr.h b/riscv/insns/mtcr.h
index d7b2b17eb2b1c9d6c689528ad0357da562f46bb9..ba55899743adcbfef52d38ce1b56a06555638361 100644 (file)
--- a/riscv/insns/mtcr.h
+++ b/riscv/insns/mtcr.h
@@ -1,10 +1,10 @@
-switch(insn.rtype.rb)
+switch(insn.rtype.rs2)
 {
   case 0:
-    set_fsr(RA);
+    set_fsr(RS1);
     break;
 
   case 29:
-    tid = RA;
+    tid = RS1;
     break;
 }

diff --git a/riscv/insns/mtf_d.h b/riscv/insns/mtf_d.h
index 4d3983335fe49dd835fef9e97a797a4cb52ddc09..6777689b948ff6f593df9d512a479cc6d1425bbc 100644 (file)
--- a/riscv/insns/mtf_d.h
+++ b/riscv/insns/mtf_d.h
@@ -1,3 +1,3 @@
 require64;
 require_fp;
-FRC = RA;
+FRDR = RS1;

diff --git a/riscv/insns/mtf_s.h b/riscv/insns/mtf_s.h
index 723a2f704d6a05e77cfd100b7ce17e17405f8737..a1c22fddce956f5606c6f9842358fa6cbda694e2 100644 (file)
--- a/riscv/insns/mtf_s.h
+++ b/riscv/insns/mtf_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRC = RA;
+FRDR = RS1;

diff --git a/riscv/insns/mtflh_d.h b/riscv/insns/mtflh_d.h
index 4e33f399bdefa85ac4c1dc3dfedf13021c30d824..c48c726314bc7ddc92949916707cdfdf67617402 100644 (file)
--- a/riscv/insns/mtflh_d.h
+++ b/riscv/insns/mtflh_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRC = (RA & 0x00000000FFFFFFFF) | (RB << 32);
+FRDR = (RS1 & 0x00000000FFFFFFFF) | (RS2 << 32);

diff --git a/riscv/insns/mtpcr.h b/riscv/insns/mtpcr.h
index 79e28bf4c5c44a36f6bd7a86abef0c523b844657..bcc613a52f27264f4ce7323252789ad71edd27d0 100644 (file)
--- a/riscv/insns/mtpcr.h
+++ b/riscv/insns/mtpcr.h
@@ -1,33 +1,33 @@
 require_supervisor;
 
-switch(insn.rtype.rb)
+switch(insn.rtype.rs2)
 {
   case 0:
-    set_sr(RA);
+    set_sr(RS1);
     break;
   case 1:
-    epc = RA;
+    epc = RS1;
     break;
   case 3:
-    ebase = RA & ~0xFFF;
+    ebase = RS1 & ~0xFFF;
     break;
   case 4:
-    count = RA;
+    count = RS1;
     break;
   case 5:
     interrupts_pending &= ~(1 << TIMER_IRQ);
-    compare = RA;
+    compare = RS1;
     break;
 
   case 16:
-    tohost = RA;
-    sim->set_tohost(RA);
+    tohost = RS1;
+    sim->set_tohost(RS1);
     break;
 
   case 24:
-    pcr_k0 = RA;
+    pcr_k0 = RS1;
     break;
   case 25:
-    pcr_k1 = RA;
+    pcr_k1 = RS1;
     break;
 }

diff --git a/riscv/insns/mul.h b/riscv/insns/mul.h
index 9c81285022b4746fcf57329f5a1b82260f7b25e0..226873f9c883917f468b4b44e056b56d39ba7fc4 100644 (file)
--- a/riscv/insns/mul.h
+++ b/riscv/insns/mul.h
@@ -1,2 +1,2 @@
 require64;
-RC = RA * RB;
+RDR = RS1 * RS2;

diff --git a/riscv/insns/mul_d.h b/riscv/insns/mul_d.h
index d16e6c5e8cd3a305d17acc82a8e760ea7e87c74b..75c7b94da1692c22a35c26540fec1a069eaaff02 100644 (file)
--- a/riscv/insns/mul_d.h
+++ b/riscv/insns/mul_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_mul(FRA, FRB);
+FRDR = f64_mul(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/mul_s.h b/riscv/insns/mul_s.h
index d700d846fa3d23a2533eeedbf1bc55daf82d7077..5c1397c5a1c4f9a65623fb377da6c4318f72edbb 100644 (file)
--- a/riscv/insns/mul_s.h
+++ b/riscv/insns/mul_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_mul(FRA, FRB);
+FRDR = f32_mul(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h
index 2d7ca4ceacdf8315a5b9d58e676c54cb7d1380e8..c4fead2db2537d453494ca2b4dc73f24c988c6d8 100644 (file)
--- a/riscv/insns/mulh.h
+++ b/riscv/insns/mulh.h
@@ -1,4 +1,4 @@
 require64;
-int64_t rb = RA;
-int64_t ra = RB;
-RC = (int128_t(rb) * int128_t(ra)) >> 64;
+int64_t rb = RS1;
+int64_t ra = RS2;
+RDR = (int128_t(rb) * int128_t(ra)) >> 64;

diff --git a/riscv/insns/mulhu.h b/riscv/insns/mulhu.h
index 45e970405c2152d707f7770081c65196b1a888cd..1ce0252e942d8ff2fe143328473a10274292fc55 100644 (file)
--- a/riscv/insns/mulhu.h
+++ b/riscv/insns/mulhu.h
@@ -1,2 +1,2 @@
 require64;
-RC = (uint128_t(RA) * uint128_t(RB)) >> 64;
+RDR = (uint128_t(RS1) * uint128_t(RS2)) >> 64;

diff --git a/riscv/insns/mulhuw.h b/riscv/insns/mulhuw.h
index 9f3de3ff630351c141e45e278c2a413af2f7f297..c2a082d8adf33f5378d9c6569039a9733192dba9 100644 (file)
--- a/riscv/insns/mulhuw.h
+++ b/riscv/insns/mulhuw.h
@@ -1,2 +1,2 @@
-RC = sext32((RA * RB) >> 32);
+RDR = sext32((RS1 * RS2) >> 32);
 

diff --git a/riscv/insns/mulhw.h b/riscv/insns/mulhw.h
index 90a17be019e35341a1c57ca1a3d361b23917955e..7becbfeea07ec3c927250eceed6f3e6b0c9ca7d9 100644 (file)
--- a/riscv/insns/mulhw.h
+++ b/riscv/insns/mulhw.h
@@ -1,2 +1,2 @@
-RC = sext32((sreg_t(RA) * sreg_t(RB)) >> 32);
+RDR = sext32((sreg_t(RS1) * sreg_t(RS2)) >> 32);
 

diff --git a/riscv/insns/mulw.h b/riscv/insns/mulw.h
index d999172c37efcdc8321e6053161ac5918f6ee3e0..c483fb6f87bcc8bbf868dfcaaa0c46d8a58beb72 100644 (file)
--- a/riscv/insns/mulw.h
+++ b/riscv/insns/mulw.h
@@ -1,2 +1,2 @@
-RC = sext32(RA * RB);
+RDR = sext32(RS1 * RS2);
 

diff --git a/riscv/insns/nmadd_d.h b/riscv/insns/nmadd_d.h
index 73ab2bf044fb2845fd2c6141dfe0ed1cb9e52e02..1cdebd32c1bf11172b42831b43099f00fcb96710 100644 (file)
--- a/riscv/insns/nmadd_d.h
+++ b/riscv/insns/nmadd_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_mulAdd(FRA, FRB, FRD) ^ (uint64_t)INT64_MIN;
+FRDR = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN;
 set_fp_exceptions;

diff --git a/riscv/insns/nmadd_s.h b/riscv/insns/nmadd_s.h
index c0603555e8f6215c390b3ba5d068444580010197..b0b70215f4db3a6a63e5f766650ace155be0cdf3 100644 (file)
--- a/riscv/insns/nmadd_s.h
+++ b/riscv/insns/nmadd_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_mulAdd(FRA, FRB, FRD) ^ (uint32_t)INT32_MIN;
+FRDR = f32_mulAdd(FRS1, FRS2, FRS3) ^ (uint32_t)INT32_MIN;
 set_fp_exceptions;

diff --git a/riscv/insns/nmsub_d.h b/riscv/insns/nmsub_d.h
index 0c06f476d0ce8e0bcc1f0f0ead636d2cd4cea1bf..1e010c85bba1365983b995cbbd36a8390d72c268 100644 (file)
--- a/riscv/insns/nmsub_d.h
+++ b/riscv/insns/nmsub_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_mulAdd(FRA, FRB, FRD ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
+FRDR = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
 set_fp_exceptions;

diff --git a/riscv/insns/nmsub_s.h b/riscv/insns/nmsub_s.h
index d9fe109511dc5b6d1b7f5eb01058cc20c00c8a3e..9818dc76fe6d326d5988bac4dd0d259db199c8b4 100644 (file)
--- a/riscv/insns/nmsub_s.h
+++ b/riscv/insns/nmsub_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_mulAdd(FRA, FRB, FRD ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN;
+FRDR = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN;
 set_fp_exceptions;

diff --git a/riscv/insns/nor.h b/riscv/insns/nor.h
index 5bb7e897f02332f3aad0ab60eef0be773867fd66..a3ba7d154c0a546956333e34533dfb4c227e1cda 100644 (file)
--- a/riscv/insns/nor.h
+++ b/riscv/insns/nor.h
@@ -1 +1 @@
-RC = ~(RA | RB);
+RDR = ~(RS1 | RS2);

diff --git a/riscv/insns/or.h b/riscv/insns/or.h
index d88c9f84e7c2c97856ec83b4f436af12c7d85920..ef27ba6f25a0c27606ac9fa120200db9d021bc56 100644 (file)
--- a/riscv/insns/or.h
+++ b/riscv/insns/or.h
@@ -1 +1 @@
-RC = RA | RB;
+RDR = RS1 | RS2;

diff --git a/riscv/insns/ori.h b/riscv/insns/ori.h
index 2fab93710a0cff44f3648cb3af4992b43646f331..d49c8c1ad0cbb29ff93c03160164207a0205112e 100644 (file)
--- a/riscv/insns/ori.h
+++ b/riscv/insns/ori.h
@@ -1 +1 @@
-RA = IMM | RB;
+RDI = IMM | RS1;

diff --git a/riscv/insns/rdnpc.h b/riscv/insns/rdnpc.h
index 95e528a36dcaddcb0e783fab77ca9d1406b8378f..254512cc00ad00c06c34b5128e977886cd649d54 100644 (file)
--- a/riscv/insns/rdnpc.h
+++ b/riscv/insns/rdnpc.h
@@ -1 +1 @@
-RC = npc;
+RDR = npc;

diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h
index dfece4377300350c02b537ded1279db759b6edce..9192428e37519adac62cd422e28490aa20a7f4c1 100644 (file)
--- a/riscv/insns/rem.h
+++ b/riscv/insns/rem.h
@@ -1,2 +1,2 @@
 require64;
-RC = sreg_t(RA) % sreg_t(RB);
+RDR = sreg_t(RS1) % sreg_t(RS2);

diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h
index e8ee6b1a3ee711c1b4f3268fa3237ea2fd885e90..2f40aaa7d6e018c5a046a423633dbc09d4d8d382 100644 (file)
--- a/riscv/insns/remu.h
+++ b/riscv/insns/remu.h
@@ -1,2 +1,2 @@
 require64;
-RC = RA % RB;
+RDR = RS1 % RS2;

diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h
index d028488e9d059cc7baa0ee81b97223cf39ac19a9..26decf20f286829ff1b1a8895f74dc3a442a1daa 100644 (file)
--- a/riscv/insns/remuw.h
+++ b/riscv/insns/remuw.h
@@ -1,2 +1,2 @@
-RC = sext32(uint32_t(RA) % uint32_t(RB));
+RDR = sext32(uint32_t(RS1) % uint32_t(RS2));
 

diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h
index 1bb3051d9692d4d3d7d70fd4bf508cd06225ab0c..83bf1470265104267fb33ddc57b0aeea39855c81 100644 (file)
--- a/riscv/insns/remw.h
+++ b/riscv/insns/remw.h
@@ -1,2 +1,2 @@
-RC = sext32(int32_t(RA) % int32_t(RB));
+RDR = sext32(int32_t(RS1) % int32_t(RS2));
 

diff --git a/riscv/insns/s_d.h b/riscv/insns/s_d.h
index d1c80377b6cebfd04e0372a5403410ebb7ef1c21..4c9c466c653cd47c1766374c54c0b7ec5f7cf2e4 100644 (file)
--- a/riscv/insns/s_d.h
+++ b/riscv/insns/s_d.h
@@ -1,2 +1,2 @@
 require_fp;
-mmu.store_uint64(RB+SIMM, FRA);
+mmu.store_uint64(RS1+SIMM, FRS2);

diff --git a/riscv/insns/s_s.h b/riscv/insns/s_s.h
index 837c2585766655008155dd8e2f70a8db668ab0ac..384246ffda7012bc759287d5674c98bf32895369 100644 (file)
--- a/riscv/insns/s_s.h
+++ b/riscv/insns/s_s.h
@@ -1,2 +1,2 @@
 require_fp;
-mmu.store_uint32(RB+SIMM, FRA);
+mmu.store_uint32(RS1+SIMM, FRS2);

diff --git a/riscv/insns/sb.h b/riscv/insns/sb.h
index 618140d3b03fca8c619809ba6fd41b3c78f01974..5a2110fccc4fe10e2595366674976d7e82d994f6 100644 (file)
--- a/riscv/insns/sb.h
+++ b/riscv/insns/sb.h
@@ -1 +1 @@
-mmu.store_uint8(RB+SIMM, RA);
+mmu.store_uint8(RS1+SIMM, RS2);

diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h
index 6a698ee8f7e34942c9685cc8f066ea47c95ba819..587df8df47ce21f621d1bb2203e85fb67e58550d 100644 (file)
--- a/riscv/insns/sd.h
+++ b/riscv/insns/sd.h
@@ -1,2 +1,2 @@
 require64;
-mmu.store_uint64(RB+SIMM, RA);
+mmu.store_uint64(RS1+SIMM, RS2);

diff --git a/riscv/insns/sgninj_d.h b/riscv/insns/sgninj_d.h
index 8bca56a8614b639125f03f0dbc903cb927739f31..b1722da9dea74fdd2fa7d26d73d4050c40a772ef 100644 (file)
--- a/riscv/insns/sgninj_d.h
+++ b/riscv/insns/sgninj_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRC = (FRA &~ INT64_MIN) | (FRB & INT64_MIN);
+FRDR = (FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN);

diff --git a/riscv/insns/sgninj_s.h b/riscv/insns/sgninj_s.h
index b68817711c0ed9cf60270b5d7d8c6d7e293b4d88..2df0b94a0e654535b2815f5c5e221cdb4606746f 100644 (file)
--- a/riscv/insns/sgninj_s.h
+++ b/riscv/insns/sgninj_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRC = (FRA &~ (uint32_t)INT32_MIN) | (FRB & (uint32_t)INT32_MIN);
+FRDR = (FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN);

diff --git a/riscv/insns/sgninjn_d.h b/riscv/insns/sgninjn_d.h
index c526735a3806161e1ad2339de3a46e4d50738ff7..90c7ae9bd9d2fae7744b274eb09e88aa1b13bd62 100644 (file)
--- a/riscv/insns/sgninjn_d.h
+++ b/riscv/insns/sgninjn_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRC = (FRA &~ INT64_MIN) | ((~FRB) & INT64_MIN);
+FRDR = (FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN);

diff --git a/riscv/insns/sgninjn_s.h b/riscv/insns/sgninjn_s.h
index 80dd7e875396276a6581b30759c4a9790c94f2b6..7be7b46623cacf406680306f65597947d84b3dae 100644 (file)
--- a/riscv/insns/sgninjn_s.h
+++ b/riscv/insns/sgninjn_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRC = (FRA &~ (uint32_t)INT32_MIN) | ((~FRB) & (uint32_t)INT32_MIN);
+FRDR = (FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN);

diff --git a/riscv/insns/sgnmul_d.h b/riscv/insns/sgnmul_d.h
index c30dcea5b9d2fad8e1d557785d0d0d95e93926c1..8e558506c815daf54d24f950af90818b21326d92 100644 (file)
--- a/riscv/insns/sgnmul_d.h
+++ b/riscv/insns/sgnmul_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRC = FRA ^ (FRB & INT64_MIN);
+FRDR = FRS1 ^ (FRS2 & INT64_MIN);

diff --git a/riscv/insns/sgnmul_s.h b/riscv/insns/sgnmul_s.h
index 6640b3126ebe372ce4deeace18b9e6c40d612427..e651888f0d47035217273d07dda6da9a0c105497 100644 (file)
--- a/riscv/insns/sgnmul_s.h
+++ b/riscv/insns/sgnmul_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRC = FRA ^ (FRB & (uint32_t)INT32_MIN);
+FRDR = FRS1 ^ (FRS2 & (uint32_t)INT32_MIN);

diff --git a/riscv/insns/sh.h b/riscv/insns/sh.h
index e0fdc0a4070fa5a65d38de769c41a8ad437523a4..bbc2bda3f8ca59f6e0bf544ea20a2a5984fce318 100644 (file)
--- a/riscv/insns/sh.h
+++ b/riscv/insns/sh.h
@@ -1 +1 @@
-mmu.store_uint16(RB+SIMM, RA);
+mmu.store_uint16(RS1+SIMM, RS2);

diff --git a/riscv/insns/sll.h b/riscv/insns/sll.h
index 7e81e6b68b45a278591a6bd73ebb0e5c8613b3de..59da49de6f92a6abcb1e03f76088fd6351f7207b 100644 (file)
--- a/riscv/insns/sll.h
+++ b/riscv/insns/sll.h
@@ -1,2 +1,2 @@
 require64;
-RC = RB << (RA & 0x3F);
+RDR = RS2 << (RS1 & 0x3F);

diff --git a/riscv/insns/slli.h b/riscv/insns/slli.h
index 606512b7fea74b89c6ec3e63123835495980c03b..33e23aa39411bb525093f7274ace2f913da1acb1 100644 (file)
--- a/riscv/insns/slli.h
+++ b/riscv/insns/slli.h
@@ -1,2 +1,2 @@
 require64;
-RA = RB << SHAMT;
+RDI = RS1 << SHAMT;

diff --git a/riscv/insns/slliw.h b/riscv/insns/slliw.h
index c8b345c826e8bcf9900cd2e21ca35babb40a2a85..85469772cb43fc0e9decd3fbab85e339cc1e89a9 100644 (file)
--- a/riscv/insns/slliw.h
+++ b/riscv/insns/slliw.h
@@ -1 +1 @@
-RA = sext32(RB << SHAMTW);
+RDI = sext32(RS1 << SHAMTW);

diff --git a/riscv/insns/sllw.h b/riscv/insns/sllw.h
index f694a2ff3ce019a24881f8d528c200f08107ecfe..3d96b0fb21ce02a7dead68d78707527b8222cc4c 100644 (file)
--- a/riscv/insns/sllw.h
+++ b/riscv/insns/sllw.h
@@ -1 +1 @@
-RC = sext32(RB << (RA & 0x1F));
+RDR = sext32(RS2 << (RS1 & 0x1F));

diff --git a/riscv/insns/slt.h b/riscv/insns/slt.h
index ccc1d447ea6deac67f9aedf67af49d2b02918153..6511f42c838485013e8034f473fd034cc5d98597 100644 (file)
--- a/riscv/insns/slt.h
+++ b/riscv/insns/slt.h
@@ -1 +1 @@
-RC = sreg_t(cmp_trunc(RA)) < sreg_t(cmp_trunc(RB));
+RDR = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2));

diff --git a/riscv/insns/slti.h b/riscv/insns/slti.h
index a5ef31ed09d5572306411ae4f89ba375b12b0f9f..6204619a73c5cedf2e44dbbf757f7e3e5f5a2ed8 100644 (file)
--- a/riscv/insns/slti.h
+++ b/riscv/insns/slti.h
@@ -1 +1 @@
-RA = sreg_t(cmp_trunc(RB)) < sreg_t(cmp_trunc(SIMM));
+RDI = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(SIMM));

diff --git a/riscv/insns/sltiu.h b/riscv/insns/sltiu.h
index a09f3ecb5572d38a9ebd5db76e2a640b786f197c..b7c8ce64f10cd1c9e3bfb3c6242a8d56f66ce1aa 100644 (file)
--- a/riscv/insns/sltiu.h
+++ b/riscv/insns/sltiu.h
@@ -1 +1 @@
-RA = cmp_trunc(RB) < cmp_trunc(SIMM);
+RDI = cmp_trunc(RS1) < cmp_trunc(SIMM);

diff --git a/riscv/insns/sltu.h b/riscv/insns/sltu.h
index 32fc94d3b05967752e0a41b75bfc4af2b76d1a05..1d4ebe65f46d85c577bc3066d85c63736bf09ffe 100644 (file)
--- a/riscv/insns/sltu.h
+++ b/riscv/insns/sltu.h
@@ -1 +1 @@
-RC = cmp_trunc(RA) < cmp_trunc(RB);
+RDR = cmp_trunc(RS1) < cmp_trunc(RS2);

diff --git a/riscv/insns/sqrt_d.h b/riscv/insns/sqrt_d.h
index fdfc19aaa8c7a0ec24addeb17d10aecba15a642c..99ffa18089203a510ab4dd86f34462d289f61073 100644 (file)
--- a/riscv/insns/sqrt_d.h
+++ b/riscv/insns/sqrt_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_sqrt(FRA);
+FRDR = f64_sqrt(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/sqrt_s.h b/riscv/insns/sqrt_s.h
index 5f2968c39740d3b50347d541f9c72155e96c0a32..12c8160b6918c777eda9ad5df990f545a0430c2f 100644 (file)
--- a/riscv/insns/sqrt_s.h
+++ b/riscv/insns/sqrt_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_sqrt(FRA);
+FRDR = f32_sqrt(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/sra.h b/riscv/insns/sra.h
index e01fcd58ebbf8623cc314f463946bfae6dfe9a90..6dfde0f49decdea983043473f1a1a4a4044c16e2 100644 (file)
--- a/riscv/insns/sra.h
+++ b/riscv/insns/sra.h
@@ -1,2 +1,2 @@
 require64;
-RC = sreg_t(RB) >> (RA & 0x3F);
+RDR = sreg_t(RS2) >> (RS1 & 0x3F);

diff --git a/riscv/insns/srai.h b/riscv/insns/srai.h
index 12a67a3b057844ce7f24addb1c7eb2f051e25ce3..b2026bb5c9486899dbb41b1e91990e9f53fb73c1 100644 (file)
--- a/riscv/insns/srai.h
+++ b/riscv/insns/srai.h
@@ -1,2 +1,2 @@
 require64;
-RA = sreg_t(RB) >> SHAMT;
+RDI = sreg_t(RS1) >> SHAMT;

diff --git a/riscv/insns/sraiw.h b/riscv/insns/sraiw.h
index 7289347f984d2a173c4f883c201e7be63b3f31c5..0831b1428d00d75caf01b371b02d7c1582b19a6a 100644 (file)
--- a/riscv/insns/sraiw.h
+++ b/riscv/insns/sraiw.h
@@ -1 +1 @@
-RA = sext32(sreg_t(RB) >> SHAMTW);
+RDI = sext32(sreg_t(RS1) >> SHAMTW);

diff --git a/riscv/insns/sraw.h b/riscv/insns/sraw.h
index 8e9aa8825f14dd27ffccb400ad539282fa940ea0..111f6328aeff8b4d4911796246ec7278bc69f9bb 100644 (file)
--- a/riscv/insns/sraw.h
+++ b/riscv/insns/sraw.h
@@ -1 +1 @@
-RC = sext32(sreg_t(RB) >> (RA & 0x1F));
+RDR = sext32(sreg_t(RS2) >> (RS1 & 0x1F));

diff --git a/riscv/insns/srl.h b/riscv/insns/srl.h
index ec6fee88a0b2c8532a1706d7339925d5d39996ec..1512be95135b2872266343ed9a5a78c571fd2475 100644 (file)
--- a/riscv/insns/srl.h
+++ b/riscv/insns/srl.h
@@ -1,2 +1,2 @@
 require64;
-RC = RB >> (RA & 0x3F);
+RDR = RS2 >> (RS1 & 0x3F);

diff --git a/riscv/insns/srli.h b/riscv/insns/srli.h
index d7bc2b418490f3e847758c1ce252e3d9cfbd6bf7..29a97a2e51254d0aced63050cbf5e1dc162048a4 100644 (file)
--- a/riscv/insns/srli.h
+++ b/riscv/insns/srli.h
@@ -1,2 +1,2 @@
 require64;
-RA = RB >> SHAMT;
+RDI = RS1 >> SHAMT;

diff --git a/riscv/insns/srliw.h b/riscv/insns/srliw.h
index 6534a890851c25bc90b972f65dd325e6c695ebc7..5513a5a403402e20db90e026ff236a5c837f223f 100644 (file)
--- a/riscv/insns/srliw.h
+++ b/riscv/insns/srliw.h
@@ -1 +1 @@
-RA = sext32((uint32_t)RB >> SHAMTW);
+RDI = sext32((uint32_t)RS1 >> SHAMTW);

diff --git a/riscv/insns/srlw.h b/riscv/insns/srlw.h
index c523b59dbe1bc55a3d0cd367ce0db3dc3ad8cc97..2d9de89f968653864bd94cb8551e526a6dc1f958 100644 (file)
--- a/riscv/insns/srlw.h
+++ b/riscv/insns/srlw.h
@@ -1 +1 @@
-RC = sext32((uint32_t)RB >> (RA & 0x1F));
+RDR = sext32((uint32_t)RS2 >> (RS1 & 0x1F));

diff --git a/riscv/insns/sub.h b/riscv/insns/sub.h
index e7ac407639435d582f7aa08ad9b08a27e0d19e54..005b66f4c3d9baae2749525b3e8d6338d696551c 100644 (file)
--- a/riscv/insns/sub.h
+++ b/riscv/insns/sub.h
@@ -1,2 +1,2 @@
 require64;
-RC = RA - RB;
+RDR = RS1 - RS2;

diff --git a/riscv/insns/sub_d.h b/riscv/insns/sub_d.h
index 023a1f324f2770080345f0d81bf4fd3a0922efa6..20997325c2f3c784cdbb47490fc45bd676ceb2b2 100644 (file)
--- a/riscv/insns/sub_d.h
+++ b/riscv/insns/sub_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_sub(FRA, FRB);
+FRDR = f64_sub(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/sub_s.h b/riscv/insns/sub_s.h
index fd83da031b63a2f38862cbde04de2a598b61fd62..e28f042dbfc5218020b7ce6ed92213859426e92b 100644 (file)
--- a/riscv/insns/sub_s.h
+++ b/riscv/insns/sub_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_sub(FRA, FRB);
+FRDR = f32_sub(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/subw.h b/riscv/insns/subw.h
index 60bcf27befc5603c0f4a1c19fbfeebba539f0292..9dd7114206908d739727e6c70b36c4943e05f222 100644 (file)
--- a/riscv/insns/subw.h
+++ b/riscv/insns/subw.h
@@ -1,2 +1,2 @@
-RC = sext32(RA - RB);
+RDR = sext32(RS1 - RS2);
 

diff --git a/riscv/insns/sw.h b/riscv/insns/sw.h
index b4e3b3d7b4c171cc90e6f744bf7235beee774af5..e644e16d611a451c80938180aae24a2f1c390346 100644 (file)
--- a/riscv/insns/sw.h
+++ b/riscv/insns/sw.h
@@ -1 +1 @@
-mmu.store_uint32(RB+SIMM, RA);
+mmu.store_uint32(RS1+SIMM, RS2);

diff --git a/riscv/insns/trunc_l_d.h b/riscv/insns/trunc_l_d.h
index 0fad400c10cd33dedfbfb4a04aef78490ba40b74..e71957bfdf4b9b584edd67f29488b55768129823 100644 (file)
--- a/riscv/insns/trunc_l_d.h
+++ b/riscv/insns/trunc_l_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_to_i64_r_minMag(FRA,true);
+FRDR = f64_to_i64_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/trunc_l_s.h b/riscv/insns/trunc_l_s.h
index 5d5a9408e31b70d89c7f613ca63cda865572011d..1d48192162e191541c673f91ebe0c41e4eeb2dad 100644 (file)
--- a/riscv/insns/trunc_l_s.h
+++ b/riscv/insns/trunc_l_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_to_i64_r_minMag(FRA,true);
+FRDR = f32_to_i64_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/trunc_w_d.h b/riscv/insns/trunc_w_d.h
index b91640a3ac59c91f72fdcaa5919bf72f38660782..2fea3dcadf656b075e21a50ad0071ffcc81065b5 100644 (file)
--- a/riscv/insns/trunc_w_d.h
+++ b/riscv/insns/trunc_w_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_to_i32_r_minMag(FRA,true);
+FRDR = f64_to_i32_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/trunc_w_s.h b/riscv/insns/trunc_w_s.h
index 73974d1f28362ddf457913d35ebebde7d2a0077d..e70f9c4795c1009289198b111965db50351ebaf4 100644 (file)
--- a/riscv/insns/trunc_w_s.h
+++ b/riscv/insns/trunc_w_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_to_i32_r_minMag(FRA,true);
+FRDR = f32_to_i32_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/truncu_l_d.h b/riscv/insns/truncu_l_d.h
index 0fad400c10cd33dedfbfb4a04aef78490ba40b74..e71957bfdf4b9b584edd67f29488b55768129823 100644 (file)
--- a/riscv/insns/truncu_l_d.h
+++ b/riscv/insns/truncu_l_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_to_i64_r_minMag(FRA,true);
+FRDR = f64_to_i64_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/truncu_l_s.h b/riscv/insns/truncu_l_s.h
index 5d5a9408e31b70d89c7f613ca63cda865572011d..1d48192162e191541c673f91ebe0c41e4eeb2dad 100644 (file)
--- a/riscv/insns/truncu_l_s.h
+++ b/riscv/insns/truncu_l_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_to_i64_r_minMag(FRA,true);
+FRDR = f32_to_i64_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/truncu_w_d.h b/riscv/insns/truncu_w_d.h
index 255fba550a6577d565ed5b7829e47bdc9d63296c..bb674f6af2a85d1ff69c3a23a7ced1e40f9b4308 100644 (file)
--- a/riscv/insns/truncu_w_d.h
+++ b/riscv/insns/truncu_w_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_to_ui32_r_minMag(FRA,true);
+FRDR = f64_to_ui32_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/truncu_w_s.h b/riscv/insns/truncu_w_s.h
index 337b9ea1e1de3a210e10aac5652bccee41940765..d85f9e5a93562708b6e33e2f979a91344b3de375 100644 (file)
--- a/riscv/insns/truncu_w_s.h
+++ b/riscv/insns/truncu_w_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_to_ui32_r_minMag(FRA,true);
+FRDR = f32_to_ui32_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/xor.h b/riscv/insns/xor.h
index 9d024472359e340b3f5083aa366263d3a71bb7e6..f11738a05b1e144c913a06a64994a5fc0f9fe881 100644 (file)
--- a/riscv/insns/xor.h
+++ b/riscv/insns/xor.h
@@ -1 +1 @@
-RC = RA ^ RB;
+RDR = RS1 ^ RS2;

diff --git a/riscv/insns/xori.h b/riscv/insns/xori.h
index 5ca46377d7386f9ba59e10d6660906c38928c0a2..fcf90429a264b3dce641961cab225aad2d96e9ad 100644 (file)
--- a/riscv/insns/xori.h
+++ b/riscv/insns/xori.h
@@ -1 +1 @@
-RA = IMM ^ RB;
+RDI = IMM ^ RS1;